coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 785e47b rmodtool: add support for ARM
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit 785e47bbf3125d86632c16584a974d1c180a989a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 20 11:08:02 2014 -0500 rmodtool: add support for ARM Add support for creating ARM rmodules. There are 3 expected relocations for an ARM rmodule: - R_ARM_ABS32 - R_ARM_THM_PC22 - R_ARM_THM_JUMP24 R_ARM_ABS32 is the only type that needs to emitted for relocation as the other 2 are relative relocations. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built vbootstub for ARM device. Original-Change-Id: I0c22d4abca970e82ccd60b33fed700b96e3e52fb Original-Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190922 Original-Reviewed-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit a642102ba7ace5c1829abe7732199eda6646950a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib3b3c90ebb672d8d6a537df896b97dc82c6186cc Reviewed-on: http://review.coreboot.org/7204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7204 for details. -gerrit

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Patch merged into coreboot/master: 25ae602 rambi: switch MCLK from 19.2Mhz to 25Mhz
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit 25ae602d2edb9426f94fe5fee26665d498f7fd9e Author: Kein Yuan <kein.yuan(a)intel.com> Date: Fri Apr 4 15:15:14 2014 -0700 rambi: switch MCLK from 19.2Mhz to 25Mhz With following settings 1.Coreboot 25Mhz 2.Maxim codec configured with MCLK=25Mhz 2.I2C 400Khz fixed 4.Including Enable/Disable SHDN bit when LRCLK starts/Stops 5.Removed PLL toggle workaround routine. audio playing is smooth before/after S3, no noise when recording so change MCLK from 19.2 back to 25Mhz. BUG=chrome-os-partner:26948 BRANCH=firmware-rambi-5216 TEST=test audio play and record on Rambi, works fine. Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6 Signed-off-by: Kein Yuan <kein.yuan(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/193881 Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7219 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7219 for details. -gerrit

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Patch merged into coreboot/master: dd20d5d baytrail: Remove unused devicetree fields
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit dd20d5d36cc5350e834cad4052d9376bd29928a1 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Apr 9 12:45:57 2014 -0700 baytrail: Remove unused devicetree fields We're no longer configuring hotplug + backlight settings from devicetree, so remove these entries + fields. BUG=chrome-os-partner:27304 TEST=Compile only. BRANCH=rambi+squawks Change-Id: I7e27fbc070a9ea774e7dcbe551d61b1b1682a47f Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193831 (cherry picked from commit 4ab13fd3aa2634673bb099bdfd714a21adc3caa0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7218 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7218 for details. -gerrit

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Patch merged into coreboot/master: b959079 baytrail: gfx: Don't configure hotplug + backlight registers
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit b9590799b3aad8ef788f2c9afd7f6c2311ab169b Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Apr 9 12:41:22 2014 -0700 baytrail: gfx: Don't configure hotplug + backlight registers - The hotplug register doesn't work in the way we describe. Just leave it at default. - The backlight registers will be configured by the OS driver. BUG=chrome-os-partner:27304 TEST=Manual on Rambi. Boot system in both dev and normal mode, verify that display comes up. Also verify that display functions after warm reboot and suspend / resume. BRANCH=rambi+squawks Change-Id: I5559c131f41c4a14e64e5cec66e18d3a4a46092c Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193830 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 3f287cc31e41fabef755c37361e2e65ca413c88c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/7217 for details. -gerrit

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Patch merged into coreboot/master: 1d07bf2 rambi: always show dev/rec screens on eDP connected panel
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit 1d07bf2609b506fe9782dd3fcfe544da07c9a859 Author: Kein Yuan <kein.yuan(a)intel.com> Date: Tue Apr 1 10:13:38 2014 -0700 rambi: always show dev/rec screens on eDP connected panel bit: 7 6 5 4 3 2 1 0 LFP2 EFP2 EFP3 CRT2 LFP EFP TV CRT so int 15 0x5f35 need to return 0x8(LFP/eDP) instead of 0x2(TV). BUG=chrome-os-partner:26365 BUG=chrome-os-partner:27505 BRANCH=rambi TEST=Booted with and without HDMI connected monitor. DEV screen always showed on eDP panel on Rambi. Change-Id: I8f876e78383424f517689eb25e9229a27739957b Original-Change-Id: I77edbeb3c86549f90302b4296b5a2f50313ca675 Signed-off-by: Kein Yuan <kein.yuan(a)intle.com> Reviewed-on: https://chromium-review.googlesource.com/193303 Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit dd375462147f182331f336ba826108e58b4e0a47) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7216 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/7216 for details. -gerrit

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Patch merged into coreboot/master: 787809e Baytrail/dptf: Always return 0 in TCPU._PPC
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit 787809e9ab117475847e8b2daf0c70e3cfff6ff4 Author: Kein Yuan <kein.yuan(a)intel.com> Date: Wed Apr 2 16:29:52 2014 -0700 Baytrail/dptf: Always return 0 in TCPU._PPC According to DPTF team _PPC in TCPU must return 0 always. BUG=chromium:355964 TEST=Pass build. BRANCH=rambi Change-Id: I76f0da27757ba4717f0e392bcd80e890d925061a Original-Change-Id: I8b9e17e5479e8a226cb11cd43ce888a3e4dead73 Signed-off-by: Kein Yuan <kein.yuan(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/193069 Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit 6dbcc677ceebbaf832e41e6db1e6cf171e2e231f) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/7215 for details. -gerrit

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Patch merged into coreboot/master: 1131889 baytrail: handle MRC being an ELF file
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit 1131889570836da2ee63f5eacb46ce31d3a55276 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 2 20:46:13 2014 -0500 baytrail: handle MRC being an ELF file Provide the option to embed MRC as an ELF file and not just binary blob. This allows for MRC to be relocated. BUG=chrome-os-partner:27654 BRANCH=rambi TEST=Built and booted rambi. Change-Id: I2e177c155a3074e4e1d450b1a73b7299aebd5286 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192893 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit 89c97d5e2023b8c5cc780e1b1d532d0a586512f9) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7214 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7214 for details. -gerrit

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Patch merged into coreboot/master: 31ac9e3 baytrail: Configure MSR for 2-core and 4-core P-state configutation
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit 31ac9e3a9a53523ad342af55b9a20c3c51cd927a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 28 10:52:13 2014 -0700 baytrail: Configure MSR for 2-core and 4-core P-state configutation Suggested settings to try for performace regression: 2-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFE (HW_ALL) 4-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFC (SW_ALL) BUG=chrome-os-partner:26211 BRANCH=baytrail TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib68a86525204ae47a820c269257a7b8df9300a6a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192573 Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit 8c8c0be0000043610eaa56926eff978f352819b8) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7213 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/7213 for details. -gerrit

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Patch merged into coreboot/master: 89f5292 baytrail: move cache-as-ram base address to 0xfe000000
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit 89f5292ee63cb6f387c06bfbdb4343cc675bc938 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 19 11:48:33 2014 -0500 baytrail: move cache-as-ram base address to 0xfe000000 Moving the cache-as-ram base address to 0xfe000000 will provide more breathing room in the physical address space. It will also allow for larger SPI roms in the future. BUG=chrome-os-partner:27045 BRANCH=baytrail CQ-DEPEND=CL:*157278 TEST=Built and booted. Suspended and resumes. Vboot works, MRC settings are being saved as well. Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190700 Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit 73c07a319d678f3e9be2fac64599c94f91c9ad9c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/7212 for details. -gerrit

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Patch merged into coreboot/master: 565d409 baytrail: romstage: Add function to check SW WP status for vboot
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit 565d409753a9878fef19eedc4a916d1efc3026a0 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Mar 14 14:06:45 2014 -0700 baytrail: romstage: Add function to check SW WP status for vboot Implement vboot_get_sw_write_protect, which returns the FW SPI ROM SW WP status. BUG=chrome-os-partner:26777 TEST=Manual on Rambi with all patches in sequence: `crossystem sw_wpsw_boot` prints 0 `flashrom --wp-enable` + reboot `crossystem sw_wpsw_boot` prints 1 BRANCH=Rambi Original-Change-Id: I5da35c1b2d25b8679bf0084af65d08de224387f8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190097 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 5bba447654417c42952c49542ed047b4867d04d1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I739cbb8fca5f02462cf78c81f9b364aabfd3fe86 Reviewed-on: http://review.coreboot.org/7211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/7211 for details. -gerrit

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coreboot-gerrit October 2014