coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 7b14c61 intel/sandybridge: Add PCI ID for northbridge 0x150
by Damien Zammit 28 Oct '14

28 Oct '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7233 -gerrit commit 7b14c61d322cdf0bb8871510b667bb709455c6a6 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Oct 29 00:11:53 2014 +1100 intel/sandybridge: Add PCI ID for northbridge 0x150 Change-Id: I335244b7c39d6ddff6ecb06cb823fee09e35ee26 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/sandybridge/northbridge.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 9331afa..7d2a4bd 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -465,6 +465,12 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; +static const struct pci_driver mc_driver_150 __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0150, /* Ivy bridge i3 */ +}; + static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); @@ -493,6 +499,6 @@ static void enable_dev(device_t dev) } struct chip_operations northbridge_intel_sandybridge_ops = { - CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge") + CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge") .enable_dev = enable_dev, };

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Patch set updated for coreboot: 11f42cf gigabyte/ga-b75m-d3h: Add new Intel mainboard
by Damien Zammit 28 Oct '14

28 Oct '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7020 -gerrit commit 11f42cf4dd90799bb1316df8de9c4b05623d3cfa Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Oct 23 22:06:38 2014 +1100 gigabyte/ga-b75m-d3h: Add new Intel mainboard This is based on LENOVO X230 port. Board boots to linux via SATA. Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM still hangs when run in SeaBIOS 3. USB does not work. SeaBIOS/GRUB2 do not detect devices connected to USB ports 4. Sound needs corrected codec verb settings Change-Id: Ib465a4824ef1a71ab6aa17bd40fc281215c6d44f Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/Kconfig | 3 + src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 75 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 21 ++ src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl | 1 + .../gigabyte/ga-b75m-d3h/acpi/mainboard.asl | 28 ++ .../gigabyte/ga-b75m-d3h/acpi/platform.asl | 73 ++++++ .../gigabyte/ga-b75m-d3h/acpi/superio.asl | 24 ++ .../gigabyte/ga-b75m-d3h/acpi/thermal.asl | 65 +++++ src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl | 1 + src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 83 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt | 6 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.default | 9 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout | 152 +++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 87 +++++++ src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 54 ++++ src/mainboard/gigabyte/ga-b75m-d3h/fadt.c | 167 ++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/gpio.c | 283 +++++++++++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c | 252 ++++++++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 110 ++++++++ src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c | 109 ++++++++ src/mainboard/gigabyte/ga-b75m-d3h/onboard.h | 25 ++ src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 208 +++++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/thermal.h | 30 +++ src/southbridge/intel/bd82x6x/early_usb_native.c | 2 +- 24 files changed, 1867 insertions(+), 1 deletion(-) diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index ff96a17..c46b979 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -27,6 +27,8 @@ config BOARD_GIGABYTE_GA_6BXC bool "GA-6BXC" config BOARD_GIGABYTE_GA_6BXE bool "GA-6BXE" +config BOARD_GIGABYTE_GA_B75M_D3H + bool "GA-B75M-D3H" config BOARD_GIGABYTE_M57SLI bool "GA-M57SLI-S4" config BOARD_GIGABYTE_MA785GMT @@ -41,6 +43,7 @@ endchoice source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig" source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/ga-6bxe/Kconfig" +source "src/mainboard/gigabyte/ga-b75m-d3h/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" source "src/mainboard/gigabyte/ma785gmt/Kconfig" source "src/mainboard/gigabyte/ma785gm/Kconfig" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig new file mode 100644 index 0000000..85e9ec2 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -0,0 +1,75 @@ +if BOARD_GIGABYTE_GA_B75M_D3H + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA1155 + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select INTEL_INT15 + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS + select UDELAY_TSC + select EARLY_CBMEM_INIT + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAINBOARD_DIR + string + default gigabyte/ga-b75m-d3h + +config MAINBOARD_PART_NUMBER + string + default "GA-B75M-D3H" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +# No need to override the chipset VGA_BIOS_ID. +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config IFD_BIOS_SECTION + string + default "0x00600000:0x007fffff" + +config IFD_ME_SECTION + string + default "0x00001000:0x004fffff" + +# UNCOMMENT BELOW WHEN YOU BUILD WITH REAL ME IMAGE +#config IFD_GBE_SECTION +# string +# default "0x00fff000:0x00000fff" + +endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc new file mode 100644 index 0000000..a2efadd --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl new file mode 100644 index 0000000..09cff9a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl new file mode 100644 index 0000000..1448aeb --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl new file mode 100644 index 0000000..753fc29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ + +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // Enable PS/2 Mouse + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl new file mode 100644 index 0000000..f71611a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 10 seconds + Name (_TSP, 100) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c new file mode 100644 index 0000000..73b1c11 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt new file mode 100644 index 0000000..312f6ef --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default new file mode 100644 index 0000000..21d75e5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default @@ -0,0 +1,9 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +sata_mode=AHCI +hyper_threading=Enable diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout new file mode 100644 index 0000000..7c8af49 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -0,0 +1,152 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 2 r 0 unused + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb new file mode 100644 index 0000000..bd9cdf6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -0,0 +1,87 @@ +chip northbridge/intel/sandybridge + + # Enable DVI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + device cpu_cluster 0 on + chip cpu/intel/socket_LGA1155 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + end + end + + device domain 0 on + subsystemid 0x1458 0x5000 inherit + device pci 00.0 on end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + + # GPI routing + register "alt_gp_smi_en" = "0x0000" + + # Set max SATA speed to 6.0 Gb/s + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + register "gen1_dec" = "0x003c0a01" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + device pci 14.0 off end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 on end # PCI bridge (ethernet here) + device pci 1f.0 on # ISA/LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 9 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x0 + io 0x62 = 0xa00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.a off end # IR + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl new file mode 100644 index 0000000..3209963 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include "acpi/thermal.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/fadt.c b/src/mainboard/gigabyte/ga-b75m-d3h/fadt.c new file mode 100644 index 0000000..8104d22 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/fadt.c @@ -0,0 +1,167 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ +#define APM_CNT 0xb2 +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x80 +#define ACPI_DISABLE 0x1e +#define ACPI_ENABLE 0xe1 +#define GNVS_UPDATE 0xea + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), + 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_DESKTOP; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = ACPI_ENABLE; + fadt->acpi_disable = ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c new file mode 100644 index 0000000..9b93c9a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c @@ -0,0 +1,283 @@ +#include "southbridge/intel/bd82x6x/gpio.h" +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /*1GPIO0 */ + .gpio1 = GPIO_MODE_GPIO, /*0SIO_EXT_SMI# */ + .gpio2 = GPIO_MODE_GPIO, /*1NOT USED */ + .gpio3 = GPIO_MODE_GPIO, /*1NOT USED */ + .gpio4 = GPIO_MODE_GPIO, /*1NOT USED */ + .gpio5 = GPIO_MODE_GPIO, /*0INTH# */ + .gpio6 = GPIO_MODE_GPIO, /*0SIO_EXT_SCI# */ + .gpio7 = GPIO_MODE_GPIO, /*1GE_SCR_WP# */ + .gpio8 = GPIO_MODE_GPIO, /*0NOT USED */ + .gpio9 = GPIO_MODE_NATIVE, /*1USB_OC5# */ + .gpio10 = GPIO_MODE_NATIVE, /*1USB_OC6# */ + .gpio11 = GPIO_MODE_NATIVE, /*0SMBALERT# */ + .gpio12 = GPIO_MODE_GPIO, /*1GPIO12 */ + .gpio13 = GPIO_MODE_GPIO, /*0GPIO13 */ + .gpio14 = GPIO_MODE_NATIVE, /*1USB_OC7# */ + .gpio15 = GPIO_MODE_GPIO, /*1GPIO15 */ + .gpio16 = GPIO_MODE_GPIO, /*1WWAN_LED_ON */ + .gpio17 = GPIO_MODE_GPIO, /*0WLAN_LED_ON */ + .gpio18 = GPIO_MODE_NATIVE, /*1PCIE_CLKREQ_WLAN# */ + .gpio19 = GPIO_MODE_GPIO, /*1BBS_BIT0 */ + .gpio20 = GPIO_MODE_NATIVE, /*0PCIE_CLKREQ_CARD# */ + .gpio21 = GPIO_MODE_GPIO, /*0BT_DET# / TP29 */ + .gpio22 = GPIO_MODE_GPIO, /*0MODEL_ID0 */ + .gpio23 = GPIO_MODE_NATIVE, /*1LCD_BK_OFF */ + .gpio24 = GPIO_MODE_GPIO, /*1GPIO24 */ + .gpio25 = GPIO_MODE_NATIVE, /*1PCIE_REQ_WWAN# / TP89 */ + .gpio26 = GPIO_MODE_NATIVE, /*1CLK_PCIE_REQ4# / TP59 */ + .gpio27 = GPIO_MODE_GPIO, /*1MSATA_DTCT# */ + .gpio28 = GPIO_MODE_GPIO, /*1PLL_ODVR_EN */ + .gpio29 = GPIO_MODE_GPIO, /*1WLAN_AOAC_ON */ + .gpio30 = GPIO_MODE_NATIVE, /*1SUS_PWR_ACK */ + .gpio31 = GPIO_MODE_GPIO, /*1AC_PRESENT */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, /* PCI_CLKRUN# */ + .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ + .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ + .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ + .gpio36 = GPIO_MODE_GPIO, /* NOT USED */ + .gpio37 = GPIO_MODE_GPIO, /* NOT USED */ + .gpio38 = GPIO_MODE_GPIO, /* NOT USED */ + .gpio39 = GPIO_MODE_GPIO, /* NOT USED */ + .gpio40 = GPIO_MODE_NATIVE, /* USB_OC1# */ + .gpio41 = GPIO_MODE_NATIVE, /* USB_OC2# */ + .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ + .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ + .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ + .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ + .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ + .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ + .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ + .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ + .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ + .gpio51 = GPIO_MODE_NATIVE, /* BBS_BIT1 */ + .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ + .gpio53 = GPIO_MODE_NATIVE, /* PWM_SELECT# / TP44 */ + .gpio54 = GPIO_MODE_NATIVE, /* PCI_REQ3# */ + .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ + .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ + .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ + .gpio59 = GPIO_MODE_NATIVE, /* USB_OC0_1# */ + .gpio60 = GPIO_MODE_NATIVE, /* DRAMRST_CNTRL_PCH */ + .gpio61 = GPIO_MODE_NATIVE, /* LPCPD# */ + .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ + .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, /* CLK_FLEX0 / TP38 */ + .gpio65 = GPIO_MODE_NATIVE, /* CLK_FLEX1 / TP45 */ + .gpio66 = GPIO_MODE_NATIVE, /* CLK_FLEX2 / TP83 */ + .gpio67 = GPIO_MODE_NATIVE, /* CLK_FLEX3 / TP82 */ + .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ + .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ + .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ + .gpio71 = GPIO_MODE_NATIVE, /* WWAN_OFF# */ + .gpio72 = GPIO_MODE_NATIVE, /* PM_BATLOW# */ + .gpio73 = GPIO_MODE_GPIO, /* PCIECLKRQ0# / TP39 */ + .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ + .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c new file mode 100644 index 0000000..29f8a45 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c @@ -0,0 +1,252 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Vendor Name : IDT + * Vendor ID : 0x10ec0269 + * Subsystem ID : 0x17aa21fa + * Revision ID : 0x100303 + */ + + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC + 0x17aa21fa, // Subsystem ID + 0x0000007d, // Number of 4 dword sets + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +/* NID 0x01 - NodeInfo */ + AZALIA_SUBVENDOR(0x0, 0x17AA21FA), + +/* NID 0x0A - External Microphone Connector + * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), + +/* NID 0x0B - Headphone Connector + * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), + +/* NID 0x0C - Not connected + * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), + +/* NID 0x0D - Internal Speakers + * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), + +/* NID 0x0F - Not connected + * Config=0x40F000F0 + */ + AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), + +/* NID 0x11 - Internal Microphone + * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), + AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0), + + 0x01970804, + 0x01870803, + 0x01470740, + 0x00970600, + + 0x00370600, + 0x00270600, + 0x00270600, + 0x00270600, + + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205), + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), + + /* + * Hardware EQ Parameters + * Sample Rate 88200 + */ + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, + 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, + 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, + 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, + 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, + 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, + 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, + 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, + 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, + 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, + 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, + 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, + 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, + 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, + 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, + 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, + 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, + 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, + 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, + 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, + 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, + 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, + 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, + 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, + 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, + 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, + 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, + 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, + 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, + 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, + 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, + 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, + 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, + 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, + 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, + 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, + 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, + 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, + 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, + 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, + 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, + 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, + 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, + 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, + 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, + 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, + 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, + + /* + * Hardware EQ Parameters + * Sample Rate 96000 + */ + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, + 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, + 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, + 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, + 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, + 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, + 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, + 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, + 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, + 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, + 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, + 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, + 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, + 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, + 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, + 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, + 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, + 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, + 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, + 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, + 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, + 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, + 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, + 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, + 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, + 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, + 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, + 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, + 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, + 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, + 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, + 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, + 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, + 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, + 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, + 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, + 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, + 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, + 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, + 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, + 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, + 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, + 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, + 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, + 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, + 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, + 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, + + /* SAFEDSP Parameters */ + 0x022782C1, 0x02277127, 0x02277227, 0x02278801, + 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, + 0x02278B0F, 0x0017B008, + + /* Misc entries */ + 0x00B707C0, /* Enable PortB as Output with HP amp */ + 0x00D70740, /* Enable PortD as Output */ + 0x0017A200, /* Disable ClkEn of PortSenseTst */ + 0x0017C621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + + /* --- Next Codec --- */ + +/* Vendor Name : Intel + * Vendor ID : 0x80862806 + * Subsystem ID : 0x80860101 + * Revision ID : 0x100000 + */ + /* coreboot specific header */ + 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of IDs + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c new file mode 100644 index 0000000..045d699 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> +#include <pc80/keyboard.h> +#include <ec/lenovo/h8/h8.h> +#include <build.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + + + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; + + pc_keyboard_init(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c new file mode 100644 index 0000000..9f8a29f --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <pc80/mc146818rtc.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h new file mode 100644 index 0000000..f8b9141 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GAB75MD3H_ONBOARD_H +#define GAB75MD3H_ONBOARD_H + +#include <arch/smp/mpspec.h> + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c new file mode 100644 index 0000000..3ba6319 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SUPERIO_BASE 0x2e +#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <superio/ite/it8728f/it8728f.h> +#include <superio/ite/common/ite.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +static void it8728f_b75md3h_disable_reboot(device_t dev) +{ + /* GPIO SIO settings */ + ite_reg_write(dev, 0xEF, 0x7E); // magic + + ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 + ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 + ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port + ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 + ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear! + ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! + ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in + ite_reg_write(dev, 0xe9, 0x27); // bus select disable + ite_reg_write(dev, 0xf0, 0x10); // ? + ite_reg_write(dev, 0xf1, 0x42); // ? + ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12) + + /* EC SIO settings */ + ite_reg_write(IT8728F_EC, 0xf1, 0xc0); + ite_reg_write(IT8728F_EC, 0xf6, 0xf0); + ite_reg_write(IT8728F_EC, 0xf9, 0x48); + ite_reg_write(IT8728F_EC, 0x60, 0x0a); + ite_reg_write(IT8728F_EC, 0x61, 0x30); + ite_reg_write(IT8728F_EC, 0x62, 0x0a); + ite_reg_write(IT8728F_EC, 0x63, 0x20); + ite_reg_write(IT8728F_EC, 0x30, 0x01); +} + +void rcba_config(void) +{ +/* + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); + + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x3500) = 0x2000035f; + RCBA32(0x3504) = 0x2000035f; + RCBA32(0x3508) = 0x2000035f; + RCBA32(0x350c) = 0x2000035f; + RCBA32(0x3510) = 0x2000035f; + RCBA32(0x3514) = 0x2000035f; + RCBA32(0x3518) = 0x2000035f; + RCBA32(0x351c) = 0x2000035f; + RCBA32(0x3520) = 0x2000035f; + RCBA32(0x3524) = 0x2000035f; + RCBA32(0x3528) = 0x2000035f; + RCBA32(0x352c) = 0x2000035f; + RCBA32(0x3530) = 0x2000035f; + RCBA32(0x3534) = 0x2000035f; + RCBA32(0x3560) = 0x024c8001; + RCBA32(0x3564) = 0x000024a3; + RCBA32(0x3568) = 0x00040002; + RCBA32(0x356c) = 0x01000050; + RCBA32(0x3570) = 0x02000662; + RCBA32(0x3574) = 0x18000f9f; + RCBA32(0x3578) = 0x1800ff4f; + RCBA32(0x357c) = 0x0001d530; + RCBA32(0x35a0) = 0xc0300c03; + RCBA32(0x35a4) = 0x00241803; + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + outw (0x0000, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; +// RCBA32(0x3418) = 0x1fee1fe1; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; +*/ + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17ee1fe1; +} + +void pch_enable_lpc(void) +{ + /* + * Enable: + * EC Decode Range PortA30/A20 + * SuperIO Port2E/2F + * PS/2 Keyboard/Mouse Port60/64 + * FDD Port3F0h-3F5h and Port3F7h + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + + /* Initialize SuperIO */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8728f_b75md3h_disable_reboot(SUPERIO_GPIO); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, +// { 1, 5, 4 }, +// { 1, 5, 4 }, +// { 1, 5, 6 }, +// { 1, 5, 5 }, +// { 1, 5, 5 }, +// { 1, 5, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd (&spd[0], 0x50); + read_spd (&spd[1], 0x51); + read_spd (&spd[2], 0x52); + read_spd (&spd[3], 0x53); +} + +#if 0 +static void dmi_config(void) +{ + DMIBAR32(0x0218) = 0x06aa0b0c; + DMIBAR32(0x021c) = 0x0b0d0b0d; + DMIBAR32(0x0300) = 0x0011028d; + DMIBAR32(0x0304) = 0x002102cd; + DMIBAR32(0x030c) = 0x007d004b; + DMIBAR32(0x0310) = 0x007e004c; + DMIBAR32(0x0318) = 0x002304ad; + DMIBAR32(0x031c) = 0x003304ed; + DMIBAR32(0x03b8) = 0x005c05a4; + DMIBAR32(0x03bc) = 0x006c05e4; + DMIBAR32(0x0530) = 0x41d3b000; + DMIBAR32(0x0534) = 0x00019f80; + DMIBAR32(0x0ba4) = 0x0000000d; + DMIBAR32(0x0d80) = 0x1c9cfc0b; + DMIBAR32(0x0e1c) = 0x20000000; + DMIBAR32(0x0e2c) = 0x20000000; +} +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h new file mode 100644 index 0000000..ed08c8a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GAB75MD3H_THERMAL_H +#define GAB75MD3H_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c index 7ce5574..b1f8447 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_native.c +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -33,7 +33,7 @@ early_usb_init (const struct southbridge_usb_port *portmap) /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 , 0x2000094a }; + const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 , 0x2000094a, 0x2000035f }; int i; /* Activate PMBAR. */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);

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Patch set updated for coreboot: f5600de cpu/intel: Add configuration for socket LGA1155
by Damien Zammit 28 Oct '14

28 Oct '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7197 -gerrit commit f5600de430382fdc6bf01bfa31e2847d05bd393d Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Oct 23 21:57:48 2014 +1100 cpu/intel: Add configuration for socket LGA1155 This allows mainboards to explicitly select LGA1155. Change-Id: Id33679b27c89038588347cb4f1a6a0e66aae3e6e Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/socket_LGA1155/Kconfig | 11 +++++++++++ src/cpu/intel/socket_LGA1155/Makefile.inc | 7 +++++++ src/cpu/intel/socket_LGA1155/socket_LGA1155.c | 5 +++++ 5 files changed, 25 insertions(+) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index aa3dd5b..de76e3e 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -33,6 +33,7 @@ source src/cpu/intel/socket_mPGA603/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig +source src/cpu/intel/socket_LGA1155/Kconfig source src/cpu/intel/socket_LGA771/Kconfig source src/cpu/intel/socket_LGA775/Kconfig source src/cpu/intel/socket_rPGA988B/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index b6e7268..51451e9 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -27,6 +27,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 diff --git a/src/cpu/intel/socket_LGA1155/Kconfig b/src/cpu/intel/socket_LGA1155/Kconfig new file mode 100644 index 0000000..35aac3c --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/Kconfig @@ -0,0 +1,11 @@ +config CPU_INTEL_SOCKET_LGA1155 + bool + +if CPU_INTEL_SOCKET_LGA1155 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select MMX + select SSE + +endif # CPU_INTEL_SOCKET_LGA1155 diff --git a/src/cpu/intel/socket_LGA1155/Makefile.inc b/src/cpu/intel/socket_LGA1155/Makefile.inc new file mode 100644 index 0000000..cbf6f06 --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/Makefile.inc @@ -0,0 +1,7 @@ +ramstage-y += socket_LGA1155.c +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo diff --git a/src/cpu/intel/socket_LGA1155/socket_LGA1155.c b/src/cpu/intel/socket_LGA1155/socket_LGA1155.c new file mode 100644 index 0000000..63c925d --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/socket_LGA1155.c @@ -0,0 +1,5 @@ +#include <device/device.h> + +struct chip_operations cpu_intel_socket_LGA1155_ops = { + CHIP_NAME("Socket LGA1155 CPU") +};

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Patch set updated for coreboot: 101daeb southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop
by Edward O'Callaghan 28 Oct '14

28 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6147 -gerrit commit 101daebba252d8be28bc6de2165f847697dd1317 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 15:36:57 2014 +1000 southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop Correct mask to select bits 4-6 inclusively as per comment and use bitwise operations while working with bits. Be sure to write back out the data on the retrain. Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Found-by: Clang --- src/southbridge/amd/rs690/cmn.c | 3 ++- src/southbridge/amd/rs780/cmn.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 05a47b3..86a6976 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -285,10 +285,11 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + tmp = (reg >> 4) & 0x07; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ reg |= 1 << 8; + nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); count++; /* CIM said "keep in loop"? */ } else { res = 1; diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 497d1af..57118b8 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -326,10 +326,11 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + tmp = (reg >> 4) & 0x07; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ reg |= 1 << 8; + nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); count++; /* CIM said "keep in loop"? */ } else { res = 1;

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New patch to review for coreboot: 5d7e112 mainboard/samsung/lumpy: Fix usage of GNU field designator ext
by Edward O'Callaghan 28 Oct '14

28 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7232 -gerrit commit 5d7e1124199ede0dd32e66a07f7872cc36568b12 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 29 06:16:51 2014 +1100 mainboard/samsung/lumpy: Fix usage of GNU field designator ext Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Ibbcdbb44c7586ac8d445870789647f8ff9585452 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/samsung/lumpy/romstage.c | 44 +++++++++++++++++----------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index dc4161d..cf2973d 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -139,32 +139,32 @@ void main(unsigned long bist) int cbmem_was_initted; struct pei_data pei_data = { - pei_version: PEI_VERSION, - mchbar: DEFAULT_MCHBAR, - dmibar: DEFAULT_DMIBAR, - epbar: DEFAULT_EPBAR, - pciexbar: CONFIG_MMCONF_BASE_ADDRESS, - smbusbar: SMBUS_IO_BASE, - wdbbar: 0x4000000, - wdbsize: 0x1000, - hpet_address: CONFIG_HPET_ADDRESS, - rcba: DEFAULT_RCBABASE, - pmbase: DEFAULT_PMBASE, - gpiobase: DEFAULT_GPIOBASE, - thermalbase: 0xfed08000, - system_type: 0, // 0 Mobile, 1 Desktop/Server - tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xa0, 0x00,0x00,0x00 }, - ts_addresses: { 0x30, 0x00, 0x00, 0x00 }, - ec_present: 1, + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0x00,0x00,0x00 }, + .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, + .ec_present = 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - dimm_channel0_disabled: 2, - dimm_channel1_disabled: 2, - max_ddr3_freq: 1333, - usb_port_config: { + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1333, + .usb_port_config = { { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */ { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */

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New patch to review for coreboot: 7c8b8f9 mainboard/google/butterfly: Fix usage of GNU field designator ext
by Edward O'Callaghan 28 Oct '14

28 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7231 -gerrit commit 7c8b8f9e63c7f0ea696ead36757e560f5b333325 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 29 06:15:57 2014 +1100 mainboard/google/butterfly: Fix usage of GNU field designator ext Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I167d2c9ad3f690de41fee51dd7800ce76b328e41 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/google/butterfly/romstage.c | 48 +++++++++++++++---------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 908b6d8..6b7613a 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -119,33 +119,33 @@ void main(unsigned long bist) int cbmem_was_initted; struct pei_data pei_data = { - pei_version: PEI_VERSION, - mchbar: DEFAULT_MCHBAR, - dmibar: DEFAULT_DMIBAR, - epbar: DEFAULT_EPBAR, - pciexbar: CONFIG_MMCONF_BASE_ADDRESS, - smbusbar: SMBUS_IO_BASE, - wdbbar: 0x4000000, - wdbsize: 0x1000, - hpet_address: CONFIG_HPET_ADDRESS, - rcba: DEFAULT_RCBABASE, - pmbase: DEFAULT_PMBASE, - gpiobase: DEFAULT_GPIOBASE, - thermalbase: 0xfed08000, - system_type: 0, // 0 Mobile, 1 Desktop/Server - tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xA0, 0x00,0xA4,0x00 }, - ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, - ec_present: 1, - ddr3lv_support: 0, + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .ddr3lv_support = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - dimm_channel0_disabled: 2, - dimm_channel1_disabled: 2, - max_ddr3_freq: 1600, - usb_port_config: { + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { /* enabled usb oc pin length */ { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ @@ -162,7 +162,7 @@ void main(unsigned long bist) { 0, 4, 0x0000 }, /* P12: Empty */ { 0, 4, 0x0000 }, /* P13: Empty */ }, - ddr_refresh_rate_config: 2, /* Force double refresh rate */ + .ddr_refresh_rate_config = 2, /* Force double refresh rate */ }; timestamp_init(get_initial_timestamp());

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New patch to review for coreboot: d30fca8 src/Kconfig: Don't treat warns as errors on Clang builds yet
by Edward O'Callaghan 28 Oct '14

28 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7230 -gerrit commit d30fca881f3589bf518f04db6f1666bc4a9b8578 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 29 06:00:15 2014 +1100 src/Kconfig: Don't treat warns as errors on Clang builds yet Currently clang/llvm builds are not fully supported. As such, let us tone down treating errors as warnings until we actually build the entire tree. Change-Id: If7f90f9887e27250f5e6d73d1692505676be9d47 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 5255130..4deed2a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1116,9 +1116,13 @@ config ENABLE_APIC_EXT_ID bool default n +# XXX Currently clang/llvm builds are not fully supported, +# Let us tone down warns treated as errors until we actually build +# the whole treee. config WARNINGS_ARE_ERRORS bool - default y + default y if !COMPILER_LLVM_CLANG + default n if COMPILER_LLVM_CLANG # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are

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Patch merged into coreboot/master: a85a92d A tool for IPQ8064 encapsulation
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit a85a92d292d0240459949e20097e66a0102dfe38 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Apr 7 13:36:48 2014 -0700 A tool for IPQ8064 encapsulation This is a copy of the tool provided by the vendor. It adds a header which tells the early stage loader where to load the next phase blob for execution. It is going to be used to encapsulate the bootblock. Usage of this tool is as follows: ipqheader.py <base-addr> <input-file> <output-file> Old-Change-Id: I448c006719f4f3dd5a6716ff2e47f7fc275c805e Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193494 Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 201630f8637eb627f0894ecd7bceb31017244ad4) Make ipqheader.py executable Modify the utility to become a Linux executable. While at it, fix the program name reported by error messages. Old-Change-Id: I25061d43fdea72655a696deb9e494e9c7382f670 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193495 Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit bbbf69c754aa3b6a1bf17ab3ced1c739c3ee0688) ipq8064: SBL headers must have 4 byte aligned blob sizes It turns out that for SBL3 to load the next phase, the sizes in the MBN header must be 4 byres aligned. This change makes sure that this requirement is enforced. Old-Change-Id: Ia64f04bb281ae772b060d2f7713c98dd348972ba Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196167 (cherry picked from commit fa6a52a07cb87ecf2538a6b0d47605d79104e4cc) Add proper license to the ipqheader tool This patch adds a vanilla BSD 3-Clause license. Original-Change-Id: I9da7176e670b598808ef5be2461b6105a4c5f6c5 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225783 Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> Original-Tested-by: Trevor Bourget <tbourget(a)codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit a0c47a8d74f1ac131c91e978b6d68bbcfaa52c37) Squashed 4 commits for the ipqheader util. Change-Id: I144c01947a89e1348a06aa82590e972e2ec31247 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6976 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6976 for details. -gerrit

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Patch set updated for coreboot: 7120905 soc: Don't hide pointers behind typedefs
by Edward O'Callaghan 28 Oct '14

28 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7228 -gerrit commit 7120905894d0a9dcb2a76e65ebe0adeb8deb124b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 28 23:00:45 2014 +1100 soc: Don't hide pointers behind typedefs Change-Id: I6ddaefa57cb6cdeb39039b7db0b597b691912d05 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/baytrail/chip.c | 8 +++---- src/soc/intel/baytrail/cpu.c | 4 ++-- src/soc/intel/baytrail/ehci.c | 4 ++-- src/soc/intel/baytrail/emmc.c | 2 +- src/soc/intel/baytrail/gfx.c | 14 +++++------ src/soc/intel/baytrail/hda.c | 2 +- src/soc/intel/baytrail/lpe.c | 12 +++++----- src/soc/intel/baytrail/lpss.c | 10 ++++---- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/baytrail/pcie.c | 14 +++++------ src/soc/intel/baytrail/pmutil.c | 8 +++---- src/soc/intel/baytrail/ramstage.c | 2 +- src/soc/intel/baytrail/sata.c | 2 +- src/soc/intel/baytrail/scc.c | 2 +- src/soc/intel/baytrail/sd.c | 2 +- src/soc/intel/baytrail/smihandler.c | 2 +- src/soc/intel/baytrail/southcluster.c | 24 +++++++++---------- src/soc/intel/baytrail/spi.c | 2 +- src/soc/intel/baytrail/xhci.c | 6 ++--- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/broadwell/me.h | 2 +- src/soc/intel/broadwell/broadwell/pch.h | 2 +- src/soc/intel/broadwell/broadwell/ramstage.h | 4 ++-- src/soc/intel/broadwell/broadwell/xhci.h | 2 +- src/soc/intel/broadwell/chip.c | 8 +++---- src/soc/intel/broadwell/cpu.c | 6 ++--- src/soc/intel/broadwell/ehci.c | 2 +- src/soc/intel/broadwell/lpc.c | 18 +++++++-------- src/soc/intel/broadwell/me.c | 24 +++++++++---------- src/soc/intel/broadwell/pch.c | 6 ++--- src/soc/intel/broadwell/pcie.c | 32 +++++++++++++------------- src/soc/intel/broadwell/romstage/uart.c | 2 +- src/soc/intel/broadwell/sata.c | 2 +- src/soc/intel/broadwell/smbus.c | 8 +++---- src/soc/intel/broadwell/smihandler.c | 2 +- src/soc/intel/broadwell/smmrelocate.c | 6 ++--- src/soc/intel/broadwell/spi.c | 2 +- src/soc/intel/broadwell/systemagent.c | 22 +++++++++--------- src/soc/intel/broadwell/xhci.c | 8 +++---- src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 2 +- src/soc/intel/fsp_baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/fsp_baytrail/chip.c | 10 ++++---- src/soc/intel/fsp_baytrail/cpu.c | 4 ++-- src/soc/intel/fsp_baytrail/northcluster.c | 8 +++---- src/soc/intel/fsp_baytrail/pmutil.c | 4 ++-- src/soc/intel/fsp_baytrail/ramstage.c | 2 +- src/soc/intel/fsp_baytrail/smihandler.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 26 ++++++++++----------- src/soc/intel/fsp_baytrail/spi.c | 2 +- src/soc/nvidia/tegra/dc.h | 2 +- src/soc/nvidia/tegra124/display.c | 2 +- src/soc/nvidia/tegra124/soc.c | 8 +++---- src/soc/samsung/exynos5250/cpu.c | 10 ++++---- src/soc/samsung/exynos5420/cpu.c | 10 ++++---- 55 files changed, 193 insertions(+), 193 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index a8b5fdc..4a7b536 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -26,16 +26,16 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); +void southcluster_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} #endif void baytrail_init_scc(void); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index ce9eb49..1a478dc 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -26,7 +26,7 @@ #include <baytrail/ramstage.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -40,7 +40,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, @@ -51,7 +51,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -79,7 +79,7 @@ struct chip_operations soc_intel_baytrail_ops = { .init = soc_init, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 97d1f04..36cb32a 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -99,7 +99,7 @@ static void baytrail_set_pstate_coord(void) wrmsr(MSR_POWER_MISC, power_misc); } -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -142,7 +142,7 @@ void baytrail_init_cpus(device_t dev) restore_default_smm_area(default_smm_area); } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 5d1a4d8..accfed2 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -91,7 +91,7 @@ static const struct reg_script ehci_hc_reset[] = { REG_SCRIPT_END }; -static void usb2_phy_init(device_t dev) +static void usb2_phy_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script usb2_phy_script[] = { @@ -123,7 +123,7 @@ static void usb2_phy_init(device_t dev) reg_script_run(usb2_phy_script); } -static void ehci_init(device_t dev) +static void ehci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script ehci_hc_init[] = { diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index f88614b..74bdb4b 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -49,7 +49,7 @@ static const struct reg_script emmc_ops[] = { REG_SCRIPT_END, }; -static void emmc_init(device_t dev) +static void emmc_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 4ed08c9..dbb2dc1 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -38,7 +38,7 @@ * Lock Power Context Base Register to point to a 24KB block * of memory in GSM. Power context save data is stored here. */ -static void gfx_lock_pcbase(device_t dev) +static void gfx_lock_pcbase(struct device *dev) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, @@ -263,18 +263,18 @@ static const struct reg_script gfx_post_vbios_script[] = { REG_SCRIPT_END }; -static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) { reg_script_run_on_dev(dev, ops); } -static void gfx_pre_vbios_init(device_t dev) +static void gfx_pre_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } -static void gfx_pm_init(device_t dev) +static void gfx_pm_init(struct device *dev) { printk(BIOS_INFO, "GFX: Power Management Init\n"); gfx_run_script(dev, gfx_init_script); @@ -283,13 +283,13 @@ static void gfx_pm_init(device_t dev) gfx_lock_pcbase(dev); } -static void gfx_post_vbios_init(device_t dev) +static void gfx_post_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } -static void gfx_panel_setup(device_t dev) +static void gfx_panel_setup(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { @@ -358,7 +358,7 @@ static void gfx_panel_setup(device_t dev) } } -static void gfx_init(device_t dev) +static void gfx_init(struct device *dev) { /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index c5de654..5733b95 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -78,7 +78,7 @@ static const uint32_t hdmi_codec_verb_table[] = { 0x20671f58, }; -static void hda_init(device_t dev) +static void hda_init(struct device *dev) { struct resource *res; int codec_mask; diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 581f42b..b6fb7c2 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -45,7 +45,7 @@ #define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) -static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +static void assign_device_nvs(struct device *dev, u32 *field, unsigned index) { struct resource *res; @@ -54,7 +54,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index) *field = res->base; } -static void lpe_enable_acpi_mode(device_t dev) +static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -87,7 +87,7 @@ static void lpe_enable_acpi_mode(device_t dev) reg_script_run_on_dev(dev, ops); } -static void setup_codec_clock(device_t dev) +static void setup_codec_clock(struct device *dev) { uint32_t reg; int clk_reg; @@ -125,7 +125,7 @@ static void setup_codec_clock(device_t dev) write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } -static void lpe_stash_firmware_info(device_t dev) +static void lpe_stash_firmware_info(struct device *dev) { struct resource *res; struct resource *mmio; @@ -149,7 +149,7 @@ static void lpe_stash_firmware_info(device_t dev) } } -static void lpe_init(device_t dev) +static void lpe_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -161,7 +161,7 @@ static void lpe_init(device_t dev) lpe_enable_acpi_mode(dev); } -static void lpe_read_resources(device_t dev) +static void lpe_read_resources(struct device *dev) { pci_dev_read_resources(dev); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 3ee648a..c548370 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -33,7 +33,7 @@ #include "chip.h" -static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -70,7 +70,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) reg_script_run_on_dev(dev, ops); } -static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) { struct reg_script ops[] = { REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, @@ -82,7 +82,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) reg_script_run_on_dev(dev, ops); } -static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) +static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; @@ -123,7 +123,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) } } -static void i2c_disable_resets(device_t dev) +static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ static const struct reg_script ops[] = { @@ -150,7 +150,7 @@ static void i2c_disable_resets(device_t dev) } } -static void lpss_init(device_t dev) +static void lpss_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; int iosf_reg, nvs_index; diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index b119e24..2d4f20b 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -71,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void) return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { unsigned long mmconf; unsigned long bmbound; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 4498f43..e530498 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -34,12 +34,12 @@ static int pll_en_off; static uint32_t strpfusecfg; -static inline int root_port_offset(device_t dev) +static inline int root_port_offset(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn); } -static inline int is_first_port(device_t dev) +static inline int is_first_port(struct device *dev) { return root_port_offset(dev) == PCIE_PORT1_FUNC; } @@ -88,7 +88,7 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_SCRIPT_END, }; -static void byt_pcie_init(device_t dev) +static void byt_pcie_init(struct device *dev) { struct reg_script init_script[] = { REG_SCRIPT_NEXT(init_static_before_exit_latency), @@ -129,7 +129,7 @@ static const struct reg_script no_dev_behind_port[] = { REG_SCRIPT_END, }; -static void check_port_enabled(device_t dev) +static void check_port_enabled(struct device *dev) { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; @@ -155,7 +155,7 @@ static void check_port_enabled(device_t dev) } } -static void check_device_present(device_t dev) +static void check_device_present(struct device *dev) { /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -172,7 +172,7 @@ static void check_device_present(device_t dev) } } -static void byt_pcie_enable(device_t dev) +static void byt_pcie_enable(struct device *dev) { if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -194,7 +194,7 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) +static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did) { uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index aee3726..b9820c1 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -28,9 +28,9 @@ #if defined(__SMM__) -static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); +static const struct device *pcu_dev = PCI_DEV(0, PCU_DEV, 0); -static inline device_t get_pcu_dev(void) +static inline struct device *get_pcu_dev(void) { return pcu_dev; } @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..10f7ff2 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -78,7 +78,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 28a2f8c..3c69985 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -159,7 +159,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { config_t *config = dev->chip_info; u8 reg8; diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 7efb66d..e2bd1dd 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -87,7 +87,7 @@ void baytrail_init_scc(void) reg_script_run(scc_after_dll); } -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 97c8628..6068e61 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -34,7 +34,7 @@ #define CAP_OVERRIDE_HIGH 0xa4 # define USE_CAP_OVERRIDES (1 << 31) -static void sd_init(device_t dev) +static void sd_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 22b60c4..4dca798 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + struct device *dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 500a13d..d3d284d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -43,12 +43,12 @@ #include "chip.h" static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); @@ -83,7 +83,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -96,7 +96,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; @@ -113,7 +113,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -154,7 +154,7 @@ static void sc_rtc_init(void) * or configuration. This is definitely a hack, but it helps the kernel * along. */ -static void com1_configure_resume(device_t dev) +static void com1_configure_resume(struct device *dev) { const uint16_t port = 0x3f8; @@ -182,7 +182,7 @@ static void com1_configure_resume(device_t dev) outb(3, port + UART8250_LCR); } -static void sc_init(device_t dev) +static void sc_init(struct device *dev) { int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; @@ -224,7 +224,7 @@ static void sc_init(device_t dev) */ /* Set bit in function disble register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -333,7 +333,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -345,7 +345,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -362,7 +362,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -478,7 +478,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 8677b61..4de3d91 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -290,7 +290,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; + struct device *dev; uint32_t sbase; #ifdef __SMM__ diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..3f3ed91 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -148,7 +148,7 @@ const struct reg_script xhci_clock_gating_script[] = { }; /* Warm Reset a USB3 port */ -static void xhci_reset_port_usb3(device_t dev, int port) +static void xhci_reset_port_usb3(struct device *dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ @@ -167,7 +167,7 @@ static void xhci_reset_port_usb3(device_t dev, int port) } /* Prepare ports to be routed to EHCI or XHCI */ -static void xhci_route_all(device_t dev) +static void xhci_route_all(struct device *dev) { static const struct reg_script xhci_route_all_script[] = { /* USB3 SuperSpeed Enable */ @@ -196,7 +196,7 @@ static void xhci_route_all(device_t dev) } } -static void xhci_init(device_t dev) +static void xhci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index f4cac7b..3259308 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -394,7 +394,7 @@ static int generate_T_state_entries(int core, int cores_per_package) static int generate_C_state_entries(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; acpi_cstate_t map[3]; int *set; diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h index ddecaf8..f3021ee 100644 --- a/src/soc/intel/broadwell/broadwell/me.h +++ b/src/soc/intel/broadwell/broadwell/me.h @@ -465,7 +465,7 @@ typedef struct { } __attribute__ ((packed)) mbp_plat_time; typedef struct { - u32 device_type : 2; + u32 struct device *ype : 2; u32 reserved : 30; } __attribute__ ((packed)) mbp_nfc_data; diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h index e677215..c58b695 100644 --- a/src/soc/intel/broadwell/broadwell/pch.h +++ b/src/soc/intel/broadwell/broadwell/pch.h @@ -47,6 +47,6 @@ int pch_is_wpt(void); int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_log_state(void); -void pch_disable_devfn(device_t dev); +void pch_disable_devfn(struct device *dev); #endif diff --git a/src/soc/intel/broadwell/broadwell/ramstage.h b/src/soc/intel/broadwell/broadwell/ramstage.h index 685de14..d66e8cc 100644 --- a/src/soc/intel/broadwell/broadwell/ramstage.h +++ b/src/soc/intel/broadwell/broadwell/ramstage.h @@ -24,8 +24,8 @@ #include <chip.h> void broadwell_init_pre_device(void *chip_info); -void broadwell_init_cpus(device_t dev); -void broadwell_pch_enable_dev(device_t dev); +void broadwell_init_cpus(struct device *dev); +void broadwell_pch_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/broadwell/xhci.h b/src/soc/intel/broadwell/broadwell/xhci.h index 3f4fb4e..a5536fc 100644 --- a/src/soc/intel/broadwell/broadwell/xhci.h +++ b/src/soc/intel/broadwell/broadwell/xhci.h @@ -55,7 +55,7 @@ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ #ifdef __SMM__ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ); #endif #endif diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 94f7893..e2ab17c 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -24,7 +24,7 @@ #include <broadwell/ramstage.h> #include <chip.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -36,7 +36,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = &pci_ops_mmconf, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = &cpu_bus_noop, @@ -45,7 +45,7 @@ static struct device_operations cpu_bus_ops = { .init = &broadwell_init_cpus, }; -static void broadwell_enable(device_t dev) +static void broadwell_enable(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -67,7 +67,7 @@ struct chip_operations soc_intel_broadwell_ops = { .init = &broadwell_init_pre_device, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 58f81fc..416fe3c 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -444,7 +444,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *conf = dev->chip_info; msr_t msr; @@ -587,7 +587,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) } /* All CPUs including BSP will run the following function. */ -static void cpu_core_init(device_t cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -671,7 +671,7 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; -void broadwell_init_cpus(device_t dev) +void broadwell_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; int num_threads; diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index a59d3c8..30f4acd 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -28,7 +28,7 @@ #include <broadwell/ehci.h> #include <broadwell/pch.h> -static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { u8 access_cntl; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 4b21326..270316c 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -89,9 +89,9 @@ static void pch_enable_ioapic(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config = dev->chip_info; pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); @@ -126,7 +126,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u16 reg16; const char *state; @@ -325,7 +325,7 @@ static void pch_pm_init(struct device *dev) RCBA32_OR(0x3a6c, 0x00000001); } -static void pch_cg_init(device_t dev) +static void pch_cg_init(struct device *dev) { u32 reg32; u16 reg16; @@ -420,7 +420,7 @@ static void lpc_init(struct device *dev) pch_set_acpi_mode(); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -482,7 +482,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -495,7 +495,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -508,7 +508,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -533,7 +533,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 15bcc34..19bc754 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -58,11 +58,11 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); /* MMIO base address for MEI interface */ static u32 mei_base_address; -void intel_me_mbp_clear(device_t dev); +void intel_me_mbp_clear(struct device *dev); #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -440,7 +440,7 @@ static inline int mei_sendrecv_icc(struct icc_header *icc, * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read * state machine on the BIOS end doesn't match the ME's state machine. */ -static void intel_me_mbp_give_up(device_t dev) +static void intel_me_mbp_give_up(struct device *dev) { struct mei_csr csr; @@ -456,7 +456,7 @@ static void intel_me_mbp_give_up(device_t dev) * mbp clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ -void intel_me_mbp_clear(device_t dev) +void intel_me_mbp_clear(struct device *dev) { int count; struct me_hfs2 hfs2; @@ -568,7 +568,7 @@ static int mkhi_end_of_post(void) void intel_me_finalize(void) { - device_t dev = PCH_DEV_ME; + struct device *dev = PCH_DEV_ME; struct me_hfs hfs; u32 reg32; @@ -629,7 +629,7 @@ static int me_icc_set_clock_enables(u32 mask) } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -699,7 +699,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -729,7 +729,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -776,7 +776,7 @@ static int intel_me_extend_valid(device_t dev) } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { config_t *config = dev->chip_info; me_bios_path path = intel_me_path(dev); @@ -829,7 +829,7 @@ static void intel_me_init(device_t dev) */ } -static void intel_me_enable(device_t dev) +static void intel_me_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ @@ -882,7 +882,7 @@ struct mbp_payload { * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 82390a4..e681620 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -81,7 +81,7 @@ u32 pch_read_soft_strap(int id) #ifndef __PRE_RAM__ /* Put device in D3Hot Power State */ -static void pch_enable_d3hot(device_t dev) +static void pch_enable_d3hot(struct device *dev) { u32 reg32 = pci_read_config32(dev, PCH_PCS); reg32 |= PCH_PCS_PS_D3HOT; @@ -89,7 +89,7 @@ static void pch_enable_d3hot(device_t dev) } /* Set bit in Function Disble register to hide this device */ -void pch_disable_devfn(device_t dev) +void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { case PCH_DEVFN_ADSP: /* Audio DSP */ @@ -179,7 +179,7 @@ void pch_disable_devfn(device_t dev) } } -void broadwell_pch_enable_dev(device_t dev) +void broadwell_pch_enable_dev(struct device *dev) { u32 reg32; diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index a407f3c..08e4863 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -32,8 +32,8 @@ #include <broadwell/rcba.h> #include <chip.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or); +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or); /* Low Power variant has 6 root ports. */ #define NUM_ROOT_PORTS 6 @@ -52,23 +52,23 @@ struct root_port_config { int coalesce; int gbe_port; int num_ports; - device_t ports[NUM_ROOT_PORTS]; + struct device *ports[NUM_ROOT_PORTS]; }; static struct root_port_config rpc; -static inline int root_port_is_first(device_t dev) +static inline int root_port_is_first(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == 0; } -static inline int root_port_is_last(device_t dev) +static inline int root_port_is_last(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); } /* Root ports are numbered 1..N in the documentation. */ -static inline int root_port_number(device_t dev) +static inline int root_port_number(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) + 1; } @@ -98,7 +98,7 @@ static void root_port_config_update_gbe_port(void) } } -static void root_port_init_config(device_t dev) +static void root_port_init_config(struct device *dev) { int rp; @@ -149,7 +149,7 @@ static void root_port_init_config(device_t dev) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_device_set_func(int index, int pci_func) { - device_t dev; + struct device *dev; unsigned new_devfn; dev = rpc.ports[index]; @@ -178,7 +178,7 @@ static void pcie_enable_clock_gating(void) int enabled_ports = 0; for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; int rp; dev = rpc.ports[i]; @@ -244,7 +244,7 @@ static void root_port_commit_config(void) pcie_enable_clock_gating(); for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; u32 reg32; dev = rpc.ports[i]; @@ -297,7 +297,7 @@ static void root_port_commit_config(void) RCBA32(RPFN) = rpc.new_rpfn; } -static void root_port_mark_disable(device_t dev) +static void root_port_mark_disable(struct device *dev) { /* Mark device as disabled. */ dev->enabled = 0; @@ -305,7 +305,7 @@ static void root_port_mark_disable(device_t dev) rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); } -static void root_port_check_disable(device_t dev) +static void root_port_check_disable(struct device *dev) { int rp; @@ -376,7 +376,7 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or) { u8 reg8; @@ -386,7 +386,7 @@ static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) pci_write_config8(dev, reg, reg8); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or) { u32 reg32; @@ -574,7 +574,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); } -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { /* Add this device to the root port config structure. */ root_port_init_config(dev); @@ -594,7 +594,7 @@ static void pch_pcie_enable(device_t dev) root_port_commit_config(); } -static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* NOTE: This is not the default position! */ if (!vendor || !device) diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 8214a8a..2517fef 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -52,7 +52,7 @@ void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ u32 gpiodf = 0x131f; - device_t dev; + struct device *dev; /* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e8d1fbe..24a8ebe 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -221,7 +221,7 @@ static void sata_init(struct device *dev) * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index a1dbdfe..c214510 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -31,7 +31,7 @@ #include <broadwell/ramstage.h> #include <broadwell/smbus.h> -static void pch_smbus_init(device_t dev) +static void pch_smbus_init(struct device *dev) { struct resource *res; u16 reg16; @@ -47,7 +47,7 @@ static void pch_smbus_init(device_t dev) outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { u16 device; struct resource *res; @@ -60,7 +60,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) { u16 device; struct resource *res; @@ -77,7 +77,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void smbus_read_resources(device_t dev) +static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_BASE_ADDRESS; diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 6acd07c..49cf774 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -83,7 +83,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + struct device *dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index bd1fc26..9ba6a00 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -196,7 +196,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -206,7 +206,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -static void fill_in_relocation_params(device_t dev, +static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { u32 tseg_size; @@ -351,7 +351,7 @@ static int install_permanent_handler(int num_cpus, static int cpu_smm_setup(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; int num_cpus; msr_t msr; diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 353323a..6095cf7 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -286,7 +286,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev = PCH_DEV_LPC; + struct device *dev = PCH_DEV_LPC; ich9_spi_regs *ich9_spi; pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 787a62b..c1110ab 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -37,7 +37,7 @@ #include <broadwell/ramstage.h> #include <broadwell/systemagent.h> -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -70,7 +70,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -89,7 +89,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -109,7 +109,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -127,7 +127,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -184,7 +184,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -253,7 +253,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -261,7 +261,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -272,7 +272,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -376,7 +376,7 @@ static void mc_add_dram_resources(device_t dev) chromeos_reserve_ram_oops(dev, index++); } -static void systemagent_read_resources(device_t dev) +static void systemagent_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -412,7 +412,7 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) +static void systemagent_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 89e1139..9530422 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -27,7 +27,7 @@ #include <broadwell/xhci.h> #ifdef __SMM__ -static u32 usb_xhci_mem_base(device_t dev) +static u32 usb_xhci_mem_base(struct device *dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -38,7 +38,7 @@ static u32 usb_xhci_mem_base(device_t dev) return mem_base & ~0xf; } -static int usb_xhci_port_count_usb3(device_t dev) +static int usb_xhci_port_count_usb3(struct device *dev) { /* PCH-LP has 4 SS ports */ return 4; @@ -71,7 +71,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port) * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +static void usb_xhci_reset_usb3(struct device *dev, int all) { u32 status, port_disabled; int timeout, port; @@ -142,7 +142,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all) } /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ) { u16 reg16; u32 reg32; diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h index d3a2377..d991d34 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h +++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h @@ -57,7 +57,7 @@ void rangeley_early_initialization(void); int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(device_t dev); +void soc_enable(struct device *dev); /* debugging functions */ void print_pci_devices(void); diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h index 095f09c..c1114df 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h @@ -25,10 +25,10 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void southcluster_enable_dev(struct device *dev); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index 839e8dc..e8f8ef4 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -25,12 +25,12 @@ #include <drivers/intel/fsp/fsp_util.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device *dev) { /* * Notify FSP for PostPciEnumeration. @@ -50,7 +50,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, @@ -60,7 +60,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = NULL, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", dev_name(dev), dev->path.type); @@ -100,7 +100,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = { .final = &finalize_chip, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 6f1e9c4..5c6375e 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -68,7 +68,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -91,7 +91,7 @@ void baytrail_init_cpus(device_t dev) } } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..010063e 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -92,7 +92,7 @@ uint32_t nc_read_top_of_low_memory(void) static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -141,7 +141,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { u32 bmbound, bsmmrrl; int index = 0; @@ -189,7 +189,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -199,7 +199,7 @@ static void nc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void nc_enable(device_t dev) +static void nc_enable(struct device *dev) { print_fsp_info(); } diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index aee3726..6a62a34 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..55abb4d 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -76,7 +76,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index 2225964..50b6ef4 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 2216902..307b006 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -51,12 +51,12 @@ typedef struct soc_intel_fsp_baytrail_config config_t; static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { #ifndef CONFIG_VIRTUAL_ROM_SIZE #error CONFIG_VIRTUAL_ROM_SIZE must be set. @@ -171,8 +171,8 @@ static void sc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -255,7 +255,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void sc_pirq_init(device_t dev) +static void sc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -318,7 +318,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -332,7 +332,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; u8 io_index = 0; @@ -354,7 +354,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -409,7 +409,7 @@ static void sc_init(struct device *dev) */ /* Set bit in function disable register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -505,7 +505,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -517,7 +517,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -534,7 +534,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -611,7 +611,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 4feb502..b64e1cb 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -288,7 +288,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; + struct device *dev; uint32_t sbase; #ifdef __SMM__ diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 48ffbda..895fd89 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -567,7 +567,7 @@ struct disp_ctl_win { u32 out_h; /* Height of output window in pixels */ }; -void display_startup(device_t dev); +void display_startup(struct device *dev); void dp_bringup(u32 winb_addr); unsigned int fb_base_mb(void); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 00dfbb6..9cc0cf0 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -234,7 +234,7 @@ uint32_t fb_base_mb(void) /* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ -void display_startup(device_t dev) +void display_startup(struct device *dev) { u32 val; int i; diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 11a52c4..eb8002b 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -29,7 +29,7 @@ * Will break if we get 2. Sigh. * We assume it's all multiples of MiB for MMUs sake. */ -static void soc_enable(device_t dev) +static void soc_enable(struct device *dev) { u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; @@ -39,13 +39,13 @@ static void soc_enable(device_t dev) mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); } -static void soc_init(device_t dev) +static void soc_init(struct device *dev) { display_startup(dev); printk(BIOS_INFO, "CPU: Tegra124\n"); } -static void soc_noop(device_t dev) +static void soc_noop(struct device *dev) { } @@ -57,7 +57,7 @@ static struct device_operations soc_ops = { .scan_bus = 0, }; -static void enable_tegra124_dev(device_t dev) +static void enable_tegra124_dev(struct device *dev) { dev->ops = &soc_ops; } diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index b8b88d7..c4561f6 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -59,7 +59,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5250_config *conf = dev->chip_info; @@ -110,7 +110,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -123,13 +123,13 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / (1024*1024)); } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -141,7 +141,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5250_dev(device_t dev) +static void enable_exynos5250_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 506b676..b646f82 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -73,7 +73,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5420_config *conf = dev->chip_info; @@ -133,7 +133,7 @@ static void tps65090_thru_ec_fet_disable(int index) } } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -154,13 +154,13 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / 1000000); } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -172,7 +172,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5420_dev(device_t dev) +static void enable_exynos5420_dev(struct device *dev) { dev->ops = &cpu_ops; }

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Patch set updated for coreboot: 5d10bd2 pci_ops.{c, h}: Don't hide pointers behind typedefs
by Edward O'Callaghan 28 Oct '14

28 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7227 -gerrit commit 5d10bd29107fc1232ee2a4850c82bde6388a7013 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 29 03:04:40 2014 +1100 pci_ops.{c,h}: Don't hide pointers behind typedefs Change-Id: I7cf7c236f94314d7970b19063d73db788c8267e5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/device/pci_ops.c | 28 ++++++++++++++-------------- src/include/device/pci_ops.h | 24 ++++++++++++------------ 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 5b633c8..6ddb493 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -34,7 +34,7 @@ const struct pci_bus_operations *pci_bus_default_ops(device_t dev) #endif } -static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, device_t dev) +static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, struct device *dev) { const struct pci_bus_operations *bops; bops = NULL; @@ -50,7 +50,7 @@ static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, device_t de * The only consumer of the return value of get_pbus() is pci_bus_ops(). * pci_bus_ops() can handle being passed NULL and auto-picks working ops. */ -static struct bus *get_pbus(device_t dev) +static struct bus *get_pbus(struct device *dev) { struct bus *pbus = NULL; @@ -82,42 +82,42 @@ static struct bus *get_pbus(device_t dev) return pbus; } -u8 pci_read_config8(device_t dev, unsigned int where) +u8 pci_read_config8(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } -u16 pci_read_config16(device_t dev, unsigned int where) +u16 pci_read_config16(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } -u32 pci_read_config32(device_t dev, unsigned int where) +u32 pci_read_config32(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } -void pci_write_config8(device_t dev, unsigned int where, u8 val) +void pci_write_config8(struct device *dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } -void pci_write_config16(device_t dev, unsigned int where, u16 val) +void pci_write_config16(struct device *dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } -void pci_write_config32(device_t dev, unsigned int where, u32 val) +void pci_write_config32(struct device *dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary, @@ -125,42 +125,42 @@ void pci_write_config32(device_t dev, unsigned int where, u32 val) } #if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(device_t dev, unsigned int where) +u8 pci_mmio_read_config8(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return pci_ops_mmconf.read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } -u16 pci_mmio_read_config16(device_t dev, unsigned int where) +u16 pci_mmio_read_config16(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return pci_ops_mmconf.read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } -u32 pci_mmio_read_config32(device_t dev, unsigned int where) +u32 pci_mmio_read_config32(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return pci_ops_mmconf.read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } -void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val) +void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } -void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val) +void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } -void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val) +void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn, diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index ae58a01..920475a 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -6,20 +6,20 @@ #include <arch/pci_ops.h> #ifndef __SIMPLE_DEVICE__ -u8 pci_read_config8(device_t dev, unsigned int where); -u16 pci_read_config16(device_t dev, unsigned int where); -u32 pci_read_config32(device_t dev, unsigned int where); -void pci_write_config8(device_t dev, unsigned int where, u8 val); -void pci_write_config16(device_t dev, unsigned int where, u16 val); -void pci_write_config32(device_t dev, unsigned int where, u32 val); +u8 pci_read_config8(struct device *dev, unsigned int where); +u16 pci_read_config16(struct device *dev, unsigned int where); +u32 pci_read_config32(struct device *dev, unsigned int where); +void pci_write_config8(struct device *dev, unsigned int where, u8 val); +void pci_write_config16(struct device *dev, unsigned int where, u16 val); +void pci_write_config32(struct device *dev, unsigned int where, u32 val); #if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(device_t dev, unsigned int where); -u16 pci_mmio_read_config16(device_t dev, unsigned int where); -u32 pci_mmio_read_config32(device_t dev, unsigned int where); -void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val); -void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val); -void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val); +u8 pci_mmio_read_config8(struct device *dev, unsigned int where); +u16 pci_mmio_read_config16(struct device *dev, unsigned int where); +u32 pci_mmio_read_config32(struct device *dev, unsigned int where); +void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val); +void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val); +void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val); #endif #endif

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coreboot-gerrit October 2014