New patch to review for coreboot: 49e7eed libpayload: usb: ehci: Honor 10ms reset recovery period

[Marc Jones]

Marc Jones ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7221

-gerrit

commit 49e7eed3e8837fd2525d571bd66c262afd4ede48
Author: Julius Werner 
Date:   Wed Apr 2 17:28:46 2014 -0700

libpayload: usb: ehci: Honor 10ms reset recovery period

This patch adds the 10ms TRSTRCY delay between a reset and the following
    Set Address command that is required by the USB 2.0 specification to the
    EHCI root hub driver. The generic_hub driver that's used for XHCI and
    external hubs already included this delay. This is such a glaring
    violation of the spec that I'm really amazed how many USB 2.0 devices
    we tested before seemed perfectly fine with responding to a Set Address
    within 2 microframes of the reset...

It also increases the port reset hold delay by one millisecond to avoid
    an ugly race condition on Tegra SoCs: they decided to time the 50ms
    themselves instead of relying on the CPU to do it (fair enough), and to
    automatically transition Port Reset to 0 and Port Enable to 1 after that
    (bad idea). If the CPU's read-modify-write to clear Port Reset races
    exactly with the host controller setting Port Enable, we may end up
    clearing the bit again and going into the companion controller handoff
    path later on. The added millisecond shouldn't cause any problems for
    other host controllers and is not a big deal compared to other delays in
    this code path.

BUG=chrome-os-partner:26749
    TEST=Run several dozen reboot loops with The USB Stick of Death (TM) (a
    blue Patriot XT 13fe:5200 with bcdDevice = 1.00), make sure it always
    gets detected correctly.

Original-Change-Id: Idd3329ae6d7e5e1c07a84a5475549b3459836b31
    Original-Signed-off-by: Julius Werner 
    Original-Reviewed-on: https://chromium-review.googlesource.com/189872
    Original-Reviewed-by: Gabe Black 
    Original-Reviewed-by: Jim Lin 
    Original-Reviewed-by: Hung-Te Lin 
    (cherry picked from commit 4deca38e9d79f6373f4418fcaf51a6945232c8b8)
    Signed-off-by: Marc Jones

Change-Id: I68a29bfd2e0f30409fbfc330b2575f0f9f61a79d
---
 payloads/libpayload/drivers/usb/ehci_rh.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c
index 5c4daed..67f63cc 100644
--- a/payloads/libpayload/drivers/usb/ehci_rh.c
+++ b/payloads/libpayload/drivers/usb/ehci_rh.c
@@ -98,8 +98,8 @@ ehci_rh_scanport (usbdev_t *dev, int port)
    	 */
    	RH_INST(dev)->ports[port] = (RH_INST(dev)->ports[port] & ~P_PORT_ENABLE) | P_PORT_RESET;

-		/* Wait a bit while reset is active. */
-		mdelay(50); // usb20 spec 7.1.7.5 (TDRSTR)
+		/* Wait a bit while reset is active (+1 to avoid Tegra race). */
+		mdelay(50 + 1); // usb20 spec 7.1.7.5 (TDRSTR)

/* Deassert reset. */
    	RH_INST(dev)->ports[port] &= ~P_PORT_RESET;
@@ -113,6 +113,8 @@ ehci_rh_scanport (usbdev_t *dev, int port)
    		return;
    	}

+		mdelay(10); /* TRSTRCY (USB 2.0 spec 7.1.7.5) */
+
    	/* If the host controller enabled the port, it's a high-speed
    	 * device, otherwise it's full-speed.
    	 */