coreboot-gerrit January 2014

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Patch merged into coreboot/master: 8c75bda Add the gizmosphere/gizmo mainboard
by gerrit＠coreboot.org 03 Jan '14

03 Jan '14

the following patch was just integrated into master: commit 8c75bda16e7d6b21cbf4ad5183153febed7689b7 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Dec 11 12:38:40 2013 -0700 Add the gizmosphere/gizmo mainboard Gizmo is a AMD-Family14 based board. More information can be found at www.gizmosphere.org Change-Id: I5cfd161b4f408be1f65cf332b083ed7c79a99cfd Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/4536 for details. -gerrit

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New patch to review for coreboot: 7b275f8 ACPI: Remove CONFIG_GENERATE_ACPI_TABLES
by Vladimir Serbinenko 03 Jan '14

03 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4609 -gerrit commit 7b275f86fddcbf7dbf4d3ebc54abd2546fa1fca3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Jan 3 15:55:40 2014 +0100 ACPI: Remove CONFIG_GENERATE_ACPI_TABLES As currently many systems would be barely functional without ACPI, always generate ACPI tables if supported. Change-Id: I372dbd03101030c904dab153552a1291f3b63518 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 11 ----------- src/arch/armv7/Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/boot/Makefile.inc | 4 ++-- src/arch/x86/boot/smbios.c | 2 +- src/arch/x86/boot/tables.c | 2 +- src/arch/x86/include/arch/acpi.h | 6 +++--- src/cpu/amd/model_fxx/Makefile.inc | 2 +- src/cpu/intel/fsp_model_206ax/Makefile.inc | 2 +- src/cpu/intel/haswell/Makefile.inc | 2 +- src/cpu/intel/model_2065x/Makefile.inc | 2 +- src/cpu/intel/model_206ax/Makefile.inc | 2 +- src/cpu/intel/speedstep/Makefile.inc | 2 +- src/lib/coreboot_table.c | 4 ++-- src/mainboard/advansus/a785e-i/mptable.c | 2 +- src/mainboard/amd/bimini_fam10/mptable.c | 2 +- src/mainboard/amd/dbm690t/mptable.c | 2 +- src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/mahogany/mptable.c | 2 +- src/mainboard/amd/mahogany_fam10/mptable.c | 2 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/amd/pistachio/mptable.c | 2 +- src/mainboard/amd/south_station/mptable.c | 2 +- src/mainboard/amd/tilapia_fam10/mptable.c | 2 +- src/mainboard/amd/torpedo/mptable.c | 2 +- src/mainboard/amd/union_station/mptable.c | 2 +- src/mainboard/asrock/939a785gmh/mptable.c | 2 +- src/mainboard/asrock/e350m1/mptable.c | 2 +- src/mainboard/asus/m4a78-em/mptable.c | 2 +- src/mainboard/asus/m4a785-m/mptable.c | 2 +- src/mainboard/asus/m5a88-v/mptable.c | 2 +- src/mainboard/avalue/eax-785e/mptable.c | 2 +- src/mainboard/emulation/qemu-i440fx/fw_cfg.c | 6 +++--- src/mainboard/gigabyte/ma785gm/mptable.c | 2 +- src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +- src/mainboard/gigabyte/ma78gm/mptable.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +- src/mainboard/jetway/pa78vm5/mptable.c | 2 +- src/mainboard/kontron/kt690/mptable.c | 2 +- src/mainboard/lippert/frontrunner-af/mptable.c | 2 +- src/mainboard/lippert/toucan-af/mptable.c | 2 +- src/mainboard/roda/rk9/mainboard.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +- src/mainboard/technexion/tim5690/mptable.c | 2 +- src/mainboard/technexion/tim8690/mptable.c | 2 +- src/northbridge/amd/agesa/family10/Makefile.inc | 2 +- src/northbridge/amd/agesa/family12/Makefile.inc | 2 +- src/northbridge/amd/amdfam10/Makefile.inc | 14 +++++++------- src/northbridge/amd/amdk8/Makefile.inc | 2 +- src/northbridge/intel/fsp_sandybridge/Makefile.inc | 2 +- src/northbridge/intel/gm45/Makefile.inc | 2 +- src/northbridge/intel/haswell/Makefile.inc | 2 +- src/northbridge/intel/i945/Makefile.inc | 2 +- src/northbridge/intel/nehalem/Makefile.inc | 2 +- src/northbridge/intel/sandybridge/Makefile.inc | 2 +- src/northbridge/intel/sch/Makefile.inc | 2 +- src/northbridge/intel/sch/acpi.c | 2 +- src/southbridge/amd/agesa/hudson/Makefile.inc | 2 +- src/southbridge/amd/amd8111/acpi.c | 4 ++-- src/southbridge/amd/cimx/sb800/Makefile.inc | 2 +- src/southbridge/amd/sb700/Makefile.inc | 2 +- src/southbridge/amd/sb800/Makefile.inc | 2 +- src/southbridge/intel/i82371eb/Makefile.inc | 4 ++-- src/southbridge/nvidia/ck804/Makefile.inc | 2 +- src/southbridge/nvidia/mcp55/Makefile.inc | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 4 ++-- src/southbridge/via/vt8237r/Makefile.inc | 2 +- 67 files changed, 81 insertions(+), 92 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 88df9ae..e2e5724 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -434,8 +434,6 @@ config HAVE_ACPI_TABLES help This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. - Whether or not the ACPI tables are actually generated by coreboot - is configurable by the user via GENERATE_ACPI_TABLES. config HAVE_MP_TABLE bool @@ -474,15 +472,6 @@ config MULTIBOOT default y depends on ARCH_X86 -config GENERATE_ACPI_TABLES - prompt "Generate ACPI tables" if HAVE_ACPI_TABLES - bool - default HAVE_ACPI_TABLES - help - Generate ACPI tables for this board. - - If unsure, say Y. - config GENERATE_MP_TABLE prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC bool diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index dfd5164..4cf8d9d 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -200,7 +200,7 @@ endif ifeq ($(CONFIG_BOARD_HAS_HARD_RESET),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c endif -ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y) +ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/dsdt.asl # make doesn't have arithmetic operators or greater-than comparisons diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2ade820..699ab2c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -280,7 +280,7 @@ endif ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/reset.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c endif -ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y) +ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/dsdt.asl ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt2.asl),) diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 3e53d79..ae7b7da 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -8,9 +8,9 @@ ramstage-y += tables.c ramstage-y += cbmem.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += ramstage_module_header.c diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 65bf538..e98a775 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -164,7 +164,7 @@ static int smbios_write_type0(unsigned long *current, int handle) BIOS_CHARACTERISTICS_SELECTABLE_BOOT | BIOS_CHARACTERISTICS_UPGRADEABLE; -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI; #endif t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET; diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index eea9bf1..63066ba 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -113,7 +113,7 @@ struct lb_memory *write_tables(void) } #endif /* CONFIG_GENERATE_MP_TABLE */ -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES #define MAX_ACPI_SIZE (45 * 1024) post_code(0x9c); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 306f7da..592004e 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -27,7 +27,7 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES #include <stdint.h> @@ -575,11 +575,11 @@ unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current); /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(void); -#else // CONFIG_GENERATE_ACPI_TABLES +#else // CONFIG_HAVE_ACPI_TABLES #define write_acpi_tables(start) (start) #define acpi_slp_type 0 -#endif /* CONFIG_GENERATE_ACPI_TABLES */ +#endif /* CONFIG_HAVE_ACPI_TABLES */ #endif /* __ASM_ACPI_H */ diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index eb62640..cf4ac21 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -4,4 +4,4 @@ romstage-y += ../../x86/mtrr/earlymtrr.c ramstage-y += model_fxx_init.c ramstage-y += model_fxx_update_microcode.c ramstage-y += processor_name.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += powernow_acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc index 1ea9c2a..48af5bb 100644 --- a/src/cpu/intel/fsp_model_206ax/Makefile.inc +++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc @@ -1,7 +1,7 @@ ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 60c061d..116e5b8 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -5,7 +5,7 @@ ramstage-y += tsc_freq.c romstage-y += romstage.c romstage-y += tsc_freq.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 3b3fc4e..b969c4c 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -13,7 +13,7 @@ ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index a324b64..c98513b 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -1,7 +1,7 @@ ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/cpu/intel/speedstep/Makefile.inc b/src/cpu/intel/speedstep/Makefile.inc index 130eb0c..e6f74d3 100644 --- a/src/cpu/intel/speedstep/Makefile.inc +++ b/src/cpu/intel/speedstep/Makefile.inc @@ -1,2 +1,2 @@ -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c speedstep.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c speedstep.c ramstage-$(CONFIG_CPU_INTEL_MODEL_1067X) += speedstep.c diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 772729a..e921a64 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -34,7 +34,7 @@ #include <option_table.h> #endif #if CONFIG_CHROMEOS -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES #include <arch/acpi.h> #endif #include <vendorcode/google/chromeos/chromeos.h> @@ -194,7 +194,7 @@ static void lb_gpios(struct lb_header *header) static void lb_vdat(struct lb_header *header) { -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES struct lb_vdat* vdat; vdat = (struct lb_vdat *)lb_new_record(header); diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c index 73ada4d..11766d9 100644 --- a/src/mainboard/advansus/a785e-i/mptable.c +++ b/src/mainboard/advansus/a785e-i/mptable.c @@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c index 792fa41..9b14e91 100644 --- a/src/mainboard/amd/bimini_fam10/mptable.c +++ b/src/mainboard/amd/bimini_fam10/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 8ef9138..b36e63c 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 7352205..325269c 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index e83837d..591f17b 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index 9f5eb12..d53b42f 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 6b8aaa6..8ede89c 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index 8ef9138..b36e63c 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index e9175d8..1f32c84 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c index c4ec478..42658b6 100644 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ b/src/mainboard/amd/tilapia_fam10/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index da97d6a..6b282c8 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin)) #else diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index e9175d8..1f32c84 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c index 8e663ec..db5ad0f 100644 --- a/src/mainboard/asrock/939a785gmh/mptable.c +++ b/src/mainboard/asrock/939a785gmh/mptable.c @@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 95df2a6..0fc4110 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c index c4ec478..42658b6 100644 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ b/src/mainboard/asus/m4a78-em/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c index c4ec478..42658b6 100644 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ b/src/mainboard/asus/m4a785-m/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c index cb7aeee..e291440 100644 --- a/src/mainboard/asus/m5a88-v/mptable.c +++ b/src/mainboard/asus/m5a88-v/mptable.c @@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c index 1889e02..bfcfd34 100644 --- a/src/mainboard/avalue/eax-785e/mptable.c +++ b/src/mainboard/avalue/eax-785e/mptable.c @@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 047f211..d22e047 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -20,7 +20,7 @@ #include <smbios.h> #include <console/console.h> #include <arch/io.h> -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES # include <arch/acpigen.h> #endif @@ -123,7 +123,7 @@ int fw_cfg_max_cpus(void) /* ---------------------------------------------------------------------- */ -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES /* * Starting with release 1.7 qemu provides acpi tables via fw_cfg. @@ -314,7 +314,7 @@ err: return 0; } -#endif /* CONFIG_GENERATE_ACPI_TABLES */ +#endif /* CONFIG_HAVE_ACPI_TABLES */ /* ---------------------------------------------------------------------- */ /* pick up smbios information from fw_cfg */ diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c index c4ec478..42658b6 100644 --- a/src/mainboard/gigabyte/ma785gm/mptable.c +++ b/src/mainboard/gigabyte/ma785gm/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c index c4ec478..42658b6 100644 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ b/src/mainboard/gigabyte/ma785gmt/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c index c4ec478..42658b6 100644 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ b/src/mainboard/gigabyte/ma78gm/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index 64274de..2a4e529 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c index 949501b..54aa8ec 100644 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ b/src/mainboard/jetway/pa78vm5/mptable.c @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c index 6a94479..0f97e64 100644 --- a/src/mainboard/kontron/kt690/mptable.c +++ b/src/mainboard/kontron/kt690/mptable.c @@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 6b8aaa6..8ede89c 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 6b8aaa6..8ede89c 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index 33e6bde..96043be 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -31,7 +31,7 @@ #include <ec/acpi/ec.h> #include "hda_verb.h" -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES #include "cstates.c" /* Include it, as the linker won't find the overloaded weak function in there. */ #endif diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 01a6980..2be07ba 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin)) #else diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c index 6a94479..0f97e64 100644 --- a/src/mainboard/technexion/tim5690/mptable.c +++ b/src/mainboard/technexion/tim5690/mptable.c @@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 6a94479..0f97e64 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES +#if !CONFIG_HAVE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/northbridge/amd/agesa/family10/Makefile.inc b/src/northbridge/amd/agesa/family10/Makefile.inc index 9676d54..a10a4a1 100644 --- a/src/northbridge/amd/agesa/family10/Makefile.inc +++ b/src/northbridge/amd/agesa/family10/Makefile.inc @@ -19,4 +19,4 @@ ramstage-y += northbridge.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.asl diff --git a/src/northbridge/amd/agesa/family12/Makefile.inc b/src/northbridge/amd/agesa/family12/Makefile.inc index 9676d54..a10a4a1 100644 --- a/src/northbridge/amd/agesa/family12/Makefile.inc +++ b/src/northbridge/amd/agesa/family12/Makefile.inc @@ -19,4 +19,4 @@ ramstage-y += northbridge.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.asl diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc index a24783b..bae7c18 100644 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ b/src/northbridge/amd/amdfam10/Makefile.inc @@ -1,13 +1,13 @@ ramstage-y += northbridge.c ramstage-y += misc_control.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr1.asl -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr2.asl -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr3.asl -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr4.asl -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr5.asl +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.asl +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sspr1.asl +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sspr2.asl +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sspr3.asl +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sspr4.asl +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sspr5.asl ramstage-y += get_pci1234.c diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc index 38b0201..eeef9e8 100644 --- a/src/northbridge/amd/amdk8/Makefile.inc +++ b/src/northbridge/amd/amdk8/Makefile.inc @@ -1,7 +1,7 @@ ramstage-y += northbridge.c ramstage-y += misc_control.c ramstage-y += get_sblk_pci1234.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c # Enable this if you want to check the values of the PCI routing registers. # Call show_all_routes() anywhere amdk8.h is included. diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc index 5bc3d58..ec855ce 100644 --- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc +++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc @@ -21,7 +21,7 @@ ramstage-y += northbridge.c ramstage-y += gma.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += fsp_util.c ramstage-$(CONFIG_ENABLE_FAST_BOOT) += mrccache.c diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 01cf855..49341f4 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -31,7 +31,7 @@ romstage-y += pm.c romstage-y += ram_calc.c romstage-$(CONFIG_IOMMU) += iommu.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += ram_calc.c ramstage-y += northbridge.c diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 04b0d2f..4acefc2 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -20,7 +20,7 @@ ramstage-y += northbridge.c ramstage-y += gma.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c ramstage-y += minihd.c diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 92a8849..a6d9a3e 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -19,7 +19,7 @@ ramstage-y += northbridge.c ramstage-y += gma.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c romstage-y += raminit.c romstage-y += early_init.c diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 6c53f49..7ce38b0 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -20,7 +20,7 @@ ramstage-y += northbridge.c ramstage-y += gma.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += ../sandybridge/mrccache.c romstage-y += raminit.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index be07e93..b3d9ccd 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -20,7 +20,7 @@ ramstage-y += northbridge.c ramstage-y += gma.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c romstage-y += raminit.c diff --git a/src/northbridge/intel/sch/Makefile.inc b/src/northbridge/intel/sch/Makefile.inc index 6124a8c..b7b87a5 100644 --- a/src/northbridge/intel/sch/Makefile.inc +++ b/src/northbridge/intel/sch/Makefile.inc @@ -20,4 +20,4 @@ ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += port_access.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c diff --git a/src/northbridge/intel/sch/acpi.c b/src/northbridge/intel/sch/acpi.c index 6dd495f..df591f9 100644 --- a/src/northbridge/intel/sch/acpi.c +++ b/src/northbridge/intel/sch/acpi.c @@ -66,7 +66,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) if (!pciexbar) return current; -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); #endif diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 6a097fc..1e655c1 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -10,7 +10,7 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index b734846..fda6924 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -89,7 +89,7 @@ static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buf } -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES unsigned pm_base; #endif @@ -162,7 +162,7 @@ static void acpi_init(struct device *dev) (on*12)+(on>>1),(on&1)*5); } -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES pm_base = pci_read_config16(dev, 0x58) & 0xff00; printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base); #endif diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 2ed5096..82ca998 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -32,7 +32,7 @@ ramstage-y += reset.c ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 677aaad..6e772fe 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -7,7 +7,7 @@ ramstage-y += ide.c ramstage-y += sata.c ramstage-y += hda.c ramstage-y += pci.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c romstage-y += reset.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc index db75d3f..d665af4 100644 --- a/src/southbridge/amd/sb800/Makefile.inc +++ b/src/southbridge/amd/sb800/Makefile.inc @@ -7,7 +7,7 @@ ramstage-y += sata.c ramstage-y += hda.c ramstage-y += pci.c ramstage-y += pcie.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 179ff8f..0aae455 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -24,8 +24,8 @@ ramstage-y += ide.c ramstage-y += usb.c ramstage-y += smbus.c ramstage-y += reset.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c romstage-y += early_pm.c diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index b249f7e..db062f5 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -13,7 +13,7 @@ ramstage-y += ht.c ramstage-y += reset.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 29ad438..03a34eb 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -11,7 +11,7 @@ ramstage-y += smbus.c ramstage-y += usb2.c ramstage-y += usb.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3b3f86a..c5081a4 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -93,7 +93,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES unsigned pm_base; #endif @@ -112,7 +112,7 @@ static void mcp55_sm_read_resources(device_t dev) static void mcp55_sm_init(device_t dev) { -#if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES struct resource *res; res = find_resource(dev, 0x60); diff --git a/src/southbridge/via/vt8237r/Makefile.inc b/src/southbridge/via/vt8237r/Makefile.inc index 71404d2..de69ffd 100644 --- a/src/southbridge/via/vt8237r/Makefile.inc +++ b/src/southbridge/via/vt8237r/Makefile.inc @@ -24,6 +24,6 @@ ramstage-y += lpc.c ramstage-y += sata.c ramstage-y += usb.c ramstage-$(CONFIG_PIRQ_ROUTE) += pirq.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

1 0

New patch to review for coreboot: dbcbae8 device/Kconfig: Add third person singular s to lacks
by Paul Menzel 03 Jan '14

03 Jan '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4608 -gerrit commit dbcbae8aa22ae70f4cb1da8f0e56a8d1aa77fed9 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jan 3 09:45:57 2014 +0100 device/Kconfig: Add third person singular s to lacks Change-Id: I74be0dbbf8d99f58ac28bfac281ccd27d1500078 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/device/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index cb951d9..2d6e226 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -32,7 +32,7 @@ config MAINBOARD_DO_NATIVE_VGA_INIT help Some mainboards, such as the Google Link, allow initializing the display without the need of a binary only VGA OPROM. Enabling this option may be - faster, but also lack flexibility in setting modes. + faster, but also lacks flexibility in setting modes. If unsure, say N.

1 0

Patch set updated for coreboot: 88b6001 X201: Fix native video init
by Vladimir Serbinenko 03 Jan '14

03 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4606 -gerrit commit 88b60019754462ad41dfcc41beaa0fdcda09e606 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Jan 3 04:27:39 2014 +0100 X201: Fix native video init Due to recent restructuring X201 native video init has disappeared form config options. Put it back and fix compilation with it. Change-Id: I6d9ba5da196c093abd2df89a6fe5efefece1fb3c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Kconfig | 1 + src/northbridge/intel/nehalem/gma.c | 16 +++------------- 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 1204e23..a2d66b3 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select EARLY_CBMEM_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 31068d1..c7a0e9b 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -548,10 +548,12 @@ static void gma_pm_init_pre_vbios(struct device *dev) #include <pc80/vga.h> #include <pc80/vga_io.h> +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT static void fake_vbios(void) { #include "fake_vbios.c" } +#endif static void gma_pm_init_post_vbios(struct device *dev) { @@ -635,8 +637,8 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); #else printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); -#endif fake_vbios(); +#endif /* Linux relies on VBT for panel info. */ if (read16(0xc0000) != 0xaa55) { @@ -670,18 +672,6 @@ static void gma_func0_init(struct device *dev) /* Post VBIOS init */ gma_pm_init_post_vbios(dev); - -#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - /* This should probably run before post VBIOS init. */ - u32 iobase, mmiobase, physbase, graphics_base; - iobase = dev->resource_list[2].base; - mmiobase = dev->resource_list[0].base; - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - graphics_base = dev->resource_list[1].base; - - int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); - i915lightup(physbase, iobase, mmiobase, graphics_base); -#endif } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

1 0

New patch to review for coreboot: 218eec1 usbdebug: Fix hidden menuconfig options
by Kyösti Mälkki 03 Jan '14

03 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4607 -gerrit commit 218eec1d190846436ed63eb72b3f310f05817d58 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 3 08:20:50 2014 +0200 usbdebug: Fix hidden menuconfig options Options for selecting the USB port and controller for usbdebug were unintentionally hidden with commit 8232bc2c on AGESA platforms using cimx/sb700 or cimx/sb800. Change-Id: Ibacc81a580519fe7fa86f08374046625327340b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/cimx/sb700/Kconfig | 2 +- src/southbridge/amd/cimx/sb800/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 570f3c2..4304357 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -20,7 +20,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB700 bool select IOAPIC - select HAVE_USBDEBUG + select HAVE_USBDEBUG_OPTIONS select AMD_SB_CIMX select HAVE_HARD_RESET diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 8ccbe4d..37aff9e 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -21,7 +21,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 bool default n select IOAPIC - select HAVE_USBDEBUG + select HAVE_USBDEBUG_OPTIONS select AMD_SB_CIMX select HAVE_HARD_RESET

1 0

New patch to review for coreboot: 3b7c834 X201: Fix native video init
by Vladimir Serbinenko 03 Jan '14

03 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4606 -gerrit commit 3b7c83424b460b9b2bcaf41f5279b5cf254f4968 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Jan 3 04:27:39 2014 +0100 X201: Fix native video init Due to recent restructuring X201 native video init has disappeared form config options. Put it back and fix compilation with it. Change-Id: I6d9ba5da196c093abd2df89a6fe5efefece1fb3c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Kconfig | 1 + src/northbridge/intel/nehalem/gma.c | 12 ------------ 2 files changed, 1 insertion(+), 12 deletions(-) diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 1204e23..a2d66b3 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select EARLY_CBMEM_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 31068d1..f0ff228 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -670,18 +670,6 @@ static void gma_func0_init(struct device *dev) /* Post VBIOS init */ gma_pm_init_post_vbios(dev); - -#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - /* This should probably run before post VBIOS init. */ - u32 iobase, mmiobase, physbase, graphics_base; - iobase = dev->resource_list[2].base; - mmiobase = dev->resource_list[0].base; - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - graphics_base = dev->resource_list[1].base; - - int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); - i915lightup(physbase, iobase, mmiobase, graphics_base); -#endif } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

1 0

Patch set updated for coreboot: b55669f cpu/allwinner/a10: Implement udelay using timer 0
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4595 -gerrit commit b55669fb88b972a9dbe1a6bb62c207b3d0d715e5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Dec 31 00:17:19 2013 -0500 cpu/allwinner/a10: Implement udelay using timer 0 Change-Id: I4825f0d57696cd28751c59ae133b7e3315fb78e5 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Kconfig | 1 + src/cpu/allwinner/a10/timer.c | 42 ++++++++++++++++++-- src/cpu/allwinner/a10/timer.h | 90 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+), 3 deletions(-) diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 3df1ceb..b782b9a 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -6,6 +6,7 @@ if CPU_ALLWINNER_A10 config CPU_SPECIFIC_OPTIONS def_bool y + select HAVE_INIT_TIMER select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select HAVE_UART_MEMORY_MAPPED diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c index e156398..60cc60c 100644 --- a/src/cpu/allwinner/a10/timer.c +++ b/src/cpu/allwinner/a10/timer.c @@ -1,19 +1,55 @@ /* - * Placeholder for code to come(needed to complete build) + * Timer control and delays for Allwinner CPUs * * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * Subject to the GNU GPL v2, or (at your option) any later version. */ +#include "timer.h" + +#include <arch/io.h> #include <delay.h> #include <timer.h> +struct a1x_timer *const tmr0 = + &((struct a1x_timer_module *)A1X_TIMER_BASE)->timer[0]; + +static inline u32 read_timer(void) +{ + return read32(&tmr0->val); +} + void init_timer(void) { - /* Stub */ + u32 reg32; + /* Load the timer rollover value */ + write32(0xffffffff, &tmr0->interval); + /* Configure the timer to run from 24MHz oscillator, no prescaler */ + reg32 = TIMER_CTRL_PRESC_DIV_EXP(0); + reg32 |= TIMER_CTRL_CLK_SRC_OSC24M; + reg32 |= TIMER_CTRL_RELOAD; + reg32 |= TIMER_CTRL_TMR_EN; + write32(reg32, &tmr0->ctrl); } void udelay(unsigned usec) { - /* Stub */ + u32 curr_tick, last_tick; + s32 ticks_left; + + last_tick = read_timer(); + /* 24 timer ticks per microsecond (24 MHz, divided by 1) */ + ticks_left = usec * 24; + + /* FIXME: Should we consider timer rollover? + * From when we start the timer, we have almost three minutes before it + * rolls over, so we should be long into having booted our payload. + */ + while (ticks_left > 0) { + curr_tick = read_timer(); + /* Timer value decreases with each tick */ + ticks_left -= last_tick - curr_tick; + last_tick = curr_tick; + } + } diff --git a/src/cpu/allwinner/a10/timer.h b/src/cpu/allwinner/a10/timer.h new file mode 100644 index 0000000..9c0c0d1 --- /dev/null +++ b/src/cpu/allwinner/a10/timer.h @@ -0,0 +1,90 @@ +/* + * Definitions for timer control on Allwinner CPUs + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_TIMER_H +#define CPU_ALLWINNER_A10_TIMER_H + +#include "memmap.h" +#include <types.h> + +/* TMRx_CTRL values */ +#define TIMER_CTRL_MODE_SINGLE (1 << 7) +#define TIMER_CTRL_PRESC_MASK (0x7 << 4) +#define TIMER_CTRL_PRESC_DIV_EXP(ep) ((ep << 4) & TIMER_CTRL_PRESC_MASK) +#define TIMER_CTRL_CLK_SRC_MASK (0x3 << 2) +#define TIMER_CTRL_CLK_SRC_LOSC (0x0 << 2) +#define TIMER_CTRL_CLK_SRC_OSC24M (0x1 << 2) +#define TIMER_CTRL_CLK_SRC_PLL6 (0x2 << 2) +#define TIMER_CTRL_RELOAD (1 << 1) +#define TIMER_CTRL_TMR_EN (1 << 0) + +/* General purpose timer */ +struct a1x_timer { + u32 ctrl; + u32 interval; + u32 val; + u8 res[4]; +} __attribute__ ((packed)); + +/* Audio video sync*/ +struct a1x_avs { + u32 ctrl; /* 0x80 */ + u32 cnt0; /* 0x84 */ + u32 cnt1; /* 0x88 */ + u32 div; /* 0x8c */ +} __attribute__ ((packed)); + +/* Watchdog */ +struct a1x_wdog { + u32 ctrl; /* 0x90 */ + u32 mode; /* 0x94 */ +} __attribute__ ((packed)); + +/* 64 bit counter */ +struct a1x_64cnt { + u32 ctrl; /* 0xa0 */ + u32 lo; /* 0xa4 */ + u32 hi; /* 0xa8 */ +} __attribute__ ((packed)); + +/* Rtc */ +struct a1x_rtc { + u32 ctrl; /* 0x100 */ + u32 yymmdd; /* 0x104 */ + u32 hhmmss; /* 0x108 */ +} __attribute__ ((packed)); + +/* Alarm */ +struct a1x_alarm { + u32 ddhhmmss; /* 0x10c */ + u32 hhmmss; /* 0x110 */ + u32 en; /* 0x114 */ + u32 irq_en; /* 0x118 */ + u32 irq_sta; /* 0x11c */ +} __attribute__ ((packed)); + +struct a1x_timer_module { + u32 irq_en; /* 0x00 */ + u32 irq_sta; /* 0x04 */ + u8 res1[8]; + struct a1x_timer timer[6]; /* We have 6 timers */ + u8 res2[16]; + struct a1x_avs avs; + struct a1x_wdog wdog; + u8 res3[8]; + struct a1x_64cnt cnt64; + u8 res4[0x58]; + struct a1x_rtc rtc; + struct a1x_alarm alarm; + u32 gp_data[4]; + u8 res5[8]; + u32 cpu_cfg; +} __attribute__ ((packed)); + +#endif /* CPU_ALLWINNER_A10_TIMER_H */

1 0

Patch set updated for coreboot: 1bc4508 cpu/allwinner/a10: Add definition for gating GPIO S clock
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4592 -gerrit commit 1bc4508c44d04218a0053f9044d71769ea29c034 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Dec 31 15:34:43 2013 -0500 cpu/allwinner/a10: Add definition for gating GPIO S clock This bit is not documented in the datasheet, but is used in the upcoming RAM init code. Change-Id: I697ec222496236ac7690460ee62313ab8b1a2f0b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/clock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index b9a0771..9656469 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -85,6 +85,8 @@ enum a1x_clken { A1X_CLKEN_SPI2, A1X_CLKEN_SPI3, A1X_CLKEN_PATA, + RSVD_0x60_25, + A1X_CLKEN_GPS, /* AHB1 module clock gating */ A1X_CLKEN_DRAM_VE = (0x64 << 5), A1X_CLKEN_TVD,

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Patch set updated for coreboot: 49c66cc cpu/allwinner/a10: Add low-level helpers for DRAM clock control
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4593 -gerrit commit 49c66ccd27ea2f20a930feb9e01a8e122713f23f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Dec 31 13:20:27 2013 -0500 cpu/allwinner/a10: Add low-level helpers for DRAM clock control PLL5 is special in that it controls the DRAM clock, and requires a fine-grained low-level control which will be needed by raminit code. This change also brings functionality which will be needed by raminit. Change-Id: I25ecc91aa2154e504ceebb9003a5e5728d47f4a3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/clock.c | 81 +++++++++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/clock.h | 28 +++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c index 87a3574..c53247e 100644 --- a/src/cpu/allwinner/a10/clock.c +++ b/src/cpu/allwinner/a10/clock.c @@ -9,6 +9,8 @@ #include <arch/io.h> +static struct a10_ccm *const ccm = (void *)A1X_CCM_BASE; + /** * \brief Enable the clock source for the peripheral * @@ -40,3 +42,82 @@ void a1x_periph_clock_disable(enum a1x_clken periph) reg32 &= ~(1 << (periph & 0x1f)); write32(reg32, addr); } + +/** + * \brief Configure PLL5 factors + * + * This is a low-level accessor to configure the divisors and multipliers of + * PLL5. PLL5 uses two factors to multiply the 24MHz oscillator clock to + * generate a pre-clock. The pre-divided clock is then divided by one of two + * independent divisors, one for DRAM, and another for peripherals clocked from + * this PLL. If the PLL was previously disabled, this function will enable it. + * Other than that, this function only modifies these factors, and leaves the + * other settings unchanged. + * + * The output clocks are give by the following formulas: + * + * Pre-clock = (24 MHz * N * K) <- Must be between 240MHz and 2GHz + * DRAM clock = pre / M + * Other module = pre / P + * + * It is the caller's responsibility to make sure the pre-divided clock falls + * within the operational range of the PLL, and that the divisors and + * multipliers are within their ranges. + * + * @param[in] mul_n Multiplier N, between 0 and 32 + * @param[in] mul_k Multiplier K, between 1 and 4 + * @param[in] div_m DRAM clock divisor, between 1 and 4 + * @param[in] exp_div_p Peripheral clock divisor exponent, between 0 and 3 + * (P = 1/2/4/8, respectively) + */ +void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p) +{ + u32 reg32; + + reg32 = read32(&ccm->pll5_cfg); + reg32 &= ~(PLL5_FACTOR_M_MASK | PLL5_FACTOR_N_MASK | + PLL5_FACTOR_K_MASK | PLL5_DIV_EXP_P_MASK); + /* The M1 factor is not documented in the datasheet, and the reference + * raminit code does not use it. Whether this is a fractional divisor, + * or an additional divisor is unknown, so don't use it for now */ + reg32 &= ~PLL5_FACTOR_M1_MASK; + reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) | + PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p)); + reg32 |= PLL5_PLL_ENABLE; + write32(reg32, &ccm->pll5_cfg); +} + +/** + * \brief Enable the clock output to DRAM chips + * + * This enables the DRAM clock to be sent to DRAM chips. This should normally be + * done after PLL5 is configured and locked. Note that the clock may be gated, + * and also needs to be ungated in order to reach the DDR chips. + * Also see @ref clock_ungate_dram_clk_output + */ +void a1x_pll5_enable_dram_clock_output(void) +{ + setbits_le32(&ccm->pll5_cfg, PLL5_DDR_CLK_OUT_EN); +} + +/** + * \brief Ungate the clock to DRAM chips + * + * Although the DRAM clock output may be enabled, it is by default gated. It + * needs to be ungated before reaching DRAM. + */ +void a1x_ungate_dram_clock_output(void) +{ + setbits_le32(&ccm->dram_clk_cfg, DRAM_CTRL_DCLK_OUT); +} + +/** + * \brief Gate the clock to DRAM chips + * + * Disable the clock to DRAM without altering PLL configuration, by closing the + * DRAM clock gate. + */ +void a1x_gate_dram_clock_output(void) +{ + clrbits_le32(&ccm->dram_clk_cfg, DRAM_CTRL_DCLK_OUT); +} diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index 9656469..41400ab 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -43,6 +43,29 @@ #define APB1_RAT_M_MASK 0x1f << 0) #define APB1_RAT_M(n) (((n) & 0x1f) << 0) +/* PLL5_CFG values */ +#define PLL5_PLL_ENABLE (1 << 31) +#define PLL5_OUT_BYPASS_EN (1 << 30) +#define PLL5_DDR_CLK_OUT_EN (1 << 29) +#define PLL5_DIV_EXP_P_MASK (0x3 << 16) +#define PLL5_DIV_EXP_P(ep) ((ep << 16) & PLL5_DIV_EXP_P_MASK) +#define PLL5_DIV_P_1 (0x0 << 16) +#define PLL5_DIV_P_2 (0x1 << 16) +#define PLL5_DIV_P_4 (0x2 << 16) +#define PLL5_DIV_P_8 (0x3 << 16) +#define PLL5_FACTOR_N_MASK (0x1f << 8) +#define PLL5_FACTOR_N(n) ((n << 8) & PLL5_FACTOR_N_MASK) +#define PLL5_LDO_EN (1 << 7) +#define PLL5_FACTOR_K_MASK (0x3 << 4) +#define PLL5_FACTOR_K(k) ((((k) - 1) << 4) & PLL5_FACTOR_K_MASK) +#define PLL5_FACTOR_M1_MASK (0x3 << 2) +#define PLL5_FACTOR_M1(m1) (((m1) << 2) & PLL5_FACTOR_M1_MASK) +#define PLL5_FACTOR_M_MASK (0x3 << 0) +#define PLL5_FACTOR_M(m) ((((m) - 1) << 0) & PLL5_FACTOR_M_MASK) + +/* DRAM_CLK values*/ +#define DRAM_CTRL_DCLK_OUT (1 << 15) + /** * \brief Clock gating definitions * @@ -228,4 +251,9 @@ struct a10_ccm { void a1x_periph_clock_enable(enum a1x_clken periph); void a1x_periph_clock_disable(enum a1x_clken periph); +void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p); +void a1x_pll5_enable_dram_clock_output(void); +void a1x_ungate_dram_clock_output(void); +void a1x_gate_dram_clock_output(void); + #endif /* CPU_ALLWINNER_A10_CLOCK_H */

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Patch set updated for coreboot: 630267b cpu/allwinner/a10: Add definitions for in/output GPIO functions
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4598 -gerrit commit 630267b2da5b9424725406d2efb73ff3e31d72eb Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 2 03:22:03 2014 -0500 cpu/allwinner/a10: Add definitions for in/output GPIO functions Change-Id: I2b857d3b4c01e39c62e54f753e400e6049f1dbc9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/gpio.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h index 709f74b..e4b24ea 100644 --- a/src/cpu/allwinner/a10/gpio.h +++ b/src/cpu/allwinner/a10/gpio.h @@ -23,6 +23,10 @@ #define GPI 8 #define GPS 9 +/* GPIO pad functions valid for all pins */ +#define GPIO_PIN_FUNC_INPUT 0 +#define GPIO_PIN_FUNC_OUTPUT 1 + struct a10_gpio_port { u32 cfg[4]; u32 dat;

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coreboot-gerrit January 2014