coreboot-gerrit January 2014

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Patch set updated for coreboot: da2661f cpu/allwinner/a10: Add functions for driving GPIO pins
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4599 -gerrit commit da2661ffbc117be887e3946767310a2db9a1a41f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 2 03:59:24 2014 -0500 cpu/allwinner/a10: Add functions for driving GPIO pins Change-Id: I9473a6e574c3af02d154a7e30245f0dc0b238300 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 1 + src/cpu/allwinner/a10/gpio.c | 98 ++++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/gpio.h | 8 ++++ 3 files changed, 107 insertions(+) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 6865529..8e743a2 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += clock.c +bootblock-y += gpio.c bootblock-y += pinmux.c bootblock-y += bootblock_media.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c diff --git a/src/cpu/allwinner/a10/gpio.c b/src/cpu/allwinner/a10/gpio.c new file mode 100644 index 0000000..295cdf2 --- /dev/null +++ b/src/cpu/allwinner/a10/gpio.c @@ -0,0 +1,98 @@ +/* + * Basic GPIO helpers for Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "gpio.h" + +#include <arch/io.h> + +static struct a10_gpio *const gpio = (void *)GPIO_BASE; + +/** + * \brief Set a single output pin + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] pin the pin number in the given port (1 -> 31) + */ +void gpio_set(u8 port, u8 pin) +{ + u32 reg32; + + if ((port > GPS)) + return; + + reg32 = gpio_read(port); + reg32 |= (1 << pin); + gpio_write(port, reg32); +} + +/** + * \brief Clear a single output pin + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] pin the pin number in the given port (1 -> 31) + */ +void gpio_clear(u8 port, u8 pin) +{ + u32 reg32; + if ((port > GPS)) + return; + + reg32 = gpio_read(port); + reg32 &= ~(1 << pin); + gpio_write(port, reg32); +} + +/** + * \brief Get the status of a single input pin + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] pin the pin number in the given port (1 -> 31) + * @return 1 if the pin is high, or 0 if the pin is low + */ +int gpio_get(u8 port, u8 pin) +{ + if ((port > GPS)) + return 0; + + return (gpio_read(port) & (1 << pin)) ? 1 : 0; +} + +/** + * \brief Write to a GPIO port + * + * Write the state of all output pins in the GPIO port. This only affects pins + * configured as output pins. + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] value 32-bit mask indicating which pins to set. For a set bit, the + * corresponding pin will be set. Otherwise, it will be cleared + */ +void gpio_write(u8 port, u32 val) +{ + if ((port > GPS)) + return; + + write32(val, &gpio->port[port].dat); +} + +/** + * \brief Write to a GPIO port + * + * Read the state of all input pins in the GPIO port. + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @return 32-bit mask indicating which pins are high. For each set bit, the + * corresponding pin is high. The value of bits corresponding to pins + * which are not configured as inputs is undefined. + */ +u32 gpio_read(u8 port) +{ + if ((port > GPS)) + return 0; + + return read32(&gpio->port[port].dat); +} diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h index e4b24ea..b20d759 100644 --- a/src/cpu/allwinner/a10/gpio.h +++ b/src/cpu/allwinner/a10/gpio.h @@ -50,6 +50,14 @@ struct a10_gpio { u32 sdr_pad_pul; } __attribute__ ((packed)); +/* gpio.c */ +void gpio_set(u8 port, u8 pin); +void gpio_clear(u8 port, u8 pin); +int gpio_get(u8 port, u8 pin); +void gpio_write(u8 port, u32 val); +u32 gpio_read(u8 port); + +/* pinmux.c */ void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func); void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func);

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Patch set updated for coreboot: aa63587 cpu/allwinner/a10: Add function for reading chip revision
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4596 -gerrit commit aa635870ae6ea7adf6f9fa5e1058999c257f653e Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 2 01:57:53 2014 -0500 cpu/allwinner/a10: Add function for reading chip revision Change-Id: Iafbd253235db3914b9382fdb41de2622ef83c6d8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/timer.c | 11 +++++++++++ src/cpu/allwinner/a10/timer.h | 9 +++++++++ 2 files changed, 20 insertions(+) diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c index 60cc60c..7d5d141 100644 --- a/src/cpu/allwinner/a10/timer.c +++ b/src/cpu/allwinner/a10/timer.c @@ -11,6 +11,7 @@ #include <delay.h> #include <timer.h> +struct a1x_timer_module *const timer_module = (void *)A1X_TIMER_BASE; struct a1x_timer *const tmr0 = &((struct a1x_timer_module *)A1X_TIMER_BASE)->timer[0]; @@ -53,3 +54,13 @@ void udelay(unsigned usec) } } + +/* + * This function has nothing to do with timers; however, the chip revision + * register is in the timer module, so keep this function here. + */ +u8 a1x_get_cpu_chip_revision(void) +{ + write32(0, &timer_module->cpu_cfg); + return (read32(&timer_module->cpu_cfg) >> 6) & 0x3; +} diff --git a/src/cpu/allwinner/a10/timer.h b/src/cpu/allwinner/a10/timer.h index 9c0c0d1..cb12753 100644 --- a/src/cpu/allwinner/a10/timer.h +++ b/src/cpu/allwinner/a10/timer.h @@ -24,6 +24,13 @@ #define TIMER_CTRL_RELOAD (1 << 1) #define TIMER_CTRL_TMR_EN (1 << 0) +/* Chip revision definitions (found in CPU_CFG register) */ +#define A1X_CHIP_REV_A 0x0 +#define A1X_CHIP_REV_C1 0x1 +#define A1X_CHIP_REV_C2 0x2 +#define A1X_CHIP_REV_B 0x3 + + /* General purpose timer */ struct a1x_timer { u32 ctrl; @@ -87,4 +94,6 @@ struct a1x_timer_module { u32 cpu_cfg; } __attribute__ ((packed)); +u8 a1x_get_cpu_chip_revision(void); + #endif /* CPU_ALLWINNER_A10_TIMER_H */

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Patch set updated for coreboot: 974e79b cpu/allwinner/a10: Import raminit code from uboot
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4597 -gerrit commit 974e79b64b05f9dffae8459455f751ae1d069bdd Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Dec 25 03:00:39 2013 -0500 cpu/allwinner/a10: Import raminit code from uboot The memory initialization code is a work in progress for uboot, so we only import the bits needed to get RAM up and running. Any refactoring is cosmetic, and any functional refactoring should be done in separate patches, and preferably, in coordination with the sunxi team. Since it's not yet determined if we should initialize memory during the bootblock or romstage, we don't add raminit to the build just yet. Change-Id: I2ec1821942c6970150a02fa3806a257da649e1c9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/dramc.h | 176 +++++++++++++++ src/cpu/allwinner/a10/raminit.c | 468 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 644 insertions(+) diff --git a/src/cpu/allwinner/a10/dramc.h b/src/cpu/allwinner/a10/dramc.h new file mode 100644 index 0000000..7d44d83 --- /dev/null +++ b/src/cpu/allwinner/a10/dramc.h @@ -0,0 +1,176 @@ +/* + * Allwinner A10 platform dram register definition. + * + * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c + * and earlier U-Boot Allwiner A10 SPL work + * + * Copyright (C) 2007-2012 Allwinner Technology Co., Ltd. + * Berg Xing <bergxing(a)allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_DRAMC_H +#define CPU_ALLWINNER_A10_DRAMC_H + +#include <types.h> + +#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) +#define DRAM_CCR_DQS_GATE (0x1 << 14) +#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) +#define DRAM_CCR_ITM_OFF (0x1 << 28) +#define DRAM_CCR_DATA_TRAINING (0x1 << 30) +#define DRAM_CCR_INIT (0x1 << 31) + +#define DRAM_MEMORY_TYPE_DDR1 1 +#define DRAM_MEMORY_TYPE_DDR2 2 +#define DRAM_MEMORY_TYPE_DDR3 3 +#define DRAM_MEMORY_TYPE_LPDDR2 4 +#define DRAM_MEMORY_TYPE_LPDDR 5 +#define DRAM_DCR_TYPE (0x1 << 0) +#define DRAM_DCR_TYPE_DDR2 0x0 +#define DRAM_DCR_TYPE_DDR3 0x1 +#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) +#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) +#define DRAM_DCR_IO_WIDTH_8BIT 0x0 +#define DRAM_DCR_IO_WIDTH_16BIT 0x1 +#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) +#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) +#define DRAM_DCR_CHIP_DENSITY_256M 0x0 +#define DRAM_DCR_CHIP_DENSITY_512M 0x1 +#define DRAM_DCR_CHIP_DENSITY_1024M 0x2 +#define DRAM_DCR_CHIP_DENSITY_2048M 0x3 +#define DRAM_DCR_CHIP_DENSITY_4096M 0x4 +#define DRAM_DCR_CHIP_DENSITY_8192M 0x5 +#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) +#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) +#define DRAM_DCR_BUS_WIDTH_32BIT 0x3 +#define DRAM_DCR_BUS_WIDTH_16BIT 0x1 +#define DRAM_DCR_BUS_WIDTH_8BIT 0x0 +#define DRAM_DCR_NR_DLLCR_32BIT 5 +#define DRAM_DCR_NR_DLLCR_16BIT 3 +#define DRAM_DCR_NR_DLLCR_8BIT 2 +#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) +#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) +#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) +#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) +#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) +#define DRAM_DCR_MODE_SEQ 0x0 +#define DRAM_DCR_MODE_INTERLEAVE 0x1 + +#define DRAM_CSR_FAILED (0x1 << 20) + +#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) +#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) +#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) +#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) +#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) +#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) +#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) +#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) +#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) +#define DRAM_MCR_RESET (0x1 << 12) +#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) +#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) +#define DRAM_MCR_DCLK_OUT (0x1 << 16) + +#define DRAM_DLLCR_NRESET (0x1 << 30) +#define DRAM_DLLCR_DISABLE (0x1 << 31) + +#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) +#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) + +#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) +#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) + +#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) +#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) +#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) +#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) +#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) +#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) +#define DRAM_MR_POWER_DOWN (0x1 << 12) + +#define DRAM_CSEL_MAGIC 0x16237495 + +struct a1x_dramc { + u32 ccr; /* 0x00 controller configuration register */ + u32 dcr; /* 0x04 dram configuration register */ + u32 iocr; /* 0x08 i/o configuration register */ + u32 csr; /* 0x0c controller status register */ + u32 drr; /* 0x10 dram refresh register */ + u32 tpr0; /* 0x14 dram timing parameters register 0 */ + u32 tpr1; /* 0x18 dram timing parameters register 1 */ + u32 tpr2; /* 0x1c dram timing parameters register 2 */ + u32 gdllcr; /* 0x20 global dll control register */ + u8 res0[0x28]; + u32 rslr0; /* 0x4c rank system latency register */ + u32 rslr1; /* 0x50 rank system latency register */ + u8 res1[0x8]; + u32 rdgr0; /* 0x5c rank dqs gating register */ + u32 rdgr1; /* 0x60 rank dqs gating register */ + u8 res2[0x34]; + u32 odtcr; /* 0x98 odt configuration register */ + u32 dtr0; /* 0x9c data training register 0 */ + u32 dtr1; /* 0xa0 data training register 1 */ + u32 dtar; /* 0xa4 data training address register */ + u32 zqcr0; /* 0xa8 zq control register 0 */ + u32 zqcr1; /* 0xac zq control register 1 */ + u32 zqsr; /* 0xb0 zq status register */ + u32 idcr; /* 0xb4 initializaton delay configure reg */ + u8 res3[0x138]; + u32 mr; /* 0x1f0 mode register */ + u32 emr; /* 0x1f4 extended mode register */ + u32 emr2; /* 0x1f8 extended mode register */ + u32 emr3; /* 0x1fc extended mode register */ + u32 dllctr; /* 0x200 dll control register */ + u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ + /* 0x208 dll control register 1(byte 1) */ + /* 0x20c dll control register 2(byte 2) */ + /* 0x210 dll control register 3(byte 3) */ + /* 0x214 dll control register 4(byte 4) */ + u32 dqtr0; /* 0x218 dq timing register */ + u32 dqtr1; /* 0x21c dq timing register */ + u32 dqtr2; /* 0x220 dq timing register */ + u32 dqtr3; /* 0x224 dq timing register */ + u32 dqstr; /* 0x228 dqs timing register */ + u32 dqsbtr; /* 0x22c dqsb timing register */ + u32 mcr; /* 0x230 mode configure register */ + u8 res[0x8]; + u32 ppwrsctl; /* 0x23c pad power save control */ + u32 apr; /* 0x240 arbiter period register */ + u32 pldtr; /* 0x244 priority level data threshold reg */ + u8 res5[0x8]; + u32 hpcr[32]; /* 0x250 host port configure register */ + u8 res6[0x10]; + u32 csel; /* 0x2e0 controller select register */ +}; + +struct dram_para { + u32 clock; + u32 type; + u32 rank_num; + u32 density; + u32 io_width; + u32 bus_width; + u32 cas; + u32 zq; + u32 odt_en; + u32 size; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr3; + u32 tpr4; + u32 tpr5; + u32 emr1; + u32 emr2; + u32 emr3; +}; + +unsigned long dramc_init(struct dram_para *para); + +#endif /* CPU_ALLWINNER_A10_DRAMC_H */ diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c new file mode 100644 index 0000000..84fe4e8 --- /dev/null +++ b/src/cpu/allwinner/a10/raminit.c @@ -0,0 +1,468 @@ +/* + * Allwinner A10 DRAM controller initialization + * + * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c + * and earlier U-Boot Allwiner A10 SPL work + * + * Copyright (C) 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net> + * Copyright (C) 2013 Luke Kenneth Casson Leighton <lkcl(a)lkcl.net> + * Copyright (C) 2007-2012 Allwinner Technology Co., Ltd. + * Berg Xing <bergxing(a)allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "clock.h" +#include "dramc.h" +#include "memmap.h" +#include "timer.h" + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> + +static struct a1x_dramc *const dram = (void *)A1X_DRAMC_BASE; + +static void mctl_ddr3_reset(void) +{ + if (a1x_get_cpu_chip_revision() != A1X_CHIP_REV_A) { + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(2); + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + } else { + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(2); + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + } +} + +static void mctl_set_drive(void) +{ + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), + DRAM_MCR_MODE_EN(0x3) | 0xffc); +} + +static void mctl_itm_disable(void) +{ + clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); +} + +static void mctl_itm_enable(void) +{ + clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); +} + +static void mctl_enable_dll0(u32 phase) +{ + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + ((phase >> 16) & 0x3f) << 6); + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE); + udelay(2); + + clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE); + udelay(22); + + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET); + udelay(22); +} + +/* + * Note: This differs from pm/standby in that it checks the bus width + */ +static void mctl_enable_dllx(u32 phase) +{ + u32 i, n, bus_width; + + bus_width = read32(&dram->dcr); + + if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) == + DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT)) + n = DRAM_DCR_NR_DLLCR_32BIT; + else + n = DRAM_DCR_NR_DLLCR_16BIT; + + for (i = 1; i < n; i++) { + clrsetbits_le32(&dram->dllcr[i], 0x4 << 14, + (phase & 0xf) << 14); + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET, + DRAM_DLLCR_DISABLE); + phase >>= 4; + } + udelay(2); + + for (i = 1; i < n; i++) + clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | + DRAM_DLLCR_DISABLE); + udelay(22); + + for (i = 1; i < n; i++) + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE, + DRAM_DLLCR_NRESET); + udelay(22); +} + +static u32 hpcr_value[32] = { + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0x0735, + 0x1035, 0x1031, 0x0731, 0x1035, + 0x1031, 0x0301, 0x0301, 0x0731 +}; + +static void mctl_configure_hostport(void) +{ + u32 i; + + for (i = 0; i < 32; i++) + write32(hpcr_value[i], &dram->hpcr[i]); +} + +static void mctl_setup_dram_clock(u32 clk) +{ + /* setup DRAM PLL */ + a1x_pll5_configure(clk / 24, 2, 2, 1); + + /* FIXME: This bit is not documented for A10, and altering it doesn't + * seem to change anything. + * + * #define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19) + * reg_val = read32(&ccm->pll5_cfg); + * reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; // PLL VCO Gain off + * write32(reg_val, &ccm->pll5_cfg); + */ + udelay(5500); + + a1x_pll5_enable_dram_clock_output(); + + /* reset GPS */ + /* FIXME: These bits are also undocumented, and seem to have no effect + * on A10. + * + * #define CCM_GPS_CTRL_RESET (0x1 << 0) + * #define CCM_GPS_CTRL_GATE (0x1 << 1) + * clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); + */ + a1x_periph_clock_enable(A1X_CLKEN_GPS); + udelay(1); + a1x_periph_clock_disable(A1X_CLKEN_GPS); + + /* setup MBUS clock */ + /* FIXME: The MBUS does not seem to be present or do anything on A10. It + * is documented in the A13 user manual, but changing settings on A10 + * has no effect. + * + * #define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0) + * #define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf) + * #define CCM_MBUS_CTRL_M_X(n) ((n) - 1) + * #define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16) + * #define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf) + * #define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0))) + * #define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24) + * #define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3) + * #define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0 + * #define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1 + * #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 + * #define CCM_MBUS_CTRL_GATE (0x1 << 31) + * reg_val = CCM_MBUS_CTRL_GATE | + * CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) | + * CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | + * CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2)); + * write32(reg_val, &ccm->mbus_clk_cfg); + */ + /* + * open DRAMC AHB & DLL register clock + * close it first + */ + a1x_periph_clock_disable(A1X_CLKEN_SDRAM); + + udelay(22); + + /* then open it */ + a1x_periph_clock_enable(A1X_CLKEN_SDRAM); + udelay(22); +} + +static int dramc_scan_readpipe(void) +{ + u32 reg32; + + /* data training trigger */ + setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); + + /* check whether data training process has completed */ + while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING) ; + + /* check data training result */ + reg32 = read32(&dram->csr); + if (reg32 & DRAM_CSR_FAILED) + return -1; + + return 0; +} + +static int dramc_scan_dll_para(void) +{ + const u32 dqs_dly[7] = { 0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc }; + const u32 clk_dly[15] = { 0x07, 0x06, 0x05, 0x04, 0x03, + 0x02, 0x01, 0x00, 0x08, 0x10, + 0x18, 0x20, 0x28, 0x30, 0x38 + }; + u32 clk_dqs_count[15]; + u32 dqs_i, clk_i, cr_i; + u32 max_val, min_val; + u32 dqs_index, clk_index; + + /* Find DQS_DLY Pass Count for every CLK_DLY */ + for (clk_i = 0; clk_i < 15; clk_i++) { + clk_dqs_count[clk_i] = 0; + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + (clk_dly[clk_i] & 0x3f) << 6); + for (dqs_i = 0; dqs_i < 7; dqs_i++) { + for (cr_i = 1; cr_i < 5; cr_i++) { + clrsetbits_le32(&dram->dllcr[cr_i], + 0x4f << 14, + (dqs_dly[clk_i] & 0x4f) << 14); + } + udelay(2); + if (dramc_scan_readpipe() == 0) + clk_dqs_count[clk_i]++; + } + } + /* Test DQS_DLY Pass Count for every CLK_DLY from up to down */ + for (dqs_i = 15; dqs_i > 0; dqs_i--) { + max_val = 15; + min_val = 15; + for (clk_i = 0; clk_i < 15; clk_i++) { + if (clk_dqs_count[clk_i] == dqs_i) { + max_val = clk_i; + if (min_val == 15) + min_val = clk_i; + } + } + if (max_val < 15) + break; + } + + /* Check if Find a CLK_DLY failed */ + if (!dqs_i) + goto fail; + + /* Find the middle index of CLK_DLY */ + clk_index = (max_val + min_val) >> 1; + if ((max_val == (15 - 1)) && (min_val > 0)) + /* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle + * value can be more close to the max_val + */ + clk_index = (15 + clk_index) >> 1; + else if ((max_val < (15 - 1)) && (min_val == 0)) + /* if CLK_DLY[0] is very good, then the middle value can be more + * close to the min_val + */ + clk_index >>= 1; + if (clk_dqs_count[clk_index] < dqs_i) + clk_index = min_val; + + /* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan + * read pipe again + */ + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + (clk_dly[clk_index] & 0x3f) << 6); + max_val = 7; + min_val = 7; + for (dqs_i = 0; dqs_i < 7; dqs_i++) { + clk_dqs_count[dqs_i] = 0; + for (cr_i = 1; cr_i < 5; cr_i++) { + clrsetbits_le32(&dram->dllcr[cr_i], + 0x4f << 14, + (dqs_dly[dqs_i] & 0x4f) << 14); + } + udelay(2); + if (dramc_scan_readpipe() == 0) { + clk_dqs_count[dqs_i] = 1; + max_val = dqs_i; + if (min_val == 7) + min_val = dqs_i; + } + } + + if (max_val < 7) { + dqs_index = (max_val + min_val) >> 1; + if ((max_val == (7 - 1)) && (min_val > 0)) + dqs_index = (7 + dqs_index) >> 1; + else if ((max_val < (7 - 1)) && (min_val == 0)) + dqs_index >>= 1; + if (!clk_dqs_count[dqs_index]) + dqs_index = min_val; + for (cr_i = 1; cr_i < 5; cr_i++) { + clrsetbits_le32(&dram->dllcr[cr_i], + 0x4f << 14, + (dqs_dly[dqs_index] & 0x4f) << 14); + } + udelay(2); + return dramc_scan_readpipe(); + } + + fail: + clrbits_le32(&dram->dllcr[0], 0x3f << 6); + for (cr_i = 1; cr_i < 5; cr_i++) + clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14); + udelay(2); + + return dramc_scan_readpipe(); +} + +static void dramc_set_autorefresh_cycle(u32 clk) +{ + u32 reg32; + u32 tmp_val; + u32 reg_dcr; + + if (clk < 600) { + reg_dcr = read32(&dram->dcr); + if ((reg_dcr & DRAM_DCR_CHIP_DENSITY_MASK) <= + DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M)) + reg32 = (131 * clk) >> 10; + else + reg32 = (336 * clk) >> 10; + + tmp_val = (7987 * clk) >> 10; + tmp_val = tmp_val * 9 - 200; + reg32 |= tmp_val << 8; + reg32 |= 0x8 << 24; + write32(reg32, &dram->drr); + } else { + write32(0x0, &dram->drr); + } +} + +unsigned long dramc_init(struct dram_para *para) +{ + u32 reg32; + int ret_val; + + /* check input dram parameter structure */ + if (!para) + return 0; + + /* setup DRAM relative clock */ + mctl_setup_dram_clock(para->clock); + + /* reset external DRAM */ + mctl_ddr3_reset(); + + mctl_set_drive(); + + /* dram clock off */ + a1x_gate_dram_clock_output(); + + /* select dram controller 1 */ + write32(DRAM_CSEL_MAGIC, &dram->csel); + + mctl_itm_disable(); + mctl_enable_dll0(para->tpr3); + + /* configure external DRAM */ + reg32 = 0x0; + if (para->type == DRAM_MEMORY_TYPE_DDR3) + reg32 |= DRAM_DCR_TYPE_DDR3; + reg32 |= DRAM_DCR_IO_WIDTH(para->io_width >> 3); + + if (para->density == 256) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M); + else if (para->density == 512) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_512M); + else if (para->density == 1024) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M); + else if (para->density == 2048) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_2048M); + else if (para->density == 4096) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_4096M); + else if (para->density == 8192) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_8192M); + else + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M); + + reg32 |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1); + reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1); + reg32 |= DRAM_DCR_CMD_RANK_ALL; + reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE); + write32(reg32, &dram->dcr); + + /* dram clock on */ + a1x_ungate_dram_clock_output(); + + udelay(1); + + while (read32(&dram->ccr) & DRAM_CCR_INIT) ; + + mctl_enable_dllx(para->tpr3); + + /* set odt impendance divide ratio */ + reg32 = ((para->zq) >> 8) & 0xfffff; + reg32 |= ((para->zq) & 0xff) << 20; + reg32 |= (para->zq) & 0xf0000000; + write32(reg32, &dram->zqcr0); + + /* set I/O configure register */ + reg32 = 0x00cc0000; + reg32 |= (para->odt_en) & 0x3; + reg32 |= ((para->odt_en) & 0x3) << 30; + write32(reg32, &dram->iocr); + + /* set refresh period */ + dramc_set_autorefresh_cycle(para->clock); + + /* set timing parameters */ + write32(para->tpr0, &dram->tpr0); + write32(para->tpr1, &dram->tpr1); + write32(para->tpr2, &dram->tpr2); + + if (para->type == DRAM_MEMORY_TYPE_DDR3) { + reg32 = DRAM_MR_BURST_LENGTH(0x0); + reg32 |= DRAM_MR_CAS_LAT(para->cas - 4); + reg32 |= DRAM_MR_WRITE_RECOVERY(0x5); + } else if (para->type == DRAM_MEMORY_TYPE_DDR2) { + reg32 = DRAM_MR_BURST_LENGTH(0x2); + reg32 |= DRAM_MR_CAS_LAT(para->cas); + reg32 |= DRAM_MR_WRITE_RECOVERY(0x5); + } + write32(reg32, &dram->mr); + + write32(para->emr1, &dram->emr); + write32(para->emr2, &dram->emr2); + write32(para->emr3, &dram->emr3); + + /* set DQS window mode */ + clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); + + /* reset external DRAM */ + setbits_le32(&dram->ccr, DRAM_CCR_INIT); + while (read32(&dram->ccr) & DRAM_CCR_INIT) ; + + /* scan read pipe value */ + mctl_itm_enable(); + if (para->tpr3 & (0x1 << 31)) { + ret_val = dramc_scan_dll_para(); + if (ret_val == 0) + para->tpr3 = + (((read32(&dram->dllcr[0]) >> 6) & 0x3f) << 16) | + (((read32(&dram->dllcr[1]) >> 14) & 0xf) << 0) | + (((read32(&dram->dllcr[2]) >> 14) & 0xf) << 4) | + (((read32(&dram->dllcr[3]) >> 14) & 0xf) << 8) | + (((read32(&dram->dllcr[4]) >> 14) & 0xf) << 12); + } else { + ret_val = dramc_scan_readpipe(); + } + + if (ret_val < 0) + return 0; + + /* configure all host port */ + mctl_configure_hostport(); + + return para->size; +}

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Patch set updated for coreboot: 4a96576 cubieboard: Turn on green LED during bootblock
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4600 -gerrit commit 4a96576fd7a5824a4870b79248a31bb1b65c3e22 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 2 04:01:52 2014 -0500 cubieboard: Turn on green LED during bootblock Change-Id: I807060bde374e4a42abe306cecf838ab157c9515 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/cubietech/cubieboard/bootblock.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index a7a55b5..90dfd0d 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -18,6 +18,10 @@ | AHB_DIV_1 \ | AXI_DIV_1 +#define GPH_STATUS_LEDS (1 << 20) | (1 << 21) +#define GPH_LED1_PIN_NO 21 +#define GPH_LED2_PIN_NO 20 + #define GPB_UART0_FUNC 2 #define GPB_UART0_PINS ((1 << 22) | (1 << 23)) @@ -56,6 +60,11 @@ static void cubieboard_setup_clocks(void) static void cubieboard_setup_gpios(void) { + /* Mux Status LED pins */ + gpio_set_multipin_func(GPH, GPH_STATUS_LEDS, GPIO_PIN_FUNC_OUTPUT); + /* Turn on green LED to let user know we're executing coreboot code */ + gpio_set(GPH, GPH_LED2_PIN_NO); + /* Mux UART pins */ gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC); }

1 0

Patch set updated for coreboot: de8c53a cpu/allwinner/a10: Refactor API for gating clocks to peripherals
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4571 -gerrit commit de8c53a3317f114e3252d9aa4574a89204ea43eb Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Dec 24 16:48:03 2013 -0500 cpu/allwinner/a10: Refactor API for gating clocks to peripherals Rather than having to track which bit in which register should be cleared or set to gate or ungate the clock to a certain peripheral, provide a simplified enum which encodes the register and bit. This change comes with a function which decodes the enum and gates/ungates the clock. This also removes the register-dependent bitmasks for APB0 and APB1 gating registers. Change-Id: Ib3ca16e54eb37eadc3ceb88f4ccc497829ac34bc Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 1 + src/cpu/allwinner/a10/clock.c | 42 +++++++++ src/cpu/allwinner/a10/clock.h | 116 ++++++++++++++++++++++--- src/mainboard/cubietech/cubieboard/bootblock.c | 7 +- 4 files changed, 148 insertions(+), 18 deletions(-) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 9f7208a..fecaf0e 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-y += clock.c bootblock-y += pinmux.c bootblock-y += bootblock_media.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c new file mode 100644 index 0000000..87a3574 --- /dev/null +++ b/src/cpu/allwinner/a10/clock.c @@ -0,0 +1,42 @@ +/* + * Helpers for clock control and gating on Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "clock.h" + +#include <arch/io.h> + +/** + * \brief Enable the clock source for the peripheral + * + * @param[in] periph peripheral and clock type to enable @see a1x_clken + */ +void a1x_periph_clock_enable(enum a1x_clken periph) +{ + void *addr; + u32 reg32; + + addr = (void *)A1X_CCM_BASE + (periph >> 5); + reg32 = read32(addr); + reg32 |= 1 << (periph & 0x1f); + write32(reg32, addr); +} + +/** + * \brief Disable the clock source for the peripheral + * + * @param[in] periph peripheral and clock type to disable @see a1x_clken + */ +void a1x_periph_clock_disable(enum a1x_clken periph) +{ + void *addr; + u32 reg32; + + addr = (void *)A1X_CCM_BASE + (periph >> 5); + reg32 = read32(addr); + reg32 &= ~(1 << (periph & 0x1f)); + write32(reg32, addr); +} diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index e028d13..b9a0771 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -43,19 +43,108 @@ #define APB1_RAT_M_MASK 0x1f << 0) #define APB1_RAT_M(n) (((n) & 0x1f) << 0) -/* APB0_GATING values */ -#define APB0_GATE_KEYPAD (1 << 10) -#define APB0_GATE_IR(x) (((1 << (x)) & 0x3) << 6) -#define APB0_GATE_PIO (1 << 5) -#define APB0_GATE_IIS (1 << 3) -#define APB0_GATE_AC97 (1 << 2) -#define APB0_GATE_CODEC (1 << 0) +/** + * \brief Clock gating definitions + * + * The definitions are specified in the form: + * 31:5 register offset from A1X_CCM_BASE for the clock register + * 4:0 bit offset for the given peripheral + * + * The names have the form [periph_type][periph_number] + * + * These definitions are meant to be used with @ref a1x_periph_clock_enable and + * @ref a1x_periph_clock_disable + */ -/* APB1_GATING values */ -#define APB1_GATE_UART(x) (((1 << (x)) & 0xff) << 16) -#define APB1_GATE_PS2(x) (((1 << (x)) & 0x3) << 6) -#define APB1_GATE_CAN (1 << 4) -#define APB1_GATE_TWI(x) (((1 << (x)) & 0x7) << 0) +enum a1x_clken { + /* AXI module clock gating */ + A1X_CLKEN_DRAM_AXI = (0x5C << 5), + /* AHB0 module clock gating */ + A1X_CLKEN_USB0 = (0x60 << 5), + A1X_CLKEN_EHCI0, + RSVD_0x60_2, + A1X_CLKEN_EHCI1, + RSVD_0x60_4, + A1X_CLKEN_SS, + A1X_CLKEN_DMA, + A1X_CLKEN_BIST, + A1X_CLKEN_MMC0, + A1X_CLKEN_MMC1, + A1X_CLKEN_MMC2, + A1X_CLKEN_MMC3, + A1X_CLKEN_NC, + A1X_CLKEN_NAND, + A1X_CLKEN_SDRAM, + RSVD_0x60_15, + A1X_CLKEN_ACE, + A1X_CLKEN_EMAC, + A1X_CLKEN_TS, + RSVD_0x60_19, + A1X_CLKEN_SPI0, + A1X_CLKEN_SPI1, + A1X_CLKEN_SPI2, + A1X_CLKEN_SPI3, + A1X_CLKEN_PATA, + /* AHB1 module clock gating */ + A1X_CLKEN_DRAM_VE = (0x64 << 5), + A1X_CLKEN_TVD, + A1X_CLKEN_TVE0, + A1X_CLKEN_TVE1, + A1X_CLKEN_LCD0, + A1X_CLKEN_LCD1, + RSVD_0x64_6, + RSVD_0x64_7, + A1X_CLKEN_CSI0, + A1X_CLKEN_CSI1, + RSVD_0x64_10, + A1X_CLKEN_HDMI, + A1X_CLKEN_DE_BE0, + A1X_CLKEN_DE_BE1, + A1X_CLKEN_DE_FE0, + A1X_CLKEN_DE_FE1, + RSVD_0x64_16, + RSVD_0x64_17, + A1X_CLKEN_MP, + RSVD_0x64_19, + A1X_CLKEN_MALI400, + /* APB0 module clock gating */ + A1X_CLKEN_CODEC = (0x68 << 5), + A1X_CLKEN_NC_APB, + A1X_CLKEN_AC97, + A1X_CLKEN_IIS, + RSVD_0x68_4, + A1X_CLKEN_PIO, + A1X_CLKEN_IR0, + A1X_CLKEN_IR1, + RSVD_0x68_8, + RSVD_0x68_9, + A1X_CLKEN_KEYPAD, + /* APB1 module clock gating */ + A1X_CLKEN_TWI0 = (0x6C << 5), + A1X_CLKEN_TWI1, + A1X_CLKEN_TWI2, + RSVD_0x6C_3, + A1X_CLKEN_CAN, + A1X_CLKEN_SCR, + A1X_CLKEN_PS20, + A1X_CLKEN_PS21, + RSVD_0x6C_8, + RSVD_0x6C_9, + RSVD_0x6C_10, + RSVD_0x6C_11, + RSVD_0x6C_12, + RSVD_0x6C_13, + RSVD_0x6C_14, + RSVD_0x6C_15, + A1X_CLKEN_UART0, + A1X_CLKEN_UART1, + A1X_CLKEN_UART2, + A1X_CLKEN_UART3, + A1X_CLKEN_UART4, + A1X_CLKEN_UART5, + A1X_CLKEN_UART6, + A1X_CLKEN_UART7, +}; struct a10_ccm { u32 pll1_cfg; /* 0x00 pll1 control */ @@ -134,4 +223,7 @@ struct a10_ccm { u32 mbus_clk_cfg; /* 0x15c */ } __attribute__ ((packed)); +void a1x_periph_clock_enable(enum a1x_clken periph); +void a1x_periph_clock_disable(enum a1x_clken periph); + #endif /* CPU_ALLWINNER_A10_CLOCK_H */ diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index a91391c..a7a55b5 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -62,12 +62,7 @@ static void cubieboard_setup_gpios(void) static void cubieboard_enable_uart(void) { - u32 reg32; - struct a10_ccm *ccm = (void *)A1X_CCM_BASE; - /* Enable clock to UART0 */ - reg32 = read32(&ccm->apb1_gate); - reg32 |= APB1_GATE_UART(0); - write32(reg32, &ccm->apb1_gate); + a1x_periph_clock_enable(A1X_CLKEN_UART0); } void bootblock_mainboard_init(void);

1 0

Patch set updated for coreboot: 3c6a108 drivers: Add support for X-Powers AXP209 PMU
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4591 -gerrit commit 3c6a1087c298c2f63ab6ab19faf35d0a3d259ac0 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Dec 30 01:21:55 2013 -0500 drivers: Add support for X-Powers AXP209 PMU Change-Id: I1de0e656a38527b172af1d0b5bcd97acbfc03bf0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/xpowers/Kconfig | 1 + src/drivers/xpowers/Makefile.inc | 1 + src/drivers/xpowers/axp209/Kconfig | 15 +++ src/drivers/xpowers/axp209/Makefile.inc | 3 + src/drivers/xpowers/axp209/axp209.c | 230 ++++++++++++++++++++++++++++++++ src/drivers/xpowers/axp209/axp209.h | 17 +++ 8 files changed, 269 insertions(+) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index b187419..8da7b05 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -37,3 +37,4 @@ source src/drivers/sil/Kconfig source src/drivers/spi/Kconfig source src/drivers/ti/Kconfig source src/drivers/trident/Kconfig +source src/drivers/xpowers/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 7b1e4ca..34ae62e 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -34,4 +34,5 @@ subdirs-y += spi subdirs-y += ti subdirs-y += ipmi subdirs-y += elog +subdirs-y += xpowers subdirs-$(CONFIG_ARCH_X86) += pc80 diff --git a/src/drivers/xpowers/Kconfig b/src/drivers/xpowers/Kconfig new file mode 100644 index 0000000..3ac2748 --- /dev/null +++ b/src/drivers/xpowers/Kconfig @@ -0,0 +1 @@ +source src/drivers/xpowers/axp209/Kconfig diff --git a/src/drivers/xpowers/Makefile.inc b/src/drivers/xpowers/Makefile.inc new file mode 100644 index 0000000..ef6dffc --- /dev/null +++ b/src/drivers/xpowers/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209 diff --git a/src/drivers/xpowers/axp209/Kconfig b/src/drivers/xpowers/axp209/Kconfig new file mode 100644 index 0000000..684873c --- /dev/null +++ b/src/drivers/xpowers/axp209/Kconfig @@ -0,0 +1,15 @@ +config DRIVER_XPOWERS_AXP209 + bool + default n + help + X-Powers AXP902 Power Management Unit + +if DRIVER_XPOWERS_AXP209 + +config DRIVER_XPOWERS_AXP209_BOOTBLOCK + bool + default n + help + Make AXP209 functionality available in he bootblock. + +endif # DRIVER_XPOWERS_AXP209 diff --git a/src/drivers/xpowers/axp209/Makefile.inc b/src/drivers/xpowers/axp209/Makefile.inc new file mode 100644 index 0000000..5ac691e --- /dev/null +++ b/src/drivers/xpowers/axp209/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-$(CONFIG_DRIVER_XPOWERS_AXP209_BOOTBLOCK) += axp209.c +romstage-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209.c +ramstage-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209.c diff --git a/src/drivers/xpowers/axp209/axp209.c b/src/drivers/xpowers/axp209/axp209.c new file mode 100644 index 0000000..68ab8a5 --- /dev/null +++ b/src/drivers/xpowers/axp209/axp209.c @@ -0,0 +1,230 @@ +/* + * Driver for X-Powers AXP 209 Power Management Unit + * + * Despite axp209_read/write only working on a byte at a time, there is no such + * limitation in the AXP209. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "axp209.h" + +#include <device/i2c.h> + +/* Hide these definitions from the rest of the source, so keep them here */ +enum registers { + REG_POWER_STATUS = 0x00, + REG_POWER_MODE = 0x01, + REG_OTG_VBUS = 0x02, + REG_CHIP_ID = 0x03, + REG_CHIP_PWROUT_CTL = 0x12, + REG_DCDC2_VOLTAGE = 0x23, + REG_DCDC2_LDO3_CTL = 0x25, + REG_DCDC3_VOLTAGE = 0x27, + REG_LDO24_VOLTAGE = 0x28, + REG_LDO3_VOLTAGE = 0x29, + REG_VBUS_IPSOUT = 0x30, + REG_PWROFF_VOLTAGE = 0x31, + REG_SHTDWN_SETTING = 0x32, +}; + +/* REG_LDO24_VOLTAGE definitions */ +#define REG_LDO24_VOLTAGE_LDO2_MASK (0xf << 4) +#define REG_LDO24_VOLTAGE_LDO2_VAL(x) ((x << 4) & REG_LDO24_VOLTAGE_LDO2_MASK) +#define REG_LDO24_VOLTAGE_LDO4_MASK (0xf << 0) +#define REG_LDO24_VOLTAGE_LDO4_VAL(x) ((x << 0) & REG_LDO24_VOLTAGE_LDO4_MASK) + +/* + * Read and write accessors. We only work on one register at a time, but there + * is no limitation on the AXP209 as to how many registers we may read or write + * in one transaction. + * These return the number of bytes read/written, or an error code. In this + * case, they return 1 on success, or an error code otherwise. + */ +static int axp209_read(u8 bus, u8 reg, u8 *val) +{ + return i2c_read(bus, AXP209_I2C_ADDR, reg, 1, val, 1); +} + +static int axp209_write(u8 bus, u8 reg, u8 val) +{ + return i2c_write(bus, AXP209_I2C_ADDR, reg, 1, &val, 1); +} + +/** + * \brief Identify and initialize an AXP209 on the I²C bus + * + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on if an AXP209 is found, or an error code otherwise. + */ +enum cb_err axp209_init(u8 bus) +{ + u8 id; + + if (axp209_read(bus, REG_CHIP_ID, &id) != 1) + return CB_ERR; + + /* From U-Boot code : Low 4 bits is chip version */ + if ((id & 0x0f) != 0x1) + return CB_ERR; + + return CB_SUCCESS; +} + +/** + * \brief Configure the output voltage of DC-DC2 converter + * + * If the requested voltage is not available, the next lowest voltage will + * be applied. + * Valid values are between 700mV and 2275mV + * + * @param[in] millivolts voltage in mV units. + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, + * CB_ERR_ARG if voltage is out of range, or an error code otherwise. + */ +enum cb_err axp209_set_dcdc2_voltage(u8 bus, u16 millivolts) +{ + u8 val; + + if (millivolts < 700 || millivolts > 2275) + return CB_ERR_ARG; + + val = (millivolts - 700) / 25; + + if (axp209_write(bus, REG_DCDC2_VOLTAGE, val) != 1) + return CB_ERR; + + return CB_SUCCESS; +} + +/** + * \brief Configure the output voltage of DC-DC3 converter + * + * If the requested voltage is not available, the next lowest voltage will + * be applied. + * Valid values are between 700mV and 3500mV + * + * @param[in] millivolts voltage in mV units. + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, + * CB_ERR_ARG if voltage is out of range, or an error code otherwise. + */ +enum cb_err axp209_set_dcdc3_voltage(u8 bus, u16 millivolts) +{ + u8 val; + + if (millivolts < 700 || millivolts > 3500) + return CB_ERR_ARG; + + val = (millivolts - 700) / 25; + + if (axp209_write(bus, REG_DCDC3_VOLTAGE, val) != 1) + return CB_ERR; + + return CB_SUCCESS; +} + +/** + * \brief Configure the output voltage of LDO2 regulator + * + * If the requested voltage is not available, the next lowest voltage will + * be applied. + * Valid values are between 700mV and 3300mV + * + * @param[in] millivolts voltage in mV units. + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, + * CB_ERR_ARG if voltage is out of range, or an error code otherwise. + */ +enum cb_err axp209_set_ldo2_voltage(u8 bus, u16 millivolts) +{ + u8 reg8, val; + + if (millivolts < 1800 || millivolts > 3300) + return CB_ERR_ARG; + + /* Try to read the register first, and stop here on error */ + if (axp209_read(bus, REG_LDO24_VOLTAGE, &reg8) != 1) + return CB_ERR; + + val = (millivolts - 1800) / 100; + reg8 &= ~REG_LDO24_VOLTAGE_LDO2_MASK; + reg8 |= REG_LDO24_VOLTAGE_LDO2_VAL(val); + + if (axp209_write(bus, REG_LDO24_VOLTAGE, reg8) != 1) + return CB_ERR; + + return CB_SUCCESS; +} + +/** + * \brief Configure the output voltage of LDO4 regulator + * + * If the requested voltage is not available, the next lowest voltage will + * be applied. + * Valid values are between 700mV and 3500mV. Datasheet lists maximum voltage at + * 2250mV, but hardware samples go as high as 3500mV. + * + * @param[in] millivolts voltage in mV units. + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, + * CB_ERR_ARG if voltage is out of range, or an error code otherwise. + */ +enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts) +{ + u8 val; + + /* Datasheet lists 2250 max, but PMU will output up to 3500mV */ + if (millivolts < 700 || millivolts > 3500) + return CB_ERR_ARG; + + val = (millivolts - 700) / 25; + + if (axp209_write(bus, REG_LDO3_VOLTAGE, val) != 1) + return CB_ERR; + + return CB_SUCCESS; +} + +/** + * \brief Configure the output voltage of DC-DC2 converter + * + * If the requested voltage is not available, the next lowest voltage will + * be applied. + * Valid values are between 1250V and 3300mV + * + * @param[in] millivolts voltage in mV units. + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, + * CB_ERR_ARG if voltage is out of range, or an error code otherwise. + */ +enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts) +{ + u8 reg8, val; + + if (millivolts < 1250 || millivolts > 3300) + return CB_ERR_ARG; + + /* Try to read the register first, and stop here on error */ + if (axp209_read(bus, REG_LDO24_VOLTAGE, &reg8) != 1) + return CB_ERR; + + if (millivolts <= 2000) + val = (millivolts - 1200) / 100; + else if (millivolts <= 2700) + val = 9 + (millivolts - 2500) / 100; + else if (millivolts <= 2800) + val = 11; + else + val = 12 + (millivolts - 3000) / 100; + + reg8 &= ~REG_LDO24_VOLTAGE_LDO4_MASK; + reg8 |= REG_LDO24_VOLTAGE_LDO4_VAL(val); + + if (axp209_write(bus, REG_LDO24_VOLTAGE, reg8) != 1) + return CB_ERR; + + return CB_SUCCESS; +} diff --git a/src/drivers/xpowers/axp209/axp209.h b/src/drivers/xpowers/axp209/axp209.h new file mode 100644 index 0000000..1d369f5 --- /dev/null +++ b/src/drivers/xpowers/axp209/axp209.h @@ -0,0 +1,17 @@ +/* + * Definitions for X-Powers AXP 209 Power Management Unit + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <types.h> + +#define AXP209_I2C_ADDR (0x68 >> 1) + +enum cb_err axp209_init(u8 bus); +enum cb_err axp209_set_dcdc2_voltage(u8 bus, u16 millivolts); +enum cb_err axp209_set_dcdc3_voltage(u8 bus, u16 millivolts); +enum cb_err axp209_set_ldo2_voltage(u8 bus, u16 millivolts); +enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts); +enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts);

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Patch set updated for coreboot: 132fe49 cpu/allwinner/a10: Add basic TWI (I²C) driver
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4588 -gerrit commit 132fe49489b589b1f81f77c583204334b5266138 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Dec 28 21:50:54 2013 -0500 cpu/allwinner/a10: Add basic TWI (I²C) driver Change-Id: I11b10301199e5ff1a45d9b7d2958cc7b6667a29c Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 1 + src/cpu/allwinner/a10/twi.c | 206 +++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/twi.h | 58 +++++++++++ 3 files changed, 265 insertions(+) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index fecaf0e..6865529 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -11,6 +11,7 @@ romstage-y += bootblock_media.c ramstage-y += uart.c ramstage-y += uart_console.c ramstage-y += timer.c +ramstage-y += twi.c ramstage-y += monotonic_timer.c ramstage-y += bootblock_media.c diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c new file mode 100644 index 0000000..692a498 --- /dev/null +++ b/src/cpu/allwinner/a10/twi.c @@ -0,0 +1,206 @@ +/* + * Setup helpers for Two Wire Interface (TWI) (I²C) Allwinner CPUs + * + * Only functionality for I²C master is provided. + * Largely based on the uboot-sunxi code. + * + * Copyright (C) 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "memmap.h" +#include "twi.h" + +#include <arch/io.h> +#include <delay.h> +#include <device/i2c.h> + +#define TWI_BASE(n) (A1X_TWI0_BASE + 0x400 * (n)) + +#define TWI_TIMEOUT (50 * 1000) + +static u8 is_busy(struct a1x_twi *twi) +{ + return (read32(&twi->stat) != TWI_STAT_IDLE); +} + +static enum cb_err wait_until_idle(struct a1x_twi *twi) +{ + u32 i = TWI_TIMEOUT; + while (i-- && is_busy((twi))) + udelay(1); + return i ? CB_SUCCESS : CB_ERR; +} + +/* FIXME: This function is basic, and unintelligent */ +static void configure_clock(struct a1x_twi *twi, u32 speed_hz) +{ + /* FIXME: We assume clock is 24MHz, which may not be the case */ + u32 apb_clk = 24000000, m, n; + + /* Pre-divide the clock by 8 */ + n = 3; + m = (apb_clk >> n) / speed_hz; + write32(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk); +} + +void a1x_twi_init(u8 bus, u32 speed_hz) +{ + u32 i = TWI_TIMEOUT; + struct a1x_twi *twi = (void *)TWI_BASE(bus); + + configure_clock(twi, speed_hz); + + /* Enable the I²C bus */ + write32(TWI_CTL_BUS_EN, &twi->ctl); + /* Issue soft reset */ + write32(1, &twi->reset); + + while (i-- && read32(&twi->reset)) + udelay(1); +} + +static void clear_interrupt_flag(struct a1x_twi *twi) +{ + write32(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl); +} + +static void i2c_send_data(struct a1x_twi *twi, u8 data) +{ + write32(data, &twi->data); + clear_interrupt_flag(twi); +} + +static enum twi_status wait_for_status(struct a1x_twi *twi) +{ + u32 i = TWI_TIMEOUT; + /* Wait until interrupt is asserted again */ + while (i-- && !(read32(&twi->ctl) & TWI_CTL_INT_FLAG)) + udelay(1); + /* A timeout here most likely indicates a bus error */ + return i ? read32(&twi->stat) : TWI_STAT_BUS_ERROR; +} + +static void i2c_send_start(struct a1x_twi *twi) +{ + u32 reg32, i; + + /* Send START condition */ + reg32 = read32(&twi->ctl); + reg32 &= ~TWI_CTL_INT_FLAG; + reg32 |= TWI_CTL_M_START; + write32(reg32, &twi->ctl); + + /* M_START is automatically cleared after condition is transmitted */ + i = TWI_TIMEOUT; + while (i-- && (read32(&twi->ctl) & TWI_CTL_M_START)) + udelay(1); +} + +static void i2c_send_stop(struct a1x_twi *twi) +{ + u32 reg32; + + /* Send STOP condition */ + reg32 = read32(&twi->ctl); + reg32 &= ~TWI_CTL_INT_FLAG; + reg32 |= TWI_CTL_M_STOP; + write32(reg32, &twi->ctl); +} + +int i2c_read(unsigned bus, unsigned chip, unsigned addr, + unsigned alen, uint8_t *buf, unsigned len) +{ + unsigned count = len; + enum twi_status expected_status; + struct a1x_twi *twi = (void *)TWI_BASE(bus); + + if (wait_until_idle(twi) != CB_SUCCESS) + return CB_ERR; + + i2c_send_start(twi); + if (wait_for_status(twi) != TWI_STAT_TX_START) + return CB_ERR; + + /* Send chip address */ + i2c_send_data(twi, chip << 1); + if (wait_for_status(twi) != TWI_STAT_TX_AW_ACK) + return CB_ERR; + + /* Send data address */ + i2c_send_data(twi, addr); + if (wait_for_status(twi) != TWI_STAT_TXD_ACK) + return CB_ERR; + + /* Send restart for read */ + i2c_send_start(twi); + if (wait_for_status(twi) != TWI_STAT_TX_RSTART) + return CB_ERR; + + /* Send chip address */ + i2c_send_data(twi, chip << 1 | 1); + if (wait_for_status(twi) != TWI_STAT_TX_AR_ACK) + return CB_ERR; + + /* Start ACK-ing received data */ + setbits_le32(&twi->ctl, TWI_CTL_A_ACK); + expected_status = TWI_STAT_RXD_ACK; + + /* Read data */ + while (count > 0) { + if (count == 1) { + /* Do not ACK the last byte */ + clrbits_le32(&twi->ctl, TWI_CTL_A_ACK); + expected_status = TWI_STAT_RXD_NAK; + } + + clear_interrupt_flag(twi); + + if (wait_for_status(twi) != expected_status) + return CB_ERR; + + *buf++ = read32(&twi->data); + count--; + } + + i2c_send_stop(twi); + + return len; +} + +int i2c_write(unsigned bus, unsigned chip, unsigned addr, + unsigned alen, const uint8_t *buf, unsigned len) +{ + unsigned count = len; + struct a1x_twi *twi = (void *)TWI_BASE(bus); + + if (wait_until_idle(twi) != CB_SUCCESS) + return CB_ERR; + + i2c_send_start(twi); + if (wait_for_status(twi) != TWI_STAT_TX_START) + return CB_ERR; + + /* Send chip address */ + i2c_send_data(twi, chip << 1); + if (wait_for_status(twi) != TWI_STAT_TX_AW_ACK) + return CB_ERR; + + /* Send data address */ + i2c_send_data(twi, addr); + if (wait_for_status(twi) != TWI_STAT_TXD_ACK) + return CB_ERR; + + /* Send data */ + while (count > 0) { + i2c_send_data(twi, *buf++); + if (wait_for_status(twi) != TWI_STAT_TXD_ACK) + return CB_ERR; + count--; + } + + i2c_send_stop(twi); + + return len; +} diff --git a/src/cpu/allwinner/a10/twi.h b/src/cpu/allwinner/a10/twi.h new file mode 100644 index 0000000..c5f2974 --- /dev/null +++ b/src/cpu/allwinner/a10/twi.h @@ -0,0 +1,58 @@ +/* + * Definitions Two Wire Interface (TWI) (I²C) Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_TWI_H +#define CPU_ALLWINNER_A10_TWI_H + +#include <types.h> + +/* TWI_CTL values */ +#define TWI_CTL_INT_EN (1 << 7) +#define TWI_CTL_BUS_EN (1 << 6) +#define TWI_CTL_M_START (1 << 5) +#define TWI_CTL_M_STOP (1 << 4) +#define TWI_CTL_INT_FLAG (1 << 3) +#define TWI_CTL_A_ACK (1 << 2) + +/* TWI_STAT values */ +enum twi_status { + TWI_STAT_BUS_ERROR = 0x00, /**< Bus error */ + TWI_STAT_TX_START = 0x08, /**< START sent */ + TWI_STAT_TX_RSTART = 0x10, /**< Repeated START sent */ + TWI_STAT_TX_AW_ACK = 0x18, /**< Sent address+read, ACK */ + TWI_STAT_TX_AW_NAK = 0x20, /**< Sent address+read, NAK */ + TWI_STAT_TXD_ACK = 0x28, /**< Sent data, got ACK */ + TWI_STAT_TXD_NAK = 0x30, /**< Sent data, no ACK */ + TWI_STAT_LOST_ARB = 0x38, /**< Lost arbitration */ + TWI_STAT_TX_AR_ACK = 0x40, /**< Sent address+write, ACK */ + TWI_STAT_TX_AR_NAK = 0x48, /**< Sent address+write, NAK */ + TWI_STAT_RXD_ACK = 0x50, /**< Got data, sent ACK */ + TWI_STAT_RXD_NAK = 0x58, /**< Got data, no ACK */ + TWI_STAT_IDLE = 0xf8, /**< Bus idle*/ +}; + +/* TWI_CLK values */ +#define TWI_CLK_M_MASK (0xf << 3) +#define TWI_CLK_M(m) (((m - 1) << 3) & TWI_CLK_M_MASK) +#define TWI_CLK_N_MASK (0x7 << 0) +#define TWI_CLK_N(n) (((n) << 3) & TWI_CLK_N_MASK) + +struct a1x_twi { + u32 addr; /**< 0x00: Slave address */ + u32 xaddr; /**< 0x04: Extended slave address */ + u32 data; /**< 0x08: Data byte */ + u32 ctl; /**< 0x0C: Control register */ + u32 stat; /**< 0x10: Status register */ + u32 clk; /**< 0x14: Clock control register */ + u32 reset; /**< 0x18: Software reset */ + u32 efr; /**< 0x1C: Enhanced Feature register */ + u32 lcr; /**< 0x20: Line control register */ +}; + +void a1x_twi_init(u8 bus, u32 speed_hz); + +#endif /* CPU_ALLWINNER_A10_TWI_H */

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Patch set updated for coreboot: 3ff01cc ibexpeak: Reduce SMI usage
by Vladimir Serbinenko 02 Jan '14

02 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4601 -gerrit commit 3ff01ccc9dd9e71cb52ac66473744ea31818b68b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Dec 30 12:48:49 2013 +0100 ibexpeak: Reduce SMI usage Remove gratuitous SMI handlers Change-Id: I3b932feb71ed53a5f2fccb92d59bb388dd6cde2f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/ibexpeak/smi.c | 12 ---- src/southbridge/intel/ibexpeak/smihandler.c | 86 +---------------------------- 2 files changed, 3 insertions(+), 95 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 2b85e2b..b07d65f 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -289,21 +289,9 @@ static void smm_relocate(void) smi_en = 0; /* reset SMI enables */ -#if 0 - smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; -#endif smi_en |= TCO_EN; smi_en |= APMC_EN; -#if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ - smi_en |= PERIODIC_EN; -#endif smi_en |= SLP_SMI_EN; -#if 0 - smi_en |= BIOS_EN; -#endif /* The following need to be on for SMIs to happen */ smi_en |= EOS | GBL_SMI_EN; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 5ee8ef9..2ae3f48 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -644,19 +644,6 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ outw(reg16, pmbase + ALT_GP_SMI_STS); } -static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & MCSMI_EN) == 0) - return; - - printk(BIOS_DEBUG, "Microcontroller SMI.\n"); -} - static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) @@ -696,73 +683,6 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & PERIODIC_EN) == 0) - return; - - printk(BIOS_DEBUG, "Periodic SMI.\n"); -} - -static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) -{ -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 2)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC */ - if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write - printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; - // if (smi1) - // southbridge_smi_command(data); - // return; - } - // Fall through to debug - } - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP -} - typedef void (*smi_handler_t)(unsigned int node, smm_state_save_area_t *state_save); @@ -778,17 +698,17 @@ static smi_handler_t southbridge_smi[32] = { southbridge_smi_pm1, // [8] PM1_STS southbridge_smi_gpe0, // [9] GPE0_STS southbridge_smi_gpi, // [10] GPI_STS - southbridge_smi_mc, // [11] MCSMI_STS + NULL, // [11] MCSMI_STS NULL, // [12] DEVMON_STS southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS + NULL, // [14] PERIODIC_STS NULL, // [15] SERIRQ_SMI_STS NULL, // [16] SMBUS_SMI_STS NULL, // [17] LEGACY_USB2_STS NULL, // [18] INTEL_USB2_STS NULL, // [19] reserved NULL, // [20] PCI_EXP_SMI_STS - southbridge_smi_monitor, // [21] MONITOR_STS + NULL, // [21] MONITOR_STS NULL, // [22] reserved NULL, // [23] reserved NULL, // [24] reserved

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New patch to review for coreboot: 8fb6a52 nehalem: Simplify smi.c by using __SIMPLE_DEVICE__
by Vladimir Serbinenko 02 Jan '14

02 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4604 -gerrit commit 8fb6a5225287dc41b0e20c7e5ccc7c22aa034ebd Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 2 10:12:21 2014 +0100 nehalem: Simplify smi.c by using __SIMPLE_DEVICE__ Change-Id: Ib5bac45ee7aa5492c10fa97cd75b828b6192250d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/ibexpeak/smi.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index b07d65f..edb35b0 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -19,6 +19,7 @@ * MA 02110-1301 USA */ +#define __SIMPLE_DEVICE__ #include <device/device.h> #include <device/pci.h> @@ -246,8 +247,8 @@ static void smm_relocate(void) printk(BIOS_DEBUG, "Initializing SMM handler..."); - pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - PMBASE) & 0xff80; + pmbase = pci_read_config32(PCI_DEV(0, 0x1f, 0), + PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); @@ -320,7 +321,7 @@ static int smm_handler_copied = 0; static void smm_install(void) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + device_t dev = PCI_DEV(0, 0, 0); u32 smm_base = 0xa0000; struct ied_header ied = { .signature = "INTEL RSVD", @@ -385,7 +386,7 @@ void smm_lock(void) * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); }

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New patch to review for coreboot: 83152a7 nehalem: Simplify acpi.c by using __SIMPLE_DEVICE__
by Vladimir Serbinenko 02 Jan '14

02 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4603 -gerrit commit 83152a7da586627ea3a84f98d63e22129c053fcd Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 2 10:10:14 2014 +0100 nehalem: Simplify acpi.c by using __SIMPLE_DEVICE__ Change-Id: I93351a2716cd58c2006400cecca1390b1704e94b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/nehalem/acpi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index df6cc1a..e175977 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -21,6 +21,8 @@ * MA 02110-1301 USA */ +#define __SIMPLE_DEVICE__ + #include <types.h> #include <string.h> #include <console/console.h> @@ -38,10 +40,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - /* Quickpath bus is not in standard coreboot device tree, - so read register directly. */ - pciexbar_reg = read32(DEFAULT_PCIEXBAR - | (QUICKPATH_BUS << 20) | 0x1050); + pciexbar_reg = + pci_read_config32 (PCI_DEV (QUICKPATH_BUS, 0, 1), 0x50); // MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) @@ -173,7 +173,7 @@ int init_igd_opregion(igd_opregion_t * opregion) /* TODO This needs to happen in S3 resume, too. * Maybe it should move to the finalize handler */ - igd = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + igd = PCI_DEV (0, 0x2, 0); pci_write_config32(igd, ASLS, (u32) opregion); reg16 = pci_read_config16(igd, SWSCI);

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coreboot-gerrit January 2014