coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

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1801 discussions

New patch to review for coreboot: 4420676 cpu/cpu.h: Allow compiling with __SIMPLE_DEVICE__
by Vladimir Serbinenko 02 Jan '14

02 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4602 -gerrit commit 4420676503d52fd3a91017a93d6211f012961ac4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 2 10:08:19 2014 +0100 cpu/cpu.h: Allow compiling with __SIMPLE_DEVICE__ Change-Id: I14a2ac47198be6359b4f10b38f1cf86c9917d67e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/include/cpu/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index bed77de..47521d4 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -16,10 +16,12 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1); #endif #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver"))) +#ifndef __SIMPLE_DEVICE__ /** start of compile time generated pci driver array */ extern struct cpu_driver cpu_drivers[]; /** end of compile time generated pci driver array */ extern struct cpu_driver ecpu_drivers[]; +#endif #endif /* !__PRE_RAM__ && !__SMM__ */ #endif /* CPU_CPU_H */

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New patch to review for coreboot: cb7d2e3 ibexpeak: Reduce SMI usage
by Vladimir Serbinenko 02 Jan '14

02 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4601 -gerrit commit cb7d2e3479c662411a17a1ebcaf96a2ceb478645 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Dec 30 12:48:49 2013 +0100 ibexpeak: Reduce SMI usage Remove gratuituois SMI handlers Change-Id: I3b932feb71ed53a5f2fccb92d59bb388dd6cde2f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/ibexpeak/smi.c | 12 ---- src/southbridge/intel/ibexpeak/smihandler.c | 86 +---------------------------- 2 files changed, 3 insertions(+), 95 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 2b85e2b..b07d65f 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -289,21 +289,9 @@ static void smm_relocate(void) smi_en = 0; /* reset SMI enables */ -#if 0 - smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; -#endif smi_en |= TCO_EN; smi_en |= APMC_EN; -#if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ - smi_en |= PERIODIC_EN; -#endif smi_en |= SLP_SMI_EN; -#if 0 - smi_en |= BIOS_EN; -#endif /* The following need to be on for SMIs to happen */ smi_en |= EOS | GBL_SMI_EN; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 5ee8ef9..2ae3f48 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -644,19 +644,6 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ outw(reg16, pmbase + ALT_GP_SMI_STS); } -static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & MCSMI_EN) == 0) - return; - - printk(BIOS_DEBUG, "Microcontroller SMI.\n"); -} - static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) @@ -696,73 +683,6 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & PERIODIC_EN) == 0) - return; - - printk(BIOS_DEBUG, "Periodic SMI.\n"); -} - -static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) -{ -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 2)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC */ - if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write - printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; - // if (smi1) - // southbridge_smi_command(data); - // return; - } - // Fall through to debug - } - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP -} - typedef void (*smi_handler_t)(unsigned int node, smm_state_save_area_t *state_save); @@ -778,17 +698,17 @@ static smi_handler_t southbridge_smi[32] = { southbridge_smi_pm1, // [8] PM1_STS southbridge_smi_gpe0, // [9] GPE0_STS southbridge_smi_gpi, // [10] GPI_STS - southbridge_smi_mc, // [11] MCSMI_STS + NULL, // [11] MCSMI_STS NULL, // [12] DEVMON_STS southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS + NULL, // [14] PERIODIC_STS NULL, // [15] SERIRQ_SMI_STS NULL, // [16] SMBUS_SMI_STS NULL, // [17] LEGACY_USB2_STS NULL, // [18] INTEL_USB2_STS NULL, // [19] reserved NULL, // [20] PCI_EXP_SMI_STS - southbridge_smi_monitor, // [21] MONITOR_STS + NULL, // [21] MONITOR_STS NULL, // [22] reserved NULL, // [23] reserved NULL, // [24] reserved

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New patch to review for coreboot: 9fb6a48 cubieboard: Turn on green LED during bootblock
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4600 -gerrit commit 9fb6a4846eb970f065a66893c119686f1cda760c Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 2 04:01:52 2014 -0500 cubieboard: Turn on green LED during bootblock Change-Id: I807060bde374e4a42abe306cecf838ab157c9515 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/cubietech/cubieboard/bootblock.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index a7a55b5..90dfd0d 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -18,6 +18,10 @@ | AHB_DIV_1 \ | AXI_DIV_1 +#define GPH_STATUS_LEDS (1 << 20) | (1 << 21) +#define GPH_LED1_PIN_NO 21 +#define GPH_LED2_PIN_NO 20 + #define GPB_UART0_FUNC 2 #define GPB_UART0_PINS ((1 << 22) | (1 << 23)) @@ -56,6 +60,11 @@ static void cubieboard_setup_clocks(void) static void cubieboard_setup_gpios(void) { + /* Mux Status LED pins */ + gpio_set_multipin_func(GPH, GPH_STATUS_LEDS, GPIO_PIN_FUNC_OUTPUT); + /* Turn on green LED to let user know we're executing coreboot code */ + gpio_set(GPH, GPH_LED2_PIN_NO); + /* Mux UART pins */ gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC); }

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New patch to review for coreboot: 51df3d2 cpu/allwinner/a10: Add functions for driving GPIO pins
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4599 -gerrit commit 51df3d29968e9a20faf0cbe1df5e23c34703aeee Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 2 03:59:24 2014 -0500 cpu/allwinner/a10: Add functions for driving GPIO pins Change-Id: I9473a6e574c3af02d154a7e30245f0dc0b238300 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 1 + src/cpu/allwinner/a10/gpio.c | 98 ++++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/gpio.h | 8 ++++ 3 files changed, 107 insertions(+) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 6865529..8e743a2 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += clock.c +bootblock-y += gpio.c bootblock-y += pinmux.c bootblock-y += bootblock_media.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c diff --git a/src/cpu/allwinner/a10/gpio.c b/src/cpu/allwinner/a10/gpio.c new file mode 100644 index 0000000..24c7f22 --- /dev/null +++ b/src/cpu/allwinner/a10/gpio.c @@ -0,0 +1,98 @@ +/* + * Basic GPIO helpers for Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "gpio.h" + +#include <arch/io.h> + +static struct a10_gpio *const gpio = (void *)GPIO_BASE; + +/** + * \brief Set a single output pin + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] pin the pin number in the given port (1 -> 31) + */ +void gpio_set(u8 port, u8 pin) +{ + u32 reg32; + + if ((port > GPS)) + return; + + reg32 = gpio_read(port); + reg32 |= (1 << pin); + gpio_write(port, reg32); +} + +/** + * \brief Clear a single output pin + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] pin the pin number in the given port (1 -> 31) + */ +void gpio_clear(u8 port, u8 pin) +{ + u32 reg32; + if ((port > GPS)) + return; + + reg32 = gpio_read(port); + reg32 &= ~(1 << pin); + gpio_write(port, reg32); +} + +/** + * \brief Get the status of a single input pin + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] pin the pin number in the given port (1 -> 31) + * @return 1 if the pin is high, or 0 if the pin is low + */ +int gpio_get(u8 port, u8 pin) +{ + if ((port > GPS)) + return 0; + + return (gpio_read(port) & (1 << pin)) ? 1 : 0; +} + +/** + * \brief Write to a GPIO port + * + * Write the state of all output pins in the GPIO port. This only affects pins + * configured as output pins. + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] value 32-bit mask indicating which pins to set. For a set bit, the + * corresponding pin will be set. Otherwise, it will be cleared + */ +void gpio_write(u8 port, u32 val) +{ + if ((port > GPS)) + return; + + write32(val, &gpio->port[port].dat); +} + +/** + * \brief Write to a GPIO port + * + * Read the state of all input pins in the GPIO port. + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @return 32-bit mask indicating which are high. For each set bit, the + * corresponding pin is high. The value of bits corresponding to pins + * which are not configured as inputs is undefined. + */ +u32 gpio_read(u8 port) +{ + if ((port > GPS)) + return 0; + + return read32(&gpio->port[port].dat); +} diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h index e4b24ea..b20d759 100644 --- a/src/cpu/allwinner/a10/gpio.h +++ b/src/cpu/allwinner/a10/gpio.h @@ -50,6 +50,14 @@ struct a10_gpio { u32 sdr_pad_pul; } __attribute__ ((packed)); +/* gpio.c */ +void gpio_set(u8 port, u8 pin); +void gpio_clear(u8 port, u8 pin); +int gpio_get(u8 port, u8 pin); +void gpio_write(u8 port, u32 val); +u32 gpio_read(u8 port); + +/* pinmux.c */ void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func); void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func);

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New patch to review for coreboot: 14a5077 cpu/allwinner/a10: Add definitions for in/output GPIO functions
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4598 -gerrit commit 14a5077baaae2f7734ce3e117457d0d07eb6a03f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 2 03:22:03 2014 -0500 cpu/allwinner/a10: Add definitions for in/output GPIO functions Change-Id: I2b857d3b4c01e39c62e54f753e400e6049f1dbc9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/gpio.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h index 709f74b..e4b24ea 100644 --- a/src/cpu/allwinner/a10/gpio.h +++ b/src/cpu/allwinner/a10/gpio.h @@ -23,6 +23,10 @@ #define GPI 8 #define GPS 9 +/* GPIO pad functions valid for all pins */ +#define GPIO_PIN_FUNC_INPUT 0 +#define GPIO_PIN_FUNC_OUTPUT 1 + struct a10_gpio_port { u32 cfg[4]; u32 dat;

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New patch to review for coreboot: 952a9d0 cpu/allwinner/a10: Import raminit code from uboot
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4597 -gerrit commit 952a9d0e5265552e8b7510b98b18b2233b0361b8 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Dec 25 03:00:39 2013 -0500 cpu/allwinner/a10: Import raminit code from uboot The memory initialization code is a work in progress for uboot, so we only import the bits needed to get RAM up and running. Any refactoring is cosmetic, and any functional refactoring should be done in separate patches, and preferably, in coordination with the sunxi team. Since it's not yet determined if we should initialize memory during the bootblock or romstage, we don't add raminit to the build just yet. Change-Id: I2ec1821942c6970150a02fa3806a257da649e1c9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/dramc.h | 176 +++++++++++++++ src/cpu/allwinner/a10/raminit.c | 468 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 644 insertions(+) diff --git a/src/cpu/allwinner/a10/dramc.h b/src/cpu/allwinner/a10/dramc.h new file mode 100644 index 0000000..7d44d83 --- /dev/null +++ b/src/cpu/allwinner/a10/dramc.h @@ -0,0 +1,176 @@ +/* + * Allwinner A10 platform dram register definition. + * + * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c + * and earlier U-Boot Allwiner A10 SPL work + * + * Copyright (C) 2007-2012 Allwinner Technology Co., Ltd. + * Berg Xing <bergxing(a)allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_DRAMC_H +#define CPU_ALLWINNER_A10_DRAMC_H + +#include <types.h> + +#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) +#define DRAM_CCR_DQS_GATE (0x1 << 14) +#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) +#define DRAM_CCR_ITM_OFF (0x1 << 28) +#define DRAM_CCR_DATA_TRAINING (0x1 << 30) +#define DRAM_CCR_INIT (0x1 << 31) + +#define DRAM_MEMORY_TYPE_DDR1 1 +#define DRAM_MEMORY_TYPE_DDR2 2 +#define DRAM_MEMORY_TYPE_DDR3 3 +#define DRAM_MEMORY_TYPE_LPDDR2 4 +#define DRAM_MEMORY_TYPE_LPDDR 5 +#define DRAM_DCR_TYPE (0x1 << 0) +#define DRAM_DCR_TYPE_DDR2 0x0 +#define DRAM_DCR_TYPE_DDR3 0x1 +#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) +#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) +#define DRAM_DCR_IO_WIDTH_8BIT 0x0 +#define DRAM_DCR_IO_WIDTH_16BIT 0x1 +#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) +#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) +#define DRAM_DCR_CHIP_DENSITY_256M 0x0 +#define DRAM_DCR_CHIP_DENSITY_512M 0x1 +#define DRAM_DCR_CHIP_DENSITY_1024M 0x2 +#define DRAM_DCR_CHIP_DENSITY_2048M 0x3 +#define DRAM_DCR_CHIP_DENSITY_4096M 0x4 +#define DRAM_DCR_CHIP_DENSITY_8192M 0x5 +#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) +#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) +#define DRAM_DCR_BUS_WIDTH_32BIT 0x3 +#define DRAM_DCR_BUS_WIDTH_16BIT 0x1 +#define DRAM_DCR_BUS_WIDTH_8BIT 0x0 +#define DRAM_DCR_NR_DLLCR_32BIT 5 +#define DRAM_DCR_NR_DLLCR_16BIT 3 +#define DRAM_DCR_NR_DLLCR_8BIT 2 +#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) +#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) +#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) +#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) +#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) +#define DRAM_DCR_MODE_SEQ 0x0 +#define DRAM_DCR_MODE_INTERLEAVE 0x1 + +#define DRAM_CSR_FAILED (0x1 << 20) + +#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) +#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) +#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) +#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) +#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) +#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) +#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) +#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) +#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) +#define DRAM_MCR_RESET (0x1 << 12) +#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) +#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) +#define DRAM_MCR_DCLK_OUT (0x1 << 16) + +#define DRAM_DLLCR_NRESET (0x1 << 30) +#define DRAM_DLLCR_DISABLE (0x1 << 31) + +#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) +#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) + +#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) +#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) + +#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) +#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) +#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) +#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) +#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) +#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) +#define DRAM_MR_POWER_DOWN (0x1 << 12) + +#define DRAM_CSEL_MAGIC 0x16237495 + +struct a1x_dramc { + u32 ccr; /* 0x00 controller configuration register */ + u32 dcr; /* 0x04 dram configuration register */ + u32 iocr; /* 0x08 i/o configuration register */ + u32 csr; /* 0x0c controller status register */ + u32 drr; /* 0x10 dram refresh register */ + u32 tpr0; /* 0x14 dram timing parameters register 0 */ + u32 tpr1; /* 0x18 dram timing parameters register 1 */ + u32 tpr2; /* 0x1c dram timing parameters register 2 */ + u32 gdllcr; /* 0x20 global dll control register */ + u8 res0[0x28]; + u32 rslr0; /* 0x4c rank system latency register */ + u32 rslr1; /* 0x50 rank system latency register */ + u8 res1[0x8]; + u32 rdgr0; /* 0x5c rank dqs gating register */ + u32 rdgr1; /* 0x60 rank dqs gating register */ + u8 res2[0x34]; + u32 odtcr; /* 0x98 odt configuration register */ + u32 dtr0; /* 0x9c data training register 0 */ + u32 dtr1; /* 0xa0 data training register 1 */ + u32 dtar; /* 0xa4 data training address register */ + u32 zqcr0; /* 0xa8 zq control register 0 */ + u32 zqcr1; /* 0xac zq control register 1 */ + u32 zqsr; /* 0xb0 zq status register */ + u32 idcr; /* 0xb4 initializaton delay configure reg */ + u8 res3[0x138]; + u32 mr; /* 0x1f0 mode register */ + u32 emr; /* 0x1f4 extended mode register */ + u32 emr2; /* 0x1f8 extended mode register */ + u32 emr3; /* 0x1fc extended mode register */ + u32 dllctr; /* 0x200 dll control register */ + u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ + /* 0x208 dll control register 1(byte 1) */ + /* 0x20c dll control register 2(byte 2) */ + /* 0x210 dll control register 3(byte 3) */ + /* 0x214 dll control register 4(byte 4) */ + u32 dqtr0; /* 0x218 dq timing register */ + u32 dqtr1; /* 0x21c dq timing register */ + u32 dqtr2; /* 0x220 dq timing register */ + u32 dqtr3; /* 0x224 dq timing register */ + u32 dqstr; /* 0x228 dqs timing register */ + u32 dqsbtr; /* 0x22c dqsb timing register */ + u32 mcr; /* 0x230 mode configure register */ + u8 res[0x8]; + u32 ppwrsctl; /* 0x23c pad power save control */ + u32 apr; /* 0x240 arbiter period register */ + u32 pldtr; /* 0x244 priority level data threshold reg */ + u8 res5[0x8]; + u32 hpcr[32]; /* 0x250 host port configure register */ + u8 res6[0x10]; + u32 csel; /* 0x2e0 controller select register */ +}; + +struct dram_para { + u32 clock; + u32 type; + u32 rank_num; + u32 density; + u32 io_width; + u32 bus_width; + u32 cas; + u32 zq; + u32 odt_en; + u32 size; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr3; + u32 tpr4; + u32 tpr5; + u32 emr1; + u32 emr2; + u32 emr3; +}; + +unsigned long dramc_init(struct dram_para *para); + +#endif /* CPU_ALLWINNER_A10_DRAMC_H */ diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c new file mode 100644 index 0000000..c428109 --- /dev/null +++ b/src/cpu/allwinner/a10/raminit.c @@ -0,0 +1,468 @@ +/* + * Allwinner A10 DRAM controller initialization + * + * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c + * and earlier U-Boot Allwiner A10 SPL work + * + * Copyright (C) 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net> + * Copyright (C) 2013 Luke Kenneth Casson Leighton <lkcl(a)lkcl.net> + * Copyright (C) 2007-2012 Allwinner Technology Co., Ltd. + * Berg Xing <bergxing(a)allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "clock.h" +#include "dramc.h" +#include "memmap.h" +#include "timer.h" + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> + +static struct a1x_dramc *const dram = (void *)A1X_DRAMC_BASE; + +static void mctl_ddr3_reset(void) +{ + if (a1x_get_cpu_chip_revision() != A1X_CHIP_REV_A) { + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(32); + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + } else { + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(32); + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + } +} + +static void mctl_set_drive(void) +{ + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), + DRAM_MCR_MODE_EN(0x3) | 0xffc); +} + +static void mctl_itm_disable(void) +{ + clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); +} + +static void mctl_itm_enable(void) +{ + clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); +} + +static void mctl_enable_dll0(u32 phase) +{ + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + ((phase >> 16) & 0x3f) << 6); + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE); + udelay(32); + + clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE); + udelay(512); + + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET); + udelay(512); +} + +/* + * Note: This differs from pm/standby in that it checks the bus width + */ +static void mctl_enable_dllx(u32 phase) +{ + u32 i, n, bus_width; + + bus_width = read32(&dram->dcr); + + if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) == + DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT)) + n = DRAM_DCR_NR_DLLCR_32BIT; + else + n = DRAM_DCR_NR_DLLCR_16BIT; + + for (i = 1; i < n; i++) { + clrsetbits_le32(&dram->dllcr[i], 0x4 << 14, + (phase & 0xf) << 14); + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET, + DRAM_DLLCR_DISABLE); + phase >>= 4; + } + udelay(32); + + for (i = 1; i < n; i++) + clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | + DRAM_DLLCR_DISABLE); + udelay(512); + + for (i = 1; i < n; i++) + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE, + DRAM_DLLCR_NRESET); + udelay(512); +} + +static u32 hpcr_value[32] = { + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0x0735, + 0x1035, 0x1031, 0x0731, 0x1035, + 0x1031, 0x0301, 0x0301, 0x0731 +}; + +static void mctl_configure_hostport(void) +{ + u32 i; + + for (i = 0; i < 32; i++) + write32(hpcr_value[i], &dram->hpcr[i]); +} + +static void mctl_setup_dram_clock(u32 clk) +{ + /* setup DRAM PLL */ + a1x_pll5_configure(clk / 24, 2, 2, 1); + + /* FIXME: This bit is not documented for A10, and altering it doesn't + * seem to change anything. + * + * #define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19) + * reg_val = read32(&ccm->pll5_cfg); + * reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; // PLL VCO Gain off + * write32(reg_val, &ccm->pll5_cfg); + */ + udelay(131000); + + a1x_pll5_enable_dram_clock_output(); + + /* reset GPS */ + /* FIXME: These bits are also undocumented, and seem to have no effect + * on A10. + * + * #define CCM_GPS_CTRL_RESET (0x1 << 0) + * #define CCM_GPS_CTRL_GATE (0x1 << 1) + * clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); + */ + a1x_periph_clock_enable(A1X_CLKEN_GPS); + udelay(4); + a1x_periph_clock_disable(A1X_CLKEN_GPS); + + /* setup MBUS clock */ + /* FIXME: The MBUS does not seem to be present or do anything on A10. It + * is documented in the A13 user manual, but changing settings on A10 + * has no effect. + * + * #define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0) + * #define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf) + * #define CCM_MBUS_CTRL_M_X(n) ((n) - 1) + * #define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16) + * #define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf) + * #define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0))) + * #define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24) + * #define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3) + * #define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0 + * #define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1 + * #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 + * #define CCM_MBUS_CTRL_GATE (0x1 << 31) + * reg_val = CCM_MBUS_CTRL_GATE | + * CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) | + * CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | + * CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2)); + * write32(reg_val, &ccm->mbus_clk_cfg); + */ + /* + * open DRAMC AHB & DLL register clock + * close it first + */ + a1x_periph_clock_disable(A1X_CLKEN_SDRAM); + + udelay(512); + + /* then open it */ + a1x_periph_clock_enable(A1X_CLKEN_SDRAM); + udelay(512); +} + +static int dramc_scan_readpipe(void) +{ + u32 reg32; + + /* data training trigger */ + setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); + + /* check whether data training process has completed */ + while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING) ; + + /* check data training result */ + reg32 = read32(&dram->csr); + if (reg32 & DRAM_CSR_FAILED) + return -1; + + return 0; +} + +static int dramc_scan_dll_para(void) +{ + const u32 dqs_dly[7] = { 0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc }; + const u32 clk_dly[15] = { 0x07, 0x06, 0x05, 0x04, 0x03, + 0x02, 0x01, 0x00, 0x08, 0x10, + 0x18, 0x20, 0x28, 0x30, 0x38 + }; + u32 clk_dqs_count[15]; + u32 dqs_i, clk_i, cr_i; + u32 max_val, min_val; + u32 dqs_index, clk_index; + + /* Find DQS_DLY Pass Count for every CLK_DLY */ + for (clk_i = 0; clk_i < 15; clk_i++) { + clk_dqs_count[clk_i] = 0; + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + (clk_dly[clk_i] & 0x3f) << 6); + for (dqs_i = 0; dqs_i < 7; dqs_i++) { + for (cr_i = 1; cr_i < 5; cr_i++) { + clrsetbits_le32(&dram->dllcr[cr_i], + 0x4f << 14, + (dqs_dly[clk_i] & 0x4f) << 14); + } + udelay(32); + if (dramc_scan_readpipe() == 0) + clk_dqs_count[clk_i]++; + } + } + /* Test DQS_DLY Pass Count for every CLK_DLY from up to down */ + for (dqs_i = 15; dqs_i > 0; dqs_i--) { + max_val = 15; + min_val = 15; + for (clk_i = 0; clk_i < 15; clk_i++) { + if (clk_dqs_count[clk_i] == dqs_i) { + max_val = clk_i; + if (min_val == 15) + min_val = clk_i; + } + } + if (max_val < 15) + break; + } + + /* Check if Find a CLK_DLY failed */ + if (!dqs_i) + goto fail; + + /* Find the middle index of CLK_DLY */ + clk_index = (max_val + min_val) >> 1; + if ((max_val == (15 - 1)) && (min_val > 0)) + /* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle + * value can be more close to the max_val + */ + clk_index = (15 + clk_index) >> 1; + else if ((max_val < (15 - 1)) && (min_val == 0)) + /* if CLK_DLY[0] is very good, then the middle value can be more + * close to the min_val + */ + clk_index >>= 1; + if (clk_dqs_count[clk_index] < dqs_i) + clk_index = min_val; + + /* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan + * read pipe again + */ + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + (clk_dly[clk_index] & 0x3f) << 6); + max_val = 7; + min_val = 7; + for (dqs_i = 0; dqs_i < 7; dqs_i++) { + clk_dqs_count[dqs_i] = 0; + for (cr_i = 1; cr_i < 5; cr_i++) { + clrsetbits_le32(&dram->dllcr[cr_i], + 0x4f << 14, + (dqs_dly[dqs_i] & 0x4f) << 14); + } + udelay(32); + if (dramc_scan_readpipe() == 0) { + clk_dqs_count[dqs_i] = 1; + max_val = dqs_i; + if (min_val == 7) + min_val = dqs_i; + } + } + + if (max_val < 7) { + dqs_index = (max_val + min_val) >> 1; + if ((max_val == (7 - 1)) && (min_val > 0)) + dqs_index = (7 + dqs_index) >> 1; + else if ((max_val < (7 - 1)) && (min_val == 0)) + dqs_index >>= 1; + if (!clk_dqs_count[dqs_index]) + dqs_index = min_val; + for (cr_i = 1; cr_i < 5; cr_i++) { + clrsetbits_le32(&dram->dllcr[cr_i], + 0x4f << 14, + (dqs_dly[dqs_index] & 0x4f) << 14); + } + udelay(32); + return dramc_scan_readpipe(); + } + + fail: + clrbits_le32(&dram->dllcr[0], 0x3f << 6); + for (cr_i = 1; cr_i < 5; cr_i++) + clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14); + udelay(32); + + return dramc_scan_readpipe(); +} + +static void dramc_set_autorefresh_cycle(u32 clk) +{ + u32 reg32; + u32 tmp_val; + u32 reg_dcr; + + if (clk < 600) { + reg_dcr = read32(&dram->dcr); + if ((reg_dcr & DRAM_DCR_CHIP_DENSITY_MASK) <= + DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M)) + reg32 = (131 * clk) >> 10; + else + reg32 = (336 * clk) >> 10; + + tmp_val = (7987 * clk) >> 10; + tmp_val = tmp_val * 9 - 200; + reg32 |= tmp_val << 8; + reg32 |= 0x8 << 24; + write32(reg32, &dram->drr); + } else { + write32(0x0, &dram->drr); + } +} + +unsigned long dramc_init(struct dram_para *para) +{ + u32 reg32; + int ret_val; + + /* check input dram parameter structure */ + if (!para) + return 0; + + /* setup DRAM relative clock */ + mctl_setup_dram_clock(para->clock); + + /* reset external DRAM */ + mctl_ddr3_reset(); + + mctl_set_drive(); + + /* dram clock off */ + a1x_gate_dram_clock_output(); + + /* select dram controller 1 */ + write32(DRAM_CSEL_MAGIC, &dram->csel); + + mctl_itm_disable(); + mctl_enable_dll0(para->tpr3); + + /* configure external DRAM */ + reg32 = 0x0; + if (para->type == DRAM_MEMORY_TYPE_DDR3) + reg32 |= DRAM_DCR_TYPE_DDR3; + reg32 |= DRAM_DCR_IO_WIDTH(para->io_width >> 3); + + if (para->density == 256) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M); + else if (para->density == 512) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_512M); + else if (para->density == 1024) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M); + else if (para->density == 2048) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_2048M); + else if (para->density == 4096) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_4096M); + else if (para->density == 8192) + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_8192M); + else + reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M); + + reg32 |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1); + reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1); + reg32 |= DRAM_DCR_CMD_RANK_ALL; + reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE); + write32(reg32, &dram->dcr); + + /* dram clock on */ + a1x_ungate_dram_clock_output(); + + udelay(2); + + while (read32(&dram->ccr) & DRAM_CCR_INIT) ; + + mctl_enable_dllx(para->tpr3); + + /* set odt impendance divide ratio */ + reg32 = ((para->zq) >> 8) & 0xfffff; + reg32 |= ((para->zq) & 0xff) << 20; + reg32 |= (para->zq) & 0xf0000000; + write32(reg32, &dram->zqcr0); + + /* set I/O configure register */ + reg32 = 0x00cc0000; + reg32 |= (para->odt_en) & 0x3; + reg32 |= ((para->odt_en) & 0x3) << 30; + write32(reg32, &dram->iocr); + + /* set refresh period */ + dramc_set_autorefresh_cycle(para->clock); + + /* set timing parameters */ + write32(para->tpr0, &dram->tpr0); + write32(para->tpr1, &dram->tpr1); + write32(para->tpr2, &dram->tpr2); + + if (para->type == DRAM_MEMORY_TYPE_DDR3) { + reg32 = DRAM_MR_BURST_LENGTH(0x0); + reg32 |= DRAM_MR_CAS_LAT(para->cas - 4); + reg32 |= DRAM_MR_WRITE_RECOVERY(0x5); + } else if (para->type == DRAM_MEMORY_TYPE_DDR2) { + reg32 = DRAM_MR_BURST_LENGTH(0x2); + reg32 |= DRAM_MR_CAS_LAT(para->cas); + reg32 |= DRAM_MR_WRITE_RECOVERY(0x5); + } + write32(reg32, &dram->mr); + + write32(para->emr1, &dram->emr); + write32(para->emr2, &dram->emr2); + write32(para->emr3, &dram->emr3); + + /* set DQS window mode */ + clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); + + /* reset external DRAM */ + setbits_le32(&dram->ccr, DRAM_CCR_INIT); + while (read32(&dram->ccr) & DRAM_CCR_INIT) ; + + /* scan read pipe value */ + mctl_itm_enable(); + if (para->tpr3 & (0x1 << 31)) { + ret_val = dramc_scan_dll_para(); + if (ret_val == 0) + para->tpr3 = + (((read32(&dram->dllcr[0]) >> 6) & 0x3f) << 16) | + (((read32(&dram->dllcr[1]) >> 14) & 0xf) << 0) | + (((read32(&dram->dllcr[2]) >> 14) & 0xf) << 4) | + (((read32(&dram->dllcr[3]) >> 14) & 0xf) << 8) | + (((read32(&dram->dllcr[4]) >> 14) & 0xf) << 12); + } else { + ret_val = dramc_scan_readpipe(); + } + + if (ret_val < 0) + return 0; + + /* configure all host port */ + mctl_configure_hostport(); + + return para->size; +}

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New patch to review for coreboot: fd3c521 cpu/allwinner/a10: Add function for reading chip revision
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4596 -gerrit commit fd3c52145b44e0da1d33137ab848d6d218b36468 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 2 01:57:53 2014 -0500 cpu/allwinner/a10: Add function for reading chip revision Change-Id: Iafbd253235db3914b9382fdb41de2622ef83c6d8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/timer.c | 11 +++++++++++ src/cpu/allwinner/a10/timer.h | 9 +++++++++ 2 files changed, 20 insertions(+) diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c index 60cc60c..7d5d141 100644 --- a/src/cpu/allwinner/a10/timer.c +++ b/src/cpu/allwinner/a10/timer.c @@ -11,6 +11,7 @@ #include <delay.h> #include <timer.h> +struct a1x_timer_module *const timer_module = (void *)A1X_TIMER_BASE; struct a1x_timer *const tmr0 = &((struct a1x_timer_module *)A1X_TIMER_BASE)->timer[0]; @@ -53,3 +54,13 @@ void udelay(unsigned usec) } } + +/* + * This function has nothing to do with timers; however, the chip revision + * register is in the timer module, so keep this function here. + */ +u8 a1x_get_cpu_chip_revision(void) +{ + write32(0, &timer_module->cpu_cfg); + return (read32(&timer_module->cpu_cfg) >> 6) & 0x3; +} diff --git a/src/cpu/allwinner/a10/timer.h b/src/cpu/allwinner/a10/timer.h index 9c0c0d1..cb12753 100644 --- a/src/cpu/allwinner/a10/timer.h +++ b/src/cpu/allwinner/a10/timer.h @@ -24,6 +24,13 @@ #define TIMER_CTRL_RELOAD (1 << 1) #define TIMER_CTRL_TMR_EN (1 << 0) +/* Chip revision definitions (found in CPU_CFG register) */ +#define A1X_CHIP_REV_A 0x0 +#define A1X_CHIP_REV_C1 0x1 +#define A1X_CHIP_REV_C2 0x2 +#define A1X_CHIP_REV_B 0x3 + + /* General purpose timer */ struct a1x_timer { u32 ctrl; @@ -87,4 +94,6 @@ struct a1x_timer_module { u32 cpu_cfg; } __attribute__ ((packed)); +u8 a1x_get_cpu_chip_revision(void); + #endif /* CPU_ALLWINNER_A10_TIMER_H */

1 0

New patch to review for coreboot: f914d34 cpu/allwinner/a10: Implement udelay using timer 0
by Alexandru Gagniuc 02 Jan '14

02 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4595 -gerrit commit f914d346da8047c96126fee1ed2e901016d8f350 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Dec 31 00:17:19 2013 -0500 cpu/allwinner/a10: Implement udelay using timer 0 Change-Id: I4825f0d57696cd28751c59ae133b7e3315fb78e5 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Kconfig | 1 + src/cpu/allwinner/a10/timer.c | 42 ++++++++++++++++++-- src/cpu/allwinner/a10/timer.h | 90 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+), 3 deletions(-) diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 3df1ceb..b782b9a 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -6,6 +6,7 @@ if CPU_ALLWINNER_A10 config CPU_SPECIFIC_OPTIONS def_bool y + select HAVE_INIT_TIMER select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select HAVE_UART_MEMORY_MAPPED diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c index e156398..60cc60c 100644 --- a/src/cpu/allwinner/a10/timer.c +++ b/src/cpu/allwinner/a10/timer.c @@ -1,19 +1,55 @@ /* - * Placeholder for code to come(needed to complete build) + * Timer control and delays for Allwinner CPUs * * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * Subject to the GNU GPL v2, or (at your option) any later version. */ +#include "timer.h" + +#include <arch/io.h> #include <delay.h> #include <timer.h> +struct a1x_timer *const tmr0 = + &((struct a1x_timer_module *)A1X_TIMER_BASE)->timer[0]; + +static inline u32 read_timer(void) +{ + return read32(&tmr0->val); +} + void init_timer(void) { - /* Stub */ + u32 reg32; + /* Load the timer rollover value */ + write32(0xffffffff, &tmr0->interval); + /* Configure the timer to run from 24MHz oscillator, no prescaler */ + reg32 = TIMER_CTRL_PRESC_DIV_EXP(0); + reg32 |= TIMER_CTRL_CLK_SRC_OSC24M; + reg32 |= TIMER_CTRL_RELOAD; + reg32 |= TIMER_CTRL_TMR_EN; + write32(reg32, &tmr0->ctrl); } void udelay(unsigned usec) { - /* Stub */ + u32 curr_tick, last_tick; + s32 ticks_left; + + last_tick = read_timer(); + /* 24 timer ticks per microsecond (24 MHz, divided by 1) */ + ticks_left = usec * 24; + + /* FIXME: Should we consider timer rollover? + * From when we start the timer, we have almost three minutes before it + * rolls over, so we should be long into having booted our payload. + */ + while (ticks_left > 0) { + curr_tick = read_timer(); + /* Timer value decreases with each tick */ + ticks_left -= last_tick - curr_tick; + last_tick = curr_tick; + } + } diff --git a/src/cpu/allwinner/a10/timer.h b/src/cpu/allwinner/a10/timer.h new file mode 100644 index 0000000..9c0c0d1 --- /dev/null +++ b/src/cpu/allwinner/a10/timer.h @@ -0,0 +1,90 @@ +/* + * Definitions for timer control on Allwinner CPUs + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_TIMER_H +#define CPU_ALLWINNER_A10_TIMER_H + +#include "memmap.h" +#include <types.h> + +/* TMRx_CTRL values */ +#define TIMER_CTRL_MODE_SINGLE (1 << 7) +#define TIMER_CTRL_PRESC_MASK (0x7 << 4) +#define TIMER_CTRL_PRESC_DIV_EXP(ep) ((ep << 4) & TIMER_CTRL_PRESC_MASK) +#define TIMER_CTRL_CLK_SRC_MASK (0x3 << 2) +#define TIMER_CTRL_CLK_SRC_LOSC (0x0 << 2) +#define TIMER_CTRL_CLK_SRC_OSC24M (0x1 << 2) +#define TIMER_CTRL_CLK_SRC_PLL6 (0x2 << 2) +#define TIMER_CTRL_RELOAD (1 << 1) +#define TIMER_CTRL_TMR_EN (1 << 0) + +/* General purpose timer */ +struct a1x_timer { + u32 ctrl; + u32 interval; + u32 val; + u8 res[4]; +} __attribute__ ((packed)); + +/* Audio video sync*/ +struct a1x_avs { + u32 ctrl; /* 0x80 */ + u32 cnt0; /* 0x84 */ + u32 cnt1; /* 0x88 */ + u32 div; /* 0x8c */ +} __attribute__ ((packed)); + +/* Watchdog */ +struct a1x_wdog { + u32 ctrl; /* 0x90 */ + u32 mode; /* 0x94 */ +} __attribute__ ((packed)); + +/* 64 bit counter */ +struct a1x_64cnt { + u32 ctrl; /* 0xa0 */ + u32 lo; /* 0xa4 */ + u32 hi; /* 0xa8 */ +} __attribute__ ((packed)); + +/* Rtc */ +struct a1x_rtc { + u32 ctrl; /* 0x100 */ + u32 yymmdd; /* 0x104 */ + u32 hhmmss; /* 0x108 */ +} __attribute__ ((packed)); + +/* Alarm */ +struct a1x_alarm { + u32 ddhhmmss; /* 0x10c */ + u32 hhmmss; /* 0x110 */ + u32 en; /* 0x114 */ + u32 irq_en; /* 0x118 */ + u32 irq_sta; /* 0x11c */ +} __attribute__ ((packed)); + +struct a1x_timer_module { + u32 irq_en; /* 0x00 */ + u32 irq_sta; /* 0x04 */ + u8 res1[8]; + struct a1x_timer timer[6]; /* We have 6 timers */ + u8 res2[16]; + struct a1x_avs avs; + struct a1x_wdog wdog; + u8 res3[8]; + struct a1x_64cnt cnt64; + u8 res4[0x58]; + struct a1x_rtc rtc; + struct a1x_alarm alarm; + u32 gp_data[4]; + u8 res5[8]; + u32 cpu_cfg; +} __attribute__ ((packed)); + +#endif /* CPU_ALLWINNER_A10_TIMER_H */

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New patch to review for coreboot: b2ca25b cpu/samsung/exynos5250/cpu.c: Remove unused variable `ret`
by Paul Menzel 01 Jan '14

01 Jan '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4594 -gerrit commit b2ca25b3780e9b312aa6cc1564d5aec7a8ca1969 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Jan 1 14:37:33 2014 +0100 cpu/samsung/exynos5250/cpu.c: Remove unused variable `ret` CC cpu/samsung/exynos5250/cpu.ramstage.o src/cpu/samsung/exynos5250/cpu.c: In function 'exynos_displayport_init': src/cpu/samsung/exynos5250/cpu.c:88:6: error: variable 'ret' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors Change-Id: I72a5a802aef0a75b0277eaac6ca6c24793812d98 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/samsung/exynos5250/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 61f937b..c663d38 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -64,7 +64,6 @@ static void set_cpu_id(void) */ static void exynos_displayport_init(device_t dev) { - int ret; struct cpu_samsung_exynos5250_config *conf = dev->chip_info; /* put these on the stack. If, at some point, we want to move * this code to a pre-ram stage, it will be much easier. @@ -117,7 +116,7 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, "Initializing Exynos VGA, base %p\n", (void *)lcdbase); - ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); + lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } static void cpu_enable(device_t dev)

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New patch to review for coreboot: 3fc8d17 cpu/allwinner/a10: Add low-level helpers for DRAM clock control
by Alexandru Gagniuc 01 Jan '14

01 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4593 -gerrit commit 3fc8d1795e63aaa551502f8e7c4e1ea61faa6b6b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Dec 31 13:20:27 2013 -0500 cpu/allwinner/a10: Add low-level helpers for DRAM clock control PLL5 is special in that it controls the DRAM clock, and requires a fine-grained low-level control which will be needed by raminit code. This change also brings functionality which will be needed by raminit. Change-Id: I25ecc91aa2154e504ceebb9003a5e5728d47f4a3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/clock.c | 81 +++++++++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/clock.h | 28 +++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c index bc78743..0fc2698 100644 --- a/src/cpu/allwinner/a10/clock.c +++ b/src/cpu/allwinner/a10/clock.c @@ -9,6 +9,8 @@ #include <arch/io.h> +static struct a10_ccm *const ccm = (void *)A1X_CCM_BASE; + /** * \brief Enable the clock source for the peripheral * @@ -40,3 +42,82 @@ void a1x_periph_clock_disable(enum a1x_clken periph) reg32 &= ~(1 << (periph & 0x1f)); write32(reg32, addr); } + +/** + * \brief Configure PLL5 factors + * + * This is a low-level accessor to configure the divisors and multipliers of + * PLL5. PLL5 uses two factors to multiply the 24MHz oscillator clock to + * generate a pre-clock. The pre-divided clock is then divided by one of two + * independent divisors, one for DRAM, and another for peripherals clocked from + * this PLL. If the PLL was previously disabled, this function will enable it. + * Other than that, this function only modifies these factors, and leaves the + * other settings unchanged. + * + * The output clocks are give by the following formulas: + * + * Pre-clock = (24 MHz * N * K) <- Must be between 240MHz and 2GHz + * DRAM clock = pre / M + * Other module = pre / P + * + * It is the caller's responsibility to make sure the pre-divided clock falls + * within the operational range of the PLL, and that the divisors and + * multipliers are within their ranges. + * + * @param[in] mul_n Multiplier N, between 0 and 32 + * @param[in] mul_k Multiplier K, between 1 and 4 + * @param[in] div_m DRAM clock divisor, between 1 and 4 + * @param[in] exp_div_p Peripheral clock divisor exponent, between 0 and 3 + * (P = 1/2/4/8, respectively) + */ +void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p) +{ + u32 reg32; + + reg32 = read32(&ccm->pll5_cfg); + reg32 &= ~(PLL5_FACTOR_M_MASK | PLL5_FACTOR_N_MASK | + PLL5_FACTOR_K_MASK | PLL5_DIV_EXP_P_MASK); + /* The M1 factor is not documented in the datasheet, and the reference + * raminit code does not use it. Whether this is a fractional divisor, + * or an additional divisor is unknown, so don't use it for now */ + reg32 &= ~PLL5_FACTOR_M1_MASK; + reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) | + PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p)); + reg32 |= PLL5_PLL_ENABLE; + write32(reg32, &ccm->pll5_cfg); +} + +/** + * \brief Enable the clock output to DRAM chips + * + * This enables the DRAM clock to be sent to DRAM chips. This should normally be + * done after PLL5 is configured and locked. Note that the clock may be gated, + * and also needs to be ungated in order to reach the DDR chips. + * Also see @ref clock_ungate_dram_clk_output + */ +void a1x_pll5_enable_dram_clock_output(void) +{ + setbits_le32(&ccm->pll5_cfg, PLL5_DDR_CLK_OUT_EN); +} + +/** + * \brief Ungate the clock to DRAM chips + * + * Although the DRAM clock output may be enabled, it is by default gated. It + * needs to be ungated before reaching DRAM. + */ +void a1x_ungate_dram_clock_output(void) +{ + setbits_le32(&ccm->dram_clk_cfg, DRAM_CTRL_DCLK_OUT); +} + +/** + * \brief Gate the clock to DRAM chips + * + * Disable the clock to DRAM without altering PLL configuration, by closing the + * DRAM clock gate. + */ +void a1x_gate_dram_clock_output(void) +{ + clrbits_le32(&ccm->dram_clk_cfg, DRAM_CTRL_DCLK_OUT); +} diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index 9656469..41400ab 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -43,6 +43,29 @@ #define APB1_RAT_M_MASK 0x1f << 0) #define APB1_RAT_M(n) (((n) & 0x1f) << 0) +/* PLL5_CFG values */ +#define PLL5_PLL_ENABLE (1 << 31) +#define PLL5_OUT_BYPASS_EN (1 << 30) +#define PLL5_DDR_CLK_OUT_EN (1 << 29) +#define PLL5_DIV_EXP_P_MASK (0x3 << 16) +#define PLL5_DIV_EXP_P(ep) ((ep << 16) & PLL5_DIV_EXP_P_MASK) +#define PLL5_DIV_P_1 (0x0 << 16) +#define PLL5_DIV_P_2 (0x1 << 16) +#define PLL5_DIV_P_4 (0x2 << 16) +#define PLL5_DIV_P_8 (0x3 << 16) +#define PLL5_FACTOR_N_MASK (0x1f << 8) +#define PLL5_FACTOR_N(n) ((n << 8) & PLL5_FACTOR_N_MASK) +#define PLL5_LDO_EN (1 << 7) +#define PLL5_FACTOR_K_MASK (0x3 << 4) +#define PLL5_FACTOR_K(k) ((((k) - 1) << 4) & PLL5_FACTOR_K_MASK) +#define PLL5_FACTOR_M1_MASK (0x3 << 2) +#define PLL5_FACTOR_M1(m1) (((m1) << 2) & PLL5_FACTOR_M1_MASK) +#define PLL5_FACTOR_M_MASK (0x3 << 0) +#define PLL5_FACTOR_M(m) ((((m) - 1) << 0) & PLL5_FACTOR_M_MASK) + +/* DRAM_CLK values*/ +#define DRAM_CTRL_DCLK_OUT (1 << 15) + /** * \brief Clock gating definitions * @@ -228,4 +251,9 @@ struct a10_ccm { void a1x_periph_clock_enable(enum a1x_clken periph); void a1x_periph_clock_disable(enum a1x_clken periph); +void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p); +void a1x_pll5_enable_dram_clock_output(void); +void a1x_ungate_dram_clock_output(void); +void a1x_gate_dram_clock_output(void); + #endif /* CPU_ALLWINNER_A10_CLOCK_H */

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coreboot-gerrit January 2014