coreboot-gerrit January 2014

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New patch to review for coreboot: bfd45fb sandy/ivy SPI: Support hardware sequencing and use with multiple chips
by Vladimir Serbinenko 04 Jan '14

04 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4613 -gerrit commit bfd45fbaf0f29516b0652ce7f8011773ca60be1a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 4 21:00:38 2014 +0100 sandy/ivy SPI: Support hardware sequencing and use with multiple chips When 2 chips are present to get to seconf one you have to use hardware sequencing. Also use it ass fallback if chip is unknown. Based on code in flashrom by Stefan Tauner and Carl-Daniel Hailfinger distributed under compatible license. Tested on Lenovo X230 which has EN25QH64 (8M) + N25Q032..3E (4M) Change-Id: I56f3cf0406b5f09fa327ed052c8e8b1df1d8a11f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/mrccache.c | 7 +- src/southbridge/intel/bd82x6x/pch.h | 8 + src/southbridge/intel/bd82x6x/spi.c | 343 ++++++++++++++++++++++++++- 3 files changed, 356 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index e19d2c5..4079b1f 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -192,7 +192,12 @@ static void update_mrc_cache(void *unused) // 1. use spi_flash_probe() to find the flash, then spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + struct spi_flash *flash = 0; + + if (!spi_is_multichip ()) + flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!flash) + flash = spi_flash_hwseq(0, 0, 1000000, SPI_MODE_3); if (!flash) { printk(BIOS_DEBUG, "Could not find SPI device\n"); return; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 90de855..6382481 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -58,6 +58,14 @@ void intel_pch_finalize_smm(void); #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) +int spi_is_multichip(void); +struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); +#endif +#endif + +#if !defined(__ASSEMBLER__) +#if !defined(__PRE_RAM__) #if !defined(__SMM__) #include "chip.h" void pch_enable(device_t dev); diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index ec5d7de..f7778e0 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -1,5 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * See file CREDITS for list of people who contributed to this * project. @@ -28,11 +30,20 @@ #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> +#include <device/pci.h> +#include <spi_flash.h> #include <spi-generic.h> +#include "pch.h" #define min(a, b) ((a)<(b)?(a):(b)) +#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ +#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) +#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ +#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) + + #ifdef __SMM__ #include <arch/pci_mmio_cfg.h> #define pci_read_config_byte(dev, reg, targ)\ @@ -115,7 +126,11 @@ typedef struct ich9_spi_regs { typedef struct ich_spi_controller { int locked; + int revision; + uint32_t flmap0; + uint32_t hsfs; + ich9_spi_regs *ich9_spi; uint8_t *opmenu; int menubytes; uint16_t *preop; @@ -356,6 +371,7 @@ void spi_init(void) pci_read_config_dword(dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); + cntlr.revision = ich_version; switch (ich_version) { case 7: { @@ -381,7 +397,11 @@ void spi_init(void) const uint16_t ich9_spibar_offset = 0x3800; ich9_spi_regs *ich9_spi = (ich9_spi_regs *)(rcrb + ich9_spibar_offset); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + uint16_t hsfs; + cntlr.ich9_spi = ich9_spi; + hsfs = readw_(&ich9_spi->hsfs); + ichspi_lock = hsfs & HSFS_FLOCKDN; + cntlr.hsfs = hsfs; cntlr.opmenu = ich9_spi->opmenu; cntlr.menubytes = sizeof(ich9_spi->opmenu); cntlr.optype = &ich9_spi->optype; @@ -392,6 +412,12 @@ void spi_init(void) cntlr.control = (uint16_t *)ich9_spi->ssfc; cntlr.bbar = &ich9_spi->bbar; cntlr.preop = &ich9_spi->preop; + + if (cntlr.hsfs & HSFS_FDV) + { + writel_ (4, &ich9_spi->fdoc); + cntlr.flmap0 = readl_(&ich9_spi->fdod); + } break; } default: @@ -591,6 +617,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) return -1; } +int spi_is_multichip (void) +{ + if (cntlr.revision != 9) + return 0; + if (!(cntlr.hsfs & HSFS_FDV)) + return 0; + return !!((cntlr.flmap0 >> 8) & 3); +} + int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, void *din, unsigned int bitsin) { @@ -743,3 +778,309 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return 0; } + +/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; + writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + timeout /= 8; /* scale timeout duration to counter */ + while ((((hsfs = readw_(cntlr.ich9_spi->hsfs)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + udelay(8); + } + writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + if (!timeout) { + uint16_t hsfc; + addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(cntlr.ich9_spi->hsfc); + printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " + "0x%08x (= 0x%08x + %d) HSFC=%x!\n", + addr, addr + len - 1, addr, len - 1, + hsfc); + return 1; + } + + if (hsfs & HSFS_FCERR) { + uint16_t hsfc; + addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(cntlr.ich9_spi->hsfc); + printk(BIOS_ERR, "Transaction error between offset 0x%08x and " + "0x%08x (= 0x%08x + %d) HSFC=%x!\n", + addr, addr + len - 1, addr, len - 1, + hsfc); + return 1; + } + return 0; +} + + +static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + u32 start, end, erase_size; + int ret; + uint16_t hsfc; + uint16_t timeout = 100 * 60; + + erase_size = flash->sector_size; + if (offset % erase_size || len % erase_size) { + printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); + return -1; + } + + flash->spi->rw = SPI_WRITE_FLAG; + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); + return ret; + } + + start = offset; + end = start + len; + + while (offset < end) { + ich_hwseq_set_addr(offset); + + offset += erase_size; + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + hsfc = readw_(cntlr.ich9_spi->hsfc); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + writew_(hsfc, &cntlr.ich9_spi->hsfc); + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + { + printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); + ret = -1; + goto out; + } + } + + printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); + +out: + spi_release_bus(flash->spi); + return ret; +} + +static void ich_read_data(uint8_t *data, int len) +{ + int i; + uint32_t temp32 = 0; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = readl_(cntlr.data + i); + + data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; + } +} + +static int ich_hwseq_read(struct spi_flash *flash, + u32 addr, size_t len, void *buf) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr + len > flash->size) { + printk (BIOS_ERR, "Attempt to read %x-%x which is out of chip\n", + addr, addr+len); + return -1; + } + + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + while (len > 0) { + block_len = min(len, cntlr.databytes); + ich_hwseq_set_addr(addr); + hsfc = readw_(cntlr.ich9_spi->hsfc); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + writew_(hsfc, &cntlr.ich9_spi->hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +/* Fill len bytes from the data array into the fdata/spid registers. + * + * Note that using len > flash->pgm->spi.max_data_write will trash the registers + * following the data registers. + */ +static void ich_fill_data(const uint8_t *data, int len) +{ + uint32_t temp32 = 0; + int i; + + if (len <= 0) + return; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = 0; + + temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + + if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ + writel_(temp32, cntlr.data + (i - (i % 4))); + } + i--; + if ((i % 4) != 3) /* Write remaining data to regs. */ + writel_(temp32, cntlr.data + (i - (i % 4))); +} + +static int ich_hwseq_write(struct spi_flash *flash, + u32 addr, size_t len, const void *buf) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + uint32_t start = addr; + + if (addr + len > flash->size) { + printk (BIOS_ERR, "Attempt to write %x-%x which is out of chip\n", + addr, addr+len); + return -1; + } + + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, cntlr.databytes); + ich_fill_data(buf, block_len); + hsfc = readw_(cntlr.ich9_spi->hsfc); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + writew_(hsfc, &cntlr.ich9_spi->hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + { + printk (BIOS_ERR, "SF: write failure at %x\n", + addr); + return -1; + } + addr += block_len; + buf += block_len; + len -= block_len; + } + printk(BIOS_DEBUG, "SF: Successfully written %zu bytes @ %#x\n", addr - start, start); + return 0; +} + + +struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + struct spi_flash *flash = NULL; + int ret; + + if (cntlr.revision != 9) { + printk(BIOS_WARNING, "SF: Unsupported revision %x\n", + cntlr.revision); + return NULL; + } + + flash = malloc(sizeof(*flash)); + if (!flash) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + printk(BIOS_WARNING, "SF: Failed to set up slave\n"); + free (flash); + return NULL; + } + + spi->rw = SPI_READ_FLAG; + ret = spi_claim_bus(spi); + if (ret) { + printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret); + free (flash); + return NULL; + } + + flash->spi = spi; + flash->name = "Opaque HW-sequencing"; + + flash->write = ich_hwseq_write; + flash->erase = ich_hwseq_erase; + flash->read = ich_hwseq_read; + switch ((cntlr.hsfs >> 3) & 3) + { + case 0: + flash->sector_size = 256; + break; + case 1: + flash->sector_size = 4096; + break; + case 2: + flash->sector_size = 8192; + break; + case 3: + flash->sector_size = 65536; + break; + } + + uint32_t flcomp; + + writel_ (0x1000, &cntlr.ich9_spi->fdoc); + flcomp = readl_(&cntlr.ich9_spi->fdod); + + flash->size = 1 << (19 + (flcomp & 7)); + + if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3)) + flash->size += 1 << (19 + ((flcomp >> 3) & 7)); + printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); + +#if CONFIG_SMM_TSEG && defined(__SMM__) + /* Ensure flash handlers are valid for TSEG */ + tseg_relocate((void **)&flash->read); + tseg_relocate((void **)&flash->write); + tseg_relocate((void **)&flash->erase); + tseg_relocate((void **)&flash->name); +#endif + + printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n", + flash->name, flash->sector_size, flash->size); + + spi_release_bus(spi); + + return flash; +}

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New patch to review for coreboot: 8343707 MRC cache: determine flash size on runtime
by Vladimir Serbinenko 04 Jan '14

04 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4612 -gerrit commit 834370777e7f37d1ced043097f5956bf598a410a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 4 20:58:55 2014 +0100 MRC cache: determine flash size on runtime It should be possible to put coreboot compiled for smaller chip by putting it at the end of bigger chip. We already have chip size in flash->size. Use it. Tested on Lenovo X230. Change-Id: If8ff03ed72671a9f2745ed4e759a04e83aa7cc37 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/haswell/mrccache.c | 8 ++++---- src/northbridge/intel/sandybridge/mrccache.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index f60d0f7..88dbf7f 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -34,8 +34,8 @@ #endif /* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_ROM_SIZE); +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + return ((u32)p + flash->size); } static struct mrc_data_container *next_mrc_block( @@ -212,7 +212,7 @@ static void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -220,7 +220,7 @@ static void update_mrc_cache(void *unused) // 4. write mrc data with flash->write() printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); } diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index e19d2c5..b8120a8 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -34,8 +34,8 @@ #endif /* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_ROM_SIZE); +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + return ((u32)p + flash->size); } static struct mrc_data_container *next_mrc_block( @@ -212,7 +212,7 @@ static void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -220,7 +220,7 @@ static void update_mrc_cache(void *unused) // 4. write mrc data with flash->write() printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); }

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New patch to review for coreboot: 627747f util/cbmem/Makfile: Add rule `junit.xml` for Jenkins
by Paul Menzel 04 Jan '14

04 Jan '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4611 -gerrit commit 627747f7217b78dba5ad101c48c4d234cf21a2b4 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jan 4 12:19:18 2014 +0100 util/cbmem/Makfile: Add rule `junit.xml` for Jenkins The rule has the target `junit.xml` and runs `make clean` and `make` and logs the result in the file `junit.xml` suitable for consumption by Jenkins. Change-Id: I42a31f6c7a45fa9c3773969d78f745fcc4e09dbd Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/cbmem/Makefile | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile index 51ee927..fe9e923 100644 --- a/util/cbmem/Makefile +++ b/util/cbmem/Makefile @@ -42,3 +42,21 @@ distclean: clean .PHONY: all clean distclean -include .dependencies + +junit.xml: + echo '<?xml version="1.0" encoding="utf-8"?><testsuite>' > $@.tmp + $(MAKE) clean; \ + echo "<testcase classname='cbmem' name='cbmem'>" >> $@.tmp; \ + $(MAKE) >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ + if [ $$type = "failure" ]; then \ + echo "<failure type='buildFailed'>" >> $@.tmp; \ + else \ + echo "<$$type>" >> $@.tmp; \ + fi; \ + echo '<![CDATA[' >> $@.tmp; \ + cat $@.tmp.2 >> $@.tmp; \ + echo "]]></$$type>" >>$@.tmp; \ + rm -f $@.tmp.2; \ + echo "</testcase>" >> $@.tmp; \ + echo "</testsuite>" >> $@.tmp + mv $@.tmp $@

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Patch merged into coreboot/master: e74911c X201: Fix native video init
by gerrit＠coreboot.org 04 Jan '14

04 Jan '14

the following patch was just integrated into master: commit e74911cff23593234ed6e0782d55c1c73832a0e9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Jan 3 04:27:39 2014 +0100 X201: Fix native video init Due to recent restructuring X201 native video init has disappeared from config options. Put it back and fix compilation with it. Change-Id: I6d9ba5da196c093abd2df89a6fe5efefece1fb3c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4606 for details. -gerrit

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Patch set updated for coreboot: e74911c X201: Fix native video init
by Stefan Reinauer 04 Jan '14

04 Jan '14

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4606 -gerrit commit e74911cff23593234ed6e0782d55c1c73832a0e9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Jan 3 04:27:39 2014 +0100 X201: Fix native video init Due to recent restructuring X201 native video init has disappeared from config options. Put it back and fix compilation with it. Change-Id: I6d9ba5da196c093abd2df89a6fe5efefece1fb3c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Kconfig | 1 + src/northbridge/intel/nehalem/gma.c | 16 +++------------- 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 1204e23..a2d66b3 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select EARLY_CBMEM_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 31068d1..c7a0e9b 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -548,10 +548,12 @@ static void gma_pm_init_pre_vbios(struct device *dev) #include <pc80/vga.h> #include <pc80/vga_io.h> +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT static void fake_vbios(void) { #include "fake_vbios.c" } +#endif static void gma_pm_init_post_vbios(struct device *dev) { @@ -635,8 +637,8 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); #else printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); -#endif fake_vbios(); +#endif /* Linux relies on VBT for panel info. */ if (read16(0xc0000) != 0xaa55) { @@ -670,18 +672,6 @@ static void gma_func0_init(struct device *dev) /* Post VBIOS init */ gma_pm_init_post_vbios(dev); - -#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - /* This should probably run before post VBIOS init. */ - u32 iobase, mmiobase, physbase, graphics_base; - iobase = dev->resource_list[2].base; - mmiobase = dev->resource_list[0].base; - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - graphics_base = dev->resource_list[1].base; - - int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); - i915lightup(physbase, iobase, mmiobase, graphics_base); -#endif } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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Patch merged into coreboot/master: 275976b board-status: fix weekly format
by gerrit＠coreboot.org 04 Jan '14

04 Jan '14

the following patch was just integrated into master: commit 275976b8e5ec0b6105e2ca44512af30271a05436 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jan 2 09:19:21 2014 +0100 board-status: fix weekly format The last few days of the year might belong to the first week of the new year in the ISO week numbering scheme. GNU date accounts for that with different-than-usual notation. Change-Id: I8047c197971077a845d6c1fdc9da6eb9f3741539 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/4610 for details. -gerrit

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Patch merged into coreboot/master: dbcbae8 device/Kconfig: Add third person singular s to lacks
by gerrit＠coreboot.org 04 Jan '14

04 Jan '14

the following patch was just integrated into master: commit dbcbae8aa22ae70f4cb1da8f0e56a8d1aa77fed9 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jan 3 09:45:57 2014 +0100 device/Kconfig: Add third person singular s to lacks Change-Id: I74be0dbbf8d99f58ac28bfac281ccd27d1500078 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/4608 for details. -gerrit

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New patch to review for coreboot: 275976b board-status: fix weekly format
by Patrick Georgi 03 Jan '14

03 Jan '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4610 -gerrit commit 275976b8e5ec0b6105e2ca44512af30271a05436 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jan 2 09:19:21 2014 +0100 board-status: fix weekly format The last few days of the year might belong to the first week of the new year in the ISO week numbering scheme. GNU date accounts for that with different-than-usual notation. Change-Id: I8047c197971077a845d6c1fdc9da6eb9f3741539 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/board_status/to-wiki/bucketize.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/to-wiki/bucketize.sh b/util/board_status/to-wiki/bucketize.sh index 19a7c77..a0d2e95 100755 --- a/util/board_status/to-wiki/bucketize.sh +++ b/util/board_status/to-wiki/bucketize.sh @@ -4,7 +4,7 @@ # into buckets of the given granularity weekly() { - date --date="$1" +%YW%V + date --date="$1" +%GW%V } monthly() {

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Patch merged into coreboot/master: e3ab008 asrock/imb-a180: Configure the 6 COM ports and the keyboard
by gerrit＠coreboot.org 03 Jan '14

03 Jan '14

the following patch was just integrated into master: commit e3ab008ccaec6119cfd23679f6495935c8aecc61 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Dec 26 08:24:16 2013 -0700 asrock/imb-a180: Configure the 6 COM ports and the keyboard Change-Id: I66d0715f3be201f8068acd7097e2be49185bee00 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/4574 for details. -gerrit

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Patch merged into coreboot/master: 5c32e7e superio: Uncomment the w83627uhg UART clock source initialization
by gerrit＠coreboot.org 03 Jan '14

03 Jan '14

the following patch was just integrated into master: commit 5c32e7e548af9443fbfce33ae8623ea252dfd291 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Dec 26 08:17:16 2013 -0700 superio: Uncomment the w83627uhg UART clock source initialization The asrock/imb-a180 mainboard is the first mainboard to use this w83627uhg/nct6627UD sio. The default h/w clock setting is 0. Adding the SIO in the mainboard Kconfig made the builder complain that the set_uart_clock_source() wasn't being used. So the calls to that function were uncommented. Change-Id: Iedba035237c5c0fa230b02ff4799bb8c1b7bbd4a Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/4573 for details. -gerrit

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coreboot-gerrit January 2014