New patch to review for coreboot: db35aa6 sandybridge/igd: Add brightness register descriptions
by Vladimir Serbinenko 05 Jan '14
by Vladimir Serbinenko 05 Jan '14
05 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4618
-gerrit
commit db35aa6dfdc55e30fc4b93264d0b24f0869a5c5f
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Jan 5 06:52:11 2014 +0100
sandybridge/igd: Add brightness register descriptions
Needed for brightness control for Lenovo X230
Change-Id: Ib6d127d2e050671dd402c31af06ff4726f65156c
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/northbridge/intel/sandybridge/acpi/igd.asl | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl
index a6804ad..7d3d4db 100644
--- a/src/northbridge/intel/sandybridge/acpi/igd.asl
+++ b/src/northbridge/intel/sandybridge/acpi/igd.asl
@@ -23,6 +23,23 @@ Device (GFX0)
{
Name (_ADR, 0x00020000)
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ BAR0, 64
+ }
+
+ OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x48254),
+ BCLV, 16,
+ Offset (0xc8250),
+ CR1, 32,
+ CR2, 32
+ }
+
/* Display Output Switching */
Method (_DOS, 1)
{
1
0
New patch to review for coreboot: 1e9e513 acpi/ec: Add missing delay
by Vladimir Serbinenko 05 Jan '14
by Vladimir Serbinenko 05 Jan '14
05 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4617
-gerrit
commit 1e9e51338c2285273a6cc67fa4976dd6d849fcb6
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Jan 5 06:50:10 2014 +0100
acpi/ec: Add missing delay
Without this delay on fast systems like X230 the port is read before it's
updated.
Change-Id: I3e01fc348cc5170cec108a05095ba301055ed6b0
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/ec/acpi/ec.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
index ab287d6..84e2730 100644
--- a/src/ec/acpi/ec.c
+++ b/src/ec/acpi/ec.c
@@ -104,6 +104,8 @@ u8 recv_ec_data(void)
// return -1;
}
+ udelay(10);
+
data = inb(ec_data_reg);
printk(BIOS_SPEW, "recv_ec_data: 0x%02x\n", data);
1
0
05 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4616
-gerrit
commit 065a825d189a61643e08bcf91bca042eb2156e00
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Jan 5 06:46:19 2014 +0100
Eon: Add EN25Q64
chip found in X230 if not using hardware sequencing.
Change-Id: I6ded10d35bfdbbe3d54c4170dd7846c7833f5ff7
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/drivers/spi/eon.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c
index 21103ae..5a74b84 100644
--- a/src/drivers/spi/eon.c
+++ b/src/drivers/spi/eon.c
@@ -21,6 +21,7 @@
#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */
#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */
+#define EON_ID_EN25Q64 0x17
#define EON_ID_EN25Q128 0x18
struct eon_spi_flash_params {
@@ -52,6 +53,14 @@ static const struct eon_spi_flash_params eon_spi_flash_table[] = {
.nr_sectors = 4096,
.name = "EN25Q128",
},
+ {
+ .idcode1 = EON_ID_EN25Q64,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_sectors = 2048,
+ .name = "EN25Q64",
+ },
};
static int eon_write(struct spi_flash *flash,
1
0
New patch to review for coreboot: e013fb8 ROMSIZE: Add option for 12M chips.
by Vladimir Serbinenko 05 Jan '14
by Vladimir Serbinenko 05 Jan '14
05 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4615
-gerrit
commit e013fb857744f3e2c58b88635c2bbbbe05acbc1e
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Jan 5 06:40:36 2014 +0100
ROMSIZE: Add option for 12M chips.
On X230 2 real chips (8 + 4) are merged into one virtual 12M chip.
Change-Id: I04e676e4a0a5b074d8a45dbfa8a595629fd1b66d
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/Kconfig | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index fc38994..6da958f 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -225,6 +225,8 @@ config BOARD_ROMSIZE_KB_4096
bool
config BOARD_ROMSIZE_KB_8192
bool
+config BOARD_ROMSIZE_KB_12288
+ bool
config BOARD_ROMSIZE_KB_16384
bool
@@ -239,6 +241,7 @@ choice
default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
+ default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288
default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
help
Select the size of the ROM chip you intend to flash coreboot on.
@@ -286,6 +289,11 @@ config COREBOOT_ROMSIZE_KB_8192
help
Choose this option if you have a 8192 KB (8 MB) ROM chip.
+config COREBOOT_ROMSIZE_KB_12288
+ bool "12288 KB (12 MB)"
+ help
+ Choose this option if you have a 12288 KB (12 MB) ROM chip.
+
config COREBOOT_ROMSIZE_KB_16384
bool "16384 KB (16 MB)"
help
@@ -304,6 +312,7 @@ config COREBOOT_ROMSIZE_KB
default 2048 if COREBOOT_ROMSIZE_KB_2048
default 4096 if COREBOOT_ROMSIZE_KB_4096
default 8192 if COREBOOT_ROMSIZE_KB_8192
+ default 12288 if COREBOOT_ROMSIZE_KB_12288
default 16384 if COREBOOT_ROMSIZE_KB_16384
# Map the config names to a hex value (bytes).
@@ -317,6 +326,7 @@ config ROM_SIZE
default 0x200000 if COREBOOT_ROMSIZE_KB_2048
default 0x400000 if COREBOOT_ROMSIZE_KB_4096
default 0x800000 if COREBOOT_ROMSIZE_KB_8192
+ default 0xc00000 if COREBOOT_ROMSIZE_KB_12288
default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
config ENABLE_POWER_BUTTON
1
0
05 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4614
-gerrit
commit 1924e092eecd6645ba3b2ce61a1ed7f163544240
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Jan 5 00:51:12 2014 +0100
X230: current tree as-is.
Known issues:
- No keyboard backlight (thinklight works)
- No S3
- EHCI output sometimes get "stuck" until key is pressed after sysagent execution.
- no S3
- MRC fails if MRC cache is supplied. For now MRC cache is disabled.
- MRC sometimes hangs with message:
System Agent: Initializing PCH
{433e0f9f-05ae-410a-a0c3-bf298ecb2
So a watchdog is reenabled to reboot if this happens
Not tested:
- ultranav
- fingerprint
- dock
Change-Id: Ida1374b8c7f99da7d2415b33c33ccc2c270a2282
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/arch/x86/boot/smbios.c | 7 +-
src/drivers/spi/eon.c | 9 +
src/ec/acpi/ec.c | 2 +
src/mainboard/lenovo/Kconfig | 10 +
src/mainboard/lenovo/x201/Makefile.inc | 1 +
src/mainboard/lenovo/x201/dsdt.asl.orig | 94 ++++++
src/mainboard/lenovo/x201/smihandler.c.orig | 210 +++++++++++++
src/mainboard/lenovo/x201/smihandler.c.rej | 15 +
src/mainboard/lenovo/x230/Kconfig | 70 +++++
src/mainboard/lenovo/x230/Makefile.inc | 20 ++
src/mainboard/lenovo/x230/acpi/ec.asl | 26 ++
src/mainboard/lenovo/x230/acpi/mainboard.asl | 0
src/mainboard/lenovo/x230/acpi/platform.asl | 74 +++++
.../lenovo/x230/acpi/sandybridge_pci_irqs.asl | 65 ++++
src/mainboard/lenovo/x230/acpi/superio.asl | 1 +
src/mainboard/lenovo/x230/acpi/video.asl | 115 +++++++
src/mainboard/lenovo/x230/acpi_tables.c | 271 ++++++++++++++++
src/mainboard/lenovo/x230/cmos.layout | 141 +++++++++
src/mainboard/lenovo/x230/devicetree.cb | 140 +++++++++
src/mainboard/lenovo/x230/dsdt.asl | 59 ++++
src/mainboard/lenovo/x230/ec.c | 29 ++
src/mainboard/lenovo/x230/ec.h | 31 ++
src/mainboard/lenovo/x230/fadt.c | 159 ++++++++++
src/mainboard/lenovo/x230/gpio.h | 304 ++++++++++++++++++
src/mainboard/lenovo/x230/hda_verb.h | 266 ++++++++++++++++
src/mainboard/lenovo/x230/mainboard.c | 186 +++++++++++
src/mainboard/lenovo/x230/onboard.h | 36 +++
src/mainboard/lenovo/x230/romstage.c | 324 +++++++++++++++++++
src/mainboard/lenovo/x230/smi.h | 0
src/mainboard/lenovo/x230/smihandler.c | 174 +++++++++++
src/mainboard/lenovo/x230/thermal.h | 31 ++
src/northbridge/intel/sandybridge/acpi/igd.asl | 17 +
src/northbridge/intel/sandybridge/mrccache.c | 16 +-
src/northbridge/intel/sandybridge/raminit.c | 8 +-
src/southbridge/intel/bd82x6x/pch.h | 8 +
src/southbridge/intel/bd82x6x/spi.c | 347 ++++++++++++++++++++-
src/southbridge/intel/ibexpeak/pch.h | 8 +
src/southbridge/intel/ibexpeak/spi.c | 347 ++++++++++++++++++++-
38 files changed, 3607 insertions(+), 14 deletions(-)
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index 65bf538..25bdb37 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -130,12 +130,15 @@ static int smbios_write_type0(unsigned long *current, int handle)
t->vendor = smbios_add_string(t->eos, "coreboot");
#if !CONFIG_CHROMEOS
+#ifndef CONFIG_VENDOR_VERSION
+#define CONFIG_VENDOR_VERSION ""
+#endif
t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
if (strlen(CONFIG_LOCALVERSION))
- t->bios_version = smbios_add_string(t->eos, CONFIG_LOCALVERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION CONFIG_LOCALVERSION);
else
- t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION COREBOOT_VERSION);
#else
#define SPACES \
" "
diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c
index 21103ae..5a74b84 100644
--- a/src/drivers/spi/eon.c
+++ b/src/drivers/spi/eon.c
@@ -21,6 +21,7 @@
#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */
#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */
+#define EON_ID_EN25Q64 0x17
#define EON_ID_EN25Q128 0x18
struct eon_spi_flash_params {
@@ -52,6 +53,14 @@ static const struct eon_spi_flash_params eon_spi_flash_table[] = {
.nr_sectors = 4096,
.name = "EN25Q128",
},
+ {
+ .idcode1 = EON_ID_EN25Q64,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_sectors = 2048,
+ .name = "EN25Q64",
+ },
};
static int eon_write(struct spi_flash *flash,
diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
index ab287d6..3b984c4 100644
--- a/src/ec/acpi/ec.c
+++ b/src/ec/acpi/ec.c
@@ -104,6 +104,8 @@ u8 recv_ec_data(void)
// return -1;
}
+ udelay(10);
+
data = inb(ec_data_reg);
printk(BIOS_SPEW, "recv_ec_data: 0x%02x\n", data);
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index de9d56f..21413fc 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -17,6 +17,11 @@ config BOARD_LENOVO_X201
help
Lenovo X201 laptop. Consult wiki for details.
+config BOARD_LENOVO_X230
+ bool "ThinkPad X230"
+ help
+ Lenovo X230 laptop. Consult wiki for details.
+
config BOARD_LENOVO_T60
bool "ThinkPad T60 / T60p"
help
@@ -29,10 +34,15 @@ endchoice
source "src/mainboard/lenovo/x60/Kconfig"
source "src/mainboard/lenovo/x201/Kconfig"
+source "src/mainboard/lenovo/x230/Kconfig"
source "src/mainboard/lenovo/t60/Kconfig"
config MAINBOARD_VENDOR
string
default "Lenovo"
+config VENDOR_VERSION
+ string
+ default "CBET4000 "
+
endif # VENDOR_LENOVO
diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc
index 9055c9e..285e0d0 100644
--- a/src/mainboard/lenovo/x201/Makefile.inc
+++ b/src/mainboard/lenovo/x201/Makefile.inc
@@ -18,6 +18,7 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += dock.c
ramstage-y += dock.c
ramstage-y += gma.c
diff --git a/src/mainboard/lenovo/x201/dsdt.asl.orig b/src/mainboard/lenovo/x201/dsdt.asl.orig
new file mode 100644
index 0000000..ca47b13
--- /dev/null
+++ b/src/mainboard/lenovo/x201/dsdt.asl.orig
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20130325 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ #include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ #include "acpi/mainboard.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/nehalem/acpi/nehalem.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ Device (UNCR)
+ {
+ Name (_BBN, 0xFF)
+ Name (_ADR, 0x00)
+ Name (RID, 0x00)
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x00FF, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ Device (SAD)
+ {
+ Name (_ADR, 0x01)
+ Name (RID, 0x00)
+ OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
+ Field (SADC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x40),
+ PAM0, 8,
+ PAM1, 8,
+ PAM2, 8,
+ PAM3, 8,
+ PAM4, 8,
+ PAM5, 8,
+ PAM6, 8
+ }
+ }
+ }
+ }
+
+ #include "acpi/video.asl"
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+
+ // Dock support code
+ #include "acpi/dock.asl"
+}
diff --git a/src/mainboard/lenovo/x201/smihandler.c.orig b/src/mainboard/lenovo/x201/smihandler.c.orig
new file mode 100644
index 0000000..2558a9e
--- /dev/null
+++ b/src/mainboard/lenovo/x201/smihandler.c.orig
@@ -0,0 +1,210 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/ibexpeak/nvs.h"
+#include "southbridge/intel/ibexpeak/pch.h"
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include "dock.h"
+#include "smi.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+static void mainboard_smi_save_cmos(void)
+{
+ u8 val;
+ u8 tmp70, tmp72;
+
+ tmp70 = inb(0x70);
+ tmp72 = inb(0x72);
+
+ val = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);
+ set_option("tft_brightness", &val);
+ val = ec_read(H8_VOLUME_CONTROL);
+ set_option("volume", &val);
+
+ outb(tmp70, 0x70);
+ outb(tmp72, 0x72);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ case SMI_DOCK_CONNECT:
+ ec_clr_bit(0x03, 2);
+ udelay(250000);
+ if (!dock_connect()) {
+ ec_set_bit(0x03, 2);
+ /* set dock LED to indicate status */
+ ec_write(0x0c, 0x09);
+ ec_write(0x0c, 0x88);
+ } else {
+ /* blink dock LED to indicate failure */
+ ec_write(0x0c, 0x08);
+ ec_write(0x0c, 0xc9);
+ }
+ break;
+
+ case SMI_DOCK_DISCONNECT:
+ ec_clr_bit(0x03, 2);
+ dock_disconnect();
+ break;
+
+ case SMI_SAVE_CMOS:
+ mainboard_smi_save_cmos();
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
+ (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch (event) {
+ /* brightness up */
+ case 0x14:
+ mainboard_smi_brightness_up();
+ mainboard_smi_save_cmos();
+ break;
+ /* brightness down */
+ case 0x15:
+ mainboard_smi_brightness_down();
+ mainboard_smi_save_cmos();
+ break;
+ /* Fn-F9 key */
+ case 0x18:
+ /* Power loss */
+ case 0x27:
+ /* Undock Key */
+ case 0x50:
+ mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
+ break;
+ /* Dock Event */
+ case 0x37:
+ case 0x58:
+ mainboard_io_trap_handler(SMI_DOCK_CONNECT);
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << 12))
+ mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ u8 tmp;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
+ data);
+
+ if (!pmbase)
+ return 0;
+
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route H8SCI to SCI */
+ outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x02;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route H8SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/lenovo/x201/smihandler.c.rej b/src/mainboard/lenovo/x201/smihandler.c.rej
new file mode 100644
index 0000000..f52c463
--- /dev/null
+++ b/src/mainboard/lenovo/x201/smihandler.c.rej
@@ -0,0 +1,15 @@
+--- src/mainboard/lenovo/x201/smihandler.c
++++ src/mainboard/lenovo/x201/smihandler.c
+@@ -109,12 +109,10 @@
+ case 0x14:
+ /* brightness up */
+ mainboard_smi_brightness_up();
+- mainboard_smi_save_cmos();
+ break;
+ case 0x15:
+ /* brightness down */
+ mainboard_smi_brightness_down();
+- mainboard_smi_save_cmos();
+ break;
+ case 0x18:
+ /* Fn-F9 key */
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
new file mode 100644
index 0000000..a170a7f
--- /dev/null
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -0,0 +1,70 @@
+if BOARD_LENOVO_X230
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select EC_LENOVO_PMH7
+ select EC_LENOVO_H8
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_SMI_HANDLER
+ select GFXUMA
+ select EARLY_CBMEM_INIT
+
+ # Workaround for EC/KBC IRQ1.
+ select SERIRQ_CONTINUOUS_MODE
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config MAINBOARD_DIR
+ string
+ default lenovo/x230
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "2325TLU"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x17aa
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x21fa
+
+config MAINBOARD_VENDOR
+ string
+ default "LENOVO"
+
+endif # BOARD_LENOVO_X230
diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc
new file mode 100644
index 0000000..d514d4b
--- /dev/null
+++ b/src/mainboard/lenovo/x230/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/lenovo/x230/acpi/ec.asl b/src/mainboard/lenovo/x230/acpi/ec.asl
new file mode 100644
index 0000000..4b3e72c
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+}
diff --git a/src/mainboard/lenovo/x230/acpi/mainboard.asl b/src/mainboard/lenovo/x230/acpi/mainboard.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl
new file mode 100644
index 0000000..73478ea
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/platform.asl
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* Not implemented. */
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..ba725ac
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
+ Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
+ Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
+ Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
+ Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/lenovo/x230/acpi/superio.asl b/src/mainboard/lenovo/x230/acpi/superio.asl
new file mode 100644
index 0000000..a2657f1
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/superio.asl
@@ -0,0 +1 @@
+#include "../../../../drivers/pc80/ps2_controller.asl"
diff --git a/src/mainboard/lenovo/x230/acpi/video.asl b/src/mainboard/lenovo/x230/acpi/video.asl
new file mode 100644
index 0000000..12a268b
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/video.asl
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org>
+ * Copyright (c) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+
+Scope (\_SB.PCI0.GFX0)
+{
+ Device (LCD0)
+ {
+ Name (_ADR, 0x0400)
+ Name (BRCT, 0)
+
+ Name (BRIG, Package (0x12)
+ {
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (_BCL, 0, NotSerialized)
+ {
+ Store (1, BRCT)
+ Return (BRIG)
+ }
+
+ Method (_BCM, 1, NotSerialized)
+ {
+ Store (ShiftLeft (Arg0, 4), ^^BCLV)
+ Store (0x80000000, ^^CR1)
+ Store (0x061a061a, ^^CR2)
+ }
+ Method (_BQC, 0, NotSerialized)
+ {
+ Store (^^BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
+ }
+
+ Method(BRID, 1, NotSerialized)
+ {
+ Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
+ If (LEqual (Local0, Ones))
+ {
+ Return (0x11)
+ }
+ Return (Local0)
+ }
+
+ /* Using Notify is the right way. But Windows doesn't handle
+ it well. So use both method in a way to avoid double action.
+ */
+ Method (DECB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x87)
+ } Else {
+ Store (BRID (_BQC ()), Local0)
+ If (LNotEqual (Local0, 2))
+ {
+ Decrement (Local0)
+ }
+ _BCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+ Method (INCB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x86)
+ } Else {
+ Store (BRID (_BQC ()), Local0)
+ If (LNotEqual (Local0, 0x11))
+ {
+ Increment (Local0)
+ }
+ _BCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c
new file mode 100644
index 0000000..95b45db
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi_tables.c
@@ -0,0 +1,271 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ /* EC handles all thermal and fan control on Butterfly. */
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* CBMEM TOC */
+ gnvs->cmem = (u32)get_cbmem_toc();
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+ // TODO: MLR
+ // The firmware read/write status is a "virtual" switch and
+ // will be handled elsewhere. Until then hard-code to
+ // read/write instead of read-only for developer mode.
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RW;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+#if CONFIG_CHROMEOS
+ // TODO(reinauer) this could move elsewhere?
+ chromeos_init_vboot(&(gnvs->chromeos));
+#endif
+
+ acpi_update_thermal_table(gnvs);
+
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+ "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ /* And tell SMI about it */
+ smm_setup_structures((void *)current, NULL, NULL);
+
+ current += sizeof(global_nvs_t);
+ ALIGN_CURRENT;
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout
new file mode 100644
index 0000000..de8b182
--- /dev/null
+++ b/src/mainboard/lenovo/x230/cmos.layout
@@ -0,0 +1,141 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: EC
+411 1 e 8 first_battery
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 touchpad
+
+#415 569 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
new file mode 100644
index 0000000..94b5839
--- /dev/null
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -0,0 +1,140 @@
+chip northbridge/intel/sandybridge
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
+ register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
+ register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
+ register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ # Coordinate with HW_ALL
+ register "pstate_coord_type" = "0xfe"
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpi1_routing" = "2"
+ register "gpi8_routing" = "2"
+
+ register "ide_legacy_combined" = "0x0"
+ register "sata_ahci" = "0x1"
+ # Enable SATA ports 0 & 1
+ register "sata_port_map" = "0x3"
+ # Set max SATA speed to 3.0 Gb/s
+ register "sata_interface_speed_support" = "0x2"
+
+ register "gen1_dec" = "0x7c1601"
+ register "gen2_dec" = "0x0c15e1"
+ register "gen4_dec" = "0x0c06a1"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug)
+ device pci 1c.1 on end # PCIe Port #2 (ETH0)
+ device pci 1c.2 on end # PCIe Port #3 (Card Reader)
+ #force ASPM for PCIe bridge to Card Reader
+ register "pcie_aspm_f2" = "0x3"
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on #LPC bridge
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
+ end
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ end
+
+ chip ec/lenovo/h8
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+
+ register "config0" = "0xa6"
+ register "config1" = "0x09"
+ register "config2" = "0xa0"
+ register "config3" = "0xe0"
+
+ register "beepmask0" = "0x00"
+ register "beepmask1" = "0x86"
+
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xd0"
+ register "event5_enable" = "0xfc"
+ register "event6_enable" = "0x00"
+ register "event7_enable" = "0x01"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventa_enable" = "0x01"
+ register "eventb_enable" = "0x00"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x0d"
+
+ register "wlan_enable" = "0x01"
+ register "trackpoint_enable" = "0x03"
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl
new file mode 100644
index 0000000..5688f63
--- /dev/null
+++ b/src/mainboard/lenovo/x230/dsdt.asl
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define THINKPAD_EC_GPE 17
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+
+ #include "acpi/video.asl"
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/x230/ec.c b/src/mainboard/lenovo/x230/ec.c
new file mode 100644
index 0000000..96716a4
--- /dev/null
+++ b/src/mainboard/lenovo/x230/ec.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+
+void butterfly_ec_init(void)
+{
+ printk(BIOS_DEBUG, "Butterfly EC Init\n");
+
+
+}
diff --git a/src/mainboard/lenovo/x230/ec.h b/src/mainboard/lenovo/x230/ec.h
new file mode 100644
index 0000000..5bbbd5a
--- /dev/null
+++ b/src/mainboard/lenovo/x230/ec.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_EC_H
+#define BUTTERFLY_EC_H
+
+#define EC_SCI_GPI 13 /* GPIO13 is EC_SCI# */
+
+/* EC SMI sources TODO: MLR- make defines */
+
+#ifndef __ACPI__
+extern void butterfly_ec_init(void);
+#endif
+
+#endif // BUTTERFLY_EC_H
diff --git a/src/mainboard/lenovo/x230/fadt.c b/src/mainboard/lenovo/x230/fadt.c
new file mode 100644
index 0000000..0ce3c72
--- /dev/null
+++ b/src/mainboard/lenovo/x230/fadt.c
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+ 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 16;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 101; /* c2 not supported */
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD |
+ ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 128;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/lenovo/x230/gpio.h b/src/mainboard/lenovo/x230/gpio.h
new file mode 100644
index 0000000..b592e6a
--- /dev/null
+++ b/src/mainboard/lenovo/x230/gpio.h
@@ -0,0 +1,304 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_GPIO_H
+#define BUTTERFLY_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NONE, /* Unused */
+ .gpio1 = GPIO_MODE_NONE, /* Unused */
+ .gpio2 = GPIO_MODE_NONE, /* Unused */
+ .gpio3 = GPIO_MODE_NONE, /* Unused */
+ .gpio4 = GPIO_MODE_NATIVE, /* Native - TPSINT# for TP SMBus IRQ */
+ .gpio5 = GPIO_MODE_NONE, /* Unused */
+ .gpio6 = GPIO_MODE_GPIO, /* Input - BOARD_ID4 */
+ .gpio7 = GPIO_MODE_GPIO, /* Input - BOARD_ID5 */
+ .gpio8 = GPIO_MODE_GPIO, /* Output - BT on/off */
+ .gpio9 = GPIO_MODE_NONE, /* Unused */
+ .gpio10 = GPIO_MODE_NONE, /* Unused */
+ .gpio11 = GPIO_MODE_GPIO, /* Input - TP WAKEUP Event */
+ .gpio12 = GPIO_MODE_NONE, /* Unused */
+ .gpio13 = GPIO_MODE_GPIO, /* Input - SCI from EC */
+ .gpio14 = GPIO_MODE_GPIO, /* Output - AOAC WLAN power control */
+ .gpio15 = GPIO_MODE_GPIO, /* Unused - Do not control WLAN*/
+ .gpio16 = GPIO_MODE_NONE, /* Unused */
+ .gpio17 = GPIO_MODE_GPIO, /* Input - DGPU_PWROK */
+ .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin*/
+ .gpio19 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 0 */
+ .gpio20 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ2# SDCard clock pin */
+ .gpio21 = GPIO_MODE_GPIO, /* Input - EC_ENTERING_RW for Google OS */
+ .gpio22 = GPIO_MODE_GPIO, /* Input - BIOS RECOVERY */
+ .gpio23 = GPIO_MODE_NONE, /* Unused */
+ .gpio24 = GPIO_MODE_GPIO, /* Output - DGPU_HOLD_RST# */
+ .gpio25 = GPIO_MODE_NONE, /* Unused */
+ .gpio26 = GPIO_MODE_NONE, /* Unused */
+ .gpio27 = GPIO_MODE_NONE, /* Unused */
+ .gpio28 = GPIO_MODE_NONE, /* Unused */
+ .gpio29 = GPIO_MODE_NONE, /* Unused */
+ .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# */
+ .gpio31 = GPIO_MODE_NONE, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT, /* Unused */
+ .gpio1 = GPIO_DIR_INPUT, /* Unused */
+ .gpio2 = GPIO_DIR_INPUT, /* Unused */
+ .gpio3 = GPIO_DIR_INPUT, /* Unused */
+ .gpio4 = GPIO_DIR_INPUT, /* Native */
+ .gpio5 = GPIO_DIR_INPUT, /* Unused */
+ .gpio6 = GPIO_DIR_INPUT, /* Input */
+ .gpio7 = GPIO_DIR_INPUT, /* Input */
+ .gpio8 = GPIO_DIR_INPUT, /* Output HIGH - set in mainboard.c */
+ .gpio9 = GPIO_DIR_INPUT, /* Unused */
+ .gpio10 = GPIO_DIR_INPUT, /* Unused */
+ .gpio11 = GPIO_DIR_INPUT, /* Input */
+ .gpio12 = GPIO_DIR_INPUT, /* Unused */
+ .gpio13 = GPIO_DIR_INPUT, /* Input */
+ .gpio14 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio15 = GPIO_DIR_INPUT, /* Unused */
+ .gpio16 = GPIO_DIR_INPUT, /* Unused */
+ .gpio17 = GPIO_DIR_INPUT, /* Input */
+ .gpio18 = GPIO_DIR_INPUT, /* Native */
+ .gpio19 = GPIO_DIR_INPUT, /* Input */
+ .gpio20 = GPIO_DIR_INPUT, /* Native */
+ .gpio21 = GPIO_DIR_INPUT, /* Input */
+ .gpio22 = GPIO_DIR_INPUT, /* Input */
+ .gpio23 = GPIO_DIR_INPUT, /* Unused */
+ .gpio24 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio25 = GPIO_DIR_INPUT, /* Unused */
+ .gpio26 = GPIO_DIR_INPUT, /* Unused */
+ .gpio27 = GPIO_DIR_INPUT, /* Unused */
+ .gpio28 = GPIO_DIR_INPUT, /* Unused */
+ .gpio29 = GPIO_DIR_INPUT, /* Unused */
+ .gpio30 = GPIO_DIR_INPUT, /* Native */
+ .gpio31 = GPIO_DIR_INPUT, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio1 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio2 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio3 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio4 = GPIO_LEVEL_LOW, /* Native */
+ .gpio5 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio6 = GPIO_LEVEL_LOW, /* Input */
+ .gpio7 = GPIO_LEVEL_LOW, /* Input */
+ .gpio8 = GPIO_LEVEL_HIGH, /* Output HIGH - set in mainboard.c */
+ .gpio9 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio10 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio11 = GPIO_LEVEL_LOW, /* Input */
+ .gpio12 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio13 = GPIO_LEVEL_LOW, /* Input */
+ .gpio14 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio15 = GPIO_LEVEL_HIGH, /* Unused */
+ .gpio16 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio17 = GPIO_LEVEL_LOW, /* Input */
+ .gpio18 = GPIO_LEVEL_LOW, /* Native */
+ .gpio19 = GPIO_LEVEL_LOW, /* Input */
+ .gpio20 = GPIO_LEVEL_LOW, /* Native */
+ .gpio21 = GPIO_LEVEL_LOW, /* Input */
+ .gpio22 = GPIO_LEVEL_LOW, /* Input */
+ .gpio23 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio24 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio25 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio26 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio27 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio28 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio29 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio30 = GPIO_LEVEL_LOW, /* Native */
+ .gpio31 = GPIO_LEVEL_LOW, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */
+ .gpio13 = GPIO_INVERT, /* invert EC SCI pin */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */
+ .gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */
+ .gpio34 = GPIO_MODE_NONE, /* Unused */
+ .gpio35 = GPIO_MODE_NONE, /* Unused */
+ .gpio36 = GPIO_MODE_GPIO, /* Output - DGPU_PWR_EN */
+ .gpio37 = GPIO_MODE_GPIO, /* Input - FDI TERM / VOLTAGE OVERRIDE */
+ .gpio38 = GPIO_MODE_GPIO, /* Input - MFG_MODE test */
+ .gpio39 = GPIO_MODE_GPIO, /* Input - DGPU_PRSNT */
+ .gpio40 = GPIO_MODE_NONE, /* Unused */
+ .gpio41 = GPIO_MODE_NONE, /* Unused */
+ .gpio42 = GPIO_MODE_NONE, /* Unused */
+ .gpio43 = GPIO_MODE_NONE, /* Unused */
+ .gpio44 = GPIO_MODE_GPIO, /* Input - BOARD_ID0 */
+ .gpio45 = GPIO_MODE_GPIO, /* Input - BOARD_ID1 */
+ .gpio46 = GPIO_MODE_GPIO, /* Input - BOARD_ID2 */
+ .gpio47 = GPIO_MODE_NATIVE, /* Native - PEGA_GPU clock request */
+ .gpio48 = GPIO_MODE_NONE, /* Unused */
+ .gpio49 = GPIO_MODE_NONE, /* Unused */
+ .gpio50 = GPIO_MODE_NONE, /* Unused */
+ .gpio51 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 1 */
+ .gpio52 = GPIO_MODE_GPIO, /* Input - Google recovery, Pull up +3V */
+ .gpio53 = GPIO_MODE_GPIO, /* Output - G Sensor LED */
+ .gpio54 = GPIO_MODE_GPIO, /* Input - Google Development */
+ .gpio55 = GPIO_MODE_GPIO, /* Input - Top-Block Swap Override */
+ .gpio56 = GPIO_MODE_NONE, /* Unused */
+ .gpio57 = GPIO_MODE_GPIO, /* Input - SV_DET */
+ .gpio58 = GPIO_MODE_NONE, /* Unused */
+ .gpio59 = GPIO_MODE_NONE, /* Unused */
+ .gpio60 = GPIO_MODE_NONE, /* GPO - DRAMRST_CNTRL_PCH */
+ .gpio61 = GPIO_MODE_NONE, /* Unused */
+ .gpio62 = GPIO_MODE_NATIVE, /* Native - Connect to EC 32.768KHz */
+ .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT, /* Native */
+ .gpio33 = GPIO_DIR_INPUT, /* Input */
+ .gpio34 = GPIO_DIR_INPUT, /* Unused */
+ .gpio35 = GPIO_DIR_INPUT, /* Unused */
+ .gpio36 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio37 = GPIO_DIR_INPUT, /* Input */
+ .gpio38 = GPIO_DIR_INPUT, /* Input */
+ .gpio39 = GPIO_DIR_INPUT, /* Input */
+ .gpio40 = GPIO_DIR_INPUT, /* Unused */
+ .gpio41 = GPIO_DIR_INPUT, /* Unused */
+ .gpio42 = GPIO_DIR_INPUT, /* Unused */
+ .gpio43 = GPIO_DIR_INPUT, /* Unused */
+ .gpio44 = GPIO_DIR_INPUT, /* Input */
+ .gpio45 = GPIO_DIR_INPUT, /* Input */
+ .gpio46 = GPIO_DIR_INPUT, /* Input */
+ .gpio47 = GPIO_DIR_INPUT, /* Native */
+ .gpio48 = GPIO_DIR_INPUT, /* Unused */
+ .gpio49 = GPIO_DIR_INPUT, /* Unused */
+ .gpio50 = GPIO_DIR_INPUT, /* Unused */
+ .gpio51 = GPIO_DIR_INPUT, /* Input */
+ .gpio52 = GPIO_DIR_INPUT, /* Input */
+ .gpio53 = GPIO_DIR_OUTPUT, /* Input */
+ .gpio54 = GPIO_DIR_INPUT, /* Input */
+ .gpio55 = GPIO_DIR_INPUT, /* Input */
+ .gpio56 = GPIO_DIR_INPUT, /* Unused */
+ .gpio57 = GPIO_DIR_INPUT, /* Input */
+ .gpio58 = GPIO_DIR_INPUT, /* Unused */
+ .gpio59 = GPIO_DIR_INPUT, /* Unused */
+ .gpio60 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio61 = GPIO_DIR_INPUT, /* Unused */
+ .gpio62 = GPIO_DIR_INPUT, /* Native */
+ .gpio63 = GPIO_DIR_INPUT, /* Native */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_LOW, /* Native */
+ .gpio33 = GPIO_LEVEL_LOW, /* Input */
+ .gpio34 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio35 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio36 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio37 = GPIO_LEVEL_LOW, /* Input */
+ .gpio38 = GPIO_LEVEL_LOW, /* Input */
+ .gpio39 = GPIO_LEVEL_LOW, /* Input */
+ .gpio40 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio41 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio42 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio43 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio44 = GPIO_LEVEL_LOW, /* Input */
+ .gpio45 = GPIO_LEVEL_LOW, /* Input */
+ .gpio46 = GPIO_LEVEL_LOW, /* Input */
+ .gpio47 = GPIO_LEVEL_LOW, /* Native */
+ .gpio48 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio49 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio50 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio51 = GPIO_LEVEL_LOW, /* Input */
+ .gpio52 = GPIO_LEVEL_LOW, /* Input */
+ .gpio53 = GPIO_LEVEL_HIGH, /* Input */
+ .gpio54 = GPIO_LEVEL_LOW, /* Input */
+ .gpio55 = GPIO_LEVEL_LOW, /* Input */
+ .gpio56 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio57 = GPIO_LEVEL_LOW, /* Input */
+ .gpio58 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio59 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio60 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio61 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio62 = GPIO_LEVEL_LOW, /* Native */
+ .gpio63 = GPIO_LEVEL_LOW, /* Native */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NONE, /* Unused */
+ .gpio65 = GPIO_MODE_NONE, /* Unused */
+ .gpio66 = GPIO_MODE_NONE, /* Unused */
+ .gpio67 = GPIO_MODE_NONE, /* Unused */
+ .gpio68 = GPIO_MODE_GPIO, /* Input - DGPU_PWR_EN */
+ .gpio69 = GPIO_MODE_NONE, /* Unused */
+ .gpio70 = GPIO_MODE_NONE, /* Unused */
+ .gpio71 = GPIO_MODE_NONE, /* Unused */
+ .gpio72 = GPIO_MODE_NONE, /* Unused */
+ .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# WLAN clock request */
+ .gpio74 = GPIO_MODE_NONE, /* Unused */
+ .gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT, /* Unused */
+ .gpio65 = GPIO_DIR_INPUT, /* Unused */
+ .gpio66 = GPIO_DIR_INPUT, /* Unused */
+ .gpio67 = GPIO_DIR_INPUT, /* Unused */
+ .gpio68 = GPIO_DIR_INPUT, /* Input */
+ .gpio69 = GPIO_DIR_INPUT, /* Unused */
+ .gpio70 = GPIO_DIR_INPUT, /* Unused */
+ .gpio71 = GPIO_DIR_INPUT, /* Unused */
+ .gpio72 = GPIO_DIR_INPUT, /* Unused */
+ .gpio73 = GPIO_DIR_INPUT, /* Native */
+ .gpio74 = GPIO_DIR_INPUT, /* Unused */
+ .gpio75 = GPIO_DIR_INPUT, /* Input */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio65 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio66 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio67 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio68 = GPIO_LEVEL_LOW, /* Input */
+ .gpio69 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio70 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio71 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio72 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio73 = GPIO_LEVEL_LOW, /* Native */
+ .gpio74 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio75 = GPIO_LEVEL_LOW, /* Input */
+};
+
+const struct pch_gpio_map butterfly_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+#endif
diff --git a/src/mainboard/lenovo/x230/hda_verb.h b/src/mainboard/lenovo/x230/hda_verb.h
new file mode 100644
index 0000000..7d22897
--- /dev/null
+++ b/src/mainboard/lenovo/x230/hda_verb.h
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Vendor Name : IDT
+ * Vendor ID : 0x111d76e5
+ * Subsystem ID : 0x103c18f9
+ * Revision ID : 0x100303
+ */
+
+
+static const u32 mainboard_cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC
+ 0x17aa21fa, // Subsystem ID
+ 0x00000073, // Number of 4 dword sets
+
+/* Bits 31:28 - Codec Address */
+/* Bits 27:20 - NID */
+/* Bits 19:8 - Verb ID */
+/* Bits 7:0 - Payload */
+
+/* NID 0x01 - NodeInfo */
+ 0x001720F9,
+ 0x00172118,
+ 0x0017223C,
+ 0x00172310,
+
+/* NID 0x0A - External Microphone Connector
+ * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
+ */
+ 0x00A71C20,
+ 0x00A71D10,
+ 0x00A71EA1,
+ 0x00A71F04,
+
+/* NID 0x0B - Headphone Connector
+ * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
+ */
+ 0x00B71C1F,
+ 0x00B71D10,
+ 0x00B71E21,
+ 0x00B71F04,
+
+/* NID 0x0C - Not connected
+ * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
+ */
+ 0x00C71CF0,
+ 0x00C71D00,
+ 0x00C71EF0,
+ 0x00C71F40,
+
+/* NID 0x0D - Internal Speakers
+ * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
+ */
+ 0x00D71C10,
+ 0x00D71D01,
+ 0x00D71E17,
+ 0x00D71F90,
+
+/* NID 0x0F - Not connected
+ * Config=0x40F000F0
+ */
+ 0x00F71CF0,
+ 0x00F71D00,
+ 0x00F71EF0,
+ 0x00F71F40,
+
+/* NID 0x11 - Internal Microphone
+ * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
+ */
+ 0x01171C40,
+ 0x01171D01,
+ 0x01171EA3,
+ 0x01171FD5,
+
+ /*
+ * Hardware EQ Parameters
+ * Sample Rate 88200
+ */
+ 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
+ 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80,
+ 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981,
+ 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80,
+ 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
+ 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80,
+ 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E,
+ 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80,
+ 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1,
+ 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80,
+ 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E,
+ 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80,
+ 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983,
+ 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80,
+ 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D,
+ 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80,
+ 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C,
+ 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80,
+ 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3,
+ 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80,
+ 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F,
+ 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80,
+ 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982,
+ 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80,
+ 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E,
+ 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80,
+ 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D,
+ 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80,
+ 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2,
+ 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80,
+ 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F,
+ 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80,
+ 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E,
+ 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80,
+ 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937,
+ 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80,
+ 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971,
+ 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80,
+ 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9,
+ 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80,
+ 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942,
+ 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80,
+ 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C,
+ 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80,
+ 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934,
+ 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80,
+ 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963,
+ 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80,
+ 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9,
+ 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80,
+ 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
+ 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80,
+
+ /*
+ * Hardware EQ Parameters
+ * Sample Rate 96000
+ */
+ 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
+ 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80,
+ 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981,
+ 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80,
+ 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
+ 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80,
+ 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E,
+ 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80,
+ 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1,
+ 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80,
+ 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E,
+ 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80,
+ 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983,
+ 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80,
+ 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D,
+ 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80,
+ 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C,
+ 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80,
+ 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3,
+ 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80,
+ 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F,
+ 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80,
+ 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982,
+ 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80,
+ 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E,
+ 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80,
+ 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D,
+ 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80,
+ 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1,
+ 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80,
+ 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F,
+ 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80,
+ 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D,
+ 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80,
+ 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938,
+ 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80,
+ 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972,
+ 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80,
+ 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8,
+ 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80,
+ 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941,
+ 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80,
+ 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999,
+ 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80,
+ 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934,
+ 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80,
+ 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966,
+ 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80,
+ 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9,
+ 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80,
+ 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
+ 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80,
+
+ /* SAFEDSP Parameters */
+ 0x022782C1, 0x02277127, 0x02277227, 0x02278801,
+ 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14,
+ 0x02278B0F, 0x0017B008,
+
+ /* Misc entries */
+ 0x00B707C0, /* Enable PortB as Output with HP amp */
+ 0x00D70740, /* Enable PortD as Output */
+ 0x0017A200, /* Disable ClkEn of PortSenseTst */
+ 0x0017C621, /* Slave Port - Port A used as microphone input for
+ combo Jack
+ Master Port - Port B used for Jack Presence Detect
+ Enable Combo Jack Detection */
+ 0x0017A208, /* Enable ClkEn of PortSenseTst */
+ 0x00170500, /* Set power state to D0 */
+
+ /* --- Next Codec --- */
+
+/* Vendor Name : Intel
+ * Vendor ID : 0x80862806
+ * Subsystem ID : 0x80860101
+ * Revision ID : 0x100000
+ */
+ /* coreboot specific header */
+ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of IDs
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ 0x30172001,
+ 0x30172101,
+ 0x30172286,
+ 0x30172380,
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ 0x30571c10,
+ 0x30571d00,
+ 0x30571e56,
+ 0x30571f18,
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ 0x30671c20,
+ 0x30671d00,
+ 0x30671e56,
+ 0x30671f18,
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ 0x30771c30,
+ 0x30771d00,
+ 0x30771e56,
+ 0x30771f18
+};
+
+static const u32 mainboard_pc_beep_verbs[] = {
+ 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
+};
+
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
+
+
diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c
new file mode 100644
index 0000000..b6b0b07
--- /dev/null
+++ b/src/mainboard/lenovo/x230/mainboard.c
@@ -0,0 +1,186 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+#include "ec.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <cbfs.h>
+#include <pc80/keyboard.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+ int res = 0;
+
+ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+ __func__, X86_AX);
+
+ switch (X86_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ X86_AX = 0x005f;
+ X86_CL = 0x00; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0001; /* Int-LVDS */
+ res = 1;
+ break;
+ case 0x5f70:
+ switch (X86_CH) {
+ case 0:
+ /* Get Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ X86_CH);
+ break;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+ break;
+ }
+ return res;
+}
+#endif
+
+const char *smbios_mainboard_version(void)
+{
+ return "Lenovo X230";
+}
+
+/* Audio Setup */
+
+extern const u32 *cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 *pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+
+}
+
+static void mainboard_init(device_t dev)
+{
+
+ /* This sneaked in here, because X201 SuperIO chip isn't really
+ connected to anything and hence we don't init it.
+ */
+ pc_keyboard_init(0);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+#if CONFIG_VGA_ROM_RUN
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+ verb_setup();
+}
+
+void h8_mainboard_init_dock (void);
+
+void h8_mainboard_init_dock (void)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/x230/onboard.h b/src/mainboard/lenovo/x230/onboard.h
new file mode 100644
index 0000000..e32e023
--- /dev/null
+++ b/src/mainboard/lenovo/x230/onboard.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_ONBOARD_H
+#define BUTTERFLY_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+/* uses 7-bit I2C address */
+/* must be set to edge triggered */
+#define BUTTERFLY_TRACKPAD_NAME "trackpad"
+#define BUTTERFLY_TRACKPAD_I2C_ADDR 0x67
+#define BUTTERFLY_TRACKPAD_IRQ 22 /* PIRQG - 22 Edge triggered */
+
+/* defines for programming the MAC address */
+#define BUTTERFLY_NIC_VENDOR_ID 0x10EC
+#define BUTTERFLY_NIC_DEVICE_ID 0x8136
+
+/* 0x00: White LINK LED and Amber ACTIVE LED */
+#define BUTTERFLY_NIC_LED_MODE 0x00
+#endif
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
new file mode 100644
index 0000000..1d1daf5
--- /dev/null
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <cbfs.h>
+
+static void pch_enable_lpc(void)
+{
+ /* X230 EC Decode Range Port60/64, Port62/66 */
+ /* Enable EC, PS/2 Keyboard/Mouse */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ COMA_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
+
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+
+ pci_write_config32(PCH_LPC_DEV, 0xac,
+ 0x80010000);
+}
+
+static void rcba_config(void)
+{
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P1IP WLAN INTA -> PIRQB
+ * D28IP_P2IP ETH0 INTB -> PIRQF
+ * D28IP_P3IP SDCARD INTC -> PIRQD
+ * D29IP_E1P EHCI1 INTA -> PIRQD
+ * D26IP_E2P EHCI2 INTA -> PIRQF
+ * D31IP_SIP SATA INTA -> PIRQB (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQH
+ * D31IP_TTIP THRT INTC -> PIRQA
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ *
+ * Trackpad interrupt is edge triggered and cannot be shared.
+ * TRACKPAD -> PIRQG
+
+ */
+
+ /* Device interrupt pin register (board specific) */
+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+ RCBA32(D29IP) = (INTA << D29IP_E1P);
+ RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
+ (INTC << D28IP_P3IP);
+ RCBA32(D27IP) = (INTA << D27IP_ZIP);
+ RCBA32(D26IP) = (INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+ /* Device interrupt route registers */
+ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+ DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+ DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
+ DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+ /* Enable IOAPIC (generic) */
+ RCBA16(OIC) = 0x0100;
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void) RCBA16(OIC);
+
+ /* Disable unused devices (board specific) */
+ RCBA32(FD) = 0x17f81fe3;
+ RCBA32(BUC) = 0;
+}
+
+void main(unsigned long bist)
+{
+ int boot_mode = 0;
+ int cbmem_was_initted;
+ u32 pm1_cnt;
+ u16 pm1_sts;
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ outb(0x6, 0xcf9);
+ hlt ();
+ }
+
+ struct pei_data pei_data = {
+ pei_version: PEI_VERSION,
+ mchbar: DEFAULT_MCHBAR,
+ dmibar: DEFAULT_DMIBAR,
+ epbar: DEFAULT_EPBAR,
+ pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+ smbusbar: SMBUS_IO_BASE,
+ wdbbar: 0x4000000,
+ wdbsize: 0x1000,
+ hpet_address: CONFIG_HPET_ADDRESS,
+ rcba: DEFAULT_RCBABASE,
+ pmbase: DEFAULT_PMBASE,
+ gpiobase: DEFAULT_GPIOBASE,
+ thermalbase: 0xfed08000,
+ system_type: 0, // 0 Mobile, 1 Desktop/Server
+ tseg_size: CONFIG_SMM_TSEG_SIZE,
+ spd_addresses: { 0xA0, 0x00,0xA2,0x00 },
+ ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+ ec_present: 1,
+ gbe_enable: 1,
+ ddr3lv_support: 0,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ dimm_channel0_disabled: 2,
+ dimm_channel1_disabled: 2,
+ max_ddr3_freq: 1600,
+ usb_port_config: {
+ /* enabled usb oc pin length */
+ { 1, 0, 0x0080 }, /* P0 */
+ { 1, 0, 0x0080 }, /* P1 */
+ { 1, 0, 0x0080 }, /* P3 */
+ { 1, 0, 0x0080 }, /* P4 */
+ { 1, 0, 0x0080 }, /* P5 */
+ { 1, 0, 0x0080 }, /* P6 */
+ { 1, 0, 0x0080 }, /* P7 */
+ { 1, 0, 0x0080 }, /* P8 */
+ { 1, 0, 0x0080 }, /* P9 */
+ { 1, 0, 0x0080 }, /* P10 */
+ { 1, 0, 0x0080 }, /* P11 */
+ { 1, 0, 0x0080 }, /* P12 */
+ { 1, 0, 0x0080 }, /* P13 */
+ { 1, 0, 0x0080 }, /* P14 */
+ { 1, 0, 0x0080 }, /* P15 */
+ },
+ ddr_refresh_rate_config: 2, /* Force double refresh rate */
+ };
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ if (bist == 0)
+ enable_lapic();
+
+
+ pch_enable_lpc();
+
+ /* Enable GPIOs */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+
+ // setup_pch_gpios(&butterfly_gpio_map);
+ outl (0x3962a5ff, DEFAULT_GPIOBASE | 0x0000);
+ outl (0x8ebf6aff, DEFAULT_GPIOBASE | 0x0004);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0008);
+ outl (0x66ff7efb, DEFAULT_GPIOBASE | 0x000c);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0010);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0014);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0018);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x001c);
+ outl (0x00080000, DEFAULT_GPIOBASE | 0x0020);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0024);
+ outw (0x0000, DEFAULT_GPIOBASE | 0x0028);
+ outw (0x0000, DEFAULT_GPIOBASE | 0x002a);
+ outl (0x00002042, DEFAULT_GPIOBASE | 0x002c);
+ outl (0x02ff08fe, DEFAULT_GPIOBASE | 0x0030);
+ outl (0x1f47f7fd, DEFAULT_GPIOBASE | 0x0034);
+ outl (0xbfffff43, DEFAULT_GPIOBASE | 0x0038);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x003c);
+ outl (0x000000ff, DEFAULT_GPIOBASE | 0x0040);
+ outl (0x00000fff, DEFAULT_GPIOBASE | 0x0044);
+ outl (0x00000fcf, DEFAULT_GPIOBASE | 0x0048);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x004c);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0050);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0054);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0058);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x005c);
+ outl (0x01000000, DEFAULT_GPIOBASE | 0x0060);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0064);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0068);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x006c);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0070);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0074);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0078);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x007c);
+
+ /* Initialize console device(s) */
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+ printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+ if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+ }
+
+ post_code(0x38);
+ /* Enable SPD ROMs and DDR-III DRAM */
+ enable_smbus();
+
+ /* Prepare USB controller early in S3 resume */
+ if (boot_mode == 2)
+ enable_usb_bar();
+
+ post_code(0x39);
+
+ post_code(0x3a);
+ pei_data.boot_mode = boot_mode;
+ timestamp_add_now(TS_BEFORE_INITRAM);
+
+ /* MRC.bin has a bug and sometimes halts (instead of reboot?).
+ */
+ if (boot_mode != 2)
+ {
+ RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */
+ outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */
+ }
+
+ sdram_initialize(&pei_data);
+
+ if (boot_mode != 2)
+ {
+ RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
+ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
+ }
+
+ timestamp_add_now(TS_AFTER_INITRAM);
+ post_code(0x3c);
+
+ rcba_config();
+ post_code(0x3d);
+
+ quick_ram_check();
+ post_code(0x3e);
+
+ MCHBAR16(SSKPD) = 0xCAFE;
+ cbmem_was_initted = !cbmem_initialize();
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+
+ *(u32 *)CBMEM_BOOT_MODE = 0;
+ *(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+ if ((boot_mode == 2) && cbmem_was_initted) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+ if (resume_backup_memory) {
+ *(u32 *)CBMEM_BOOT_MODE = boot_mode;
+ *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+ }
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ } else if (boot_mode == 2) {
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0x6, 0xcf9);
+ hlt();
+ } else {
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ }
+#endif
+ post_code(0x3f);
+#if CONFIG_CHROMEOS
+ init_chromeos(boot_mode);
+#endif
+ timestamp_add_now(TS_END_ROMSTAGE);
+}
diff --git a/src/mainboard/lenovo/x230/smi.h b/src/mainboard/lenovo/x230/smi.h
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c
new file mode 100644
index 0000000..ca92091
--- /dev/null
+++ b/src/mainboard/lenovo/x230/smihandler.c
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include "smi.h"
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
+ (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch (event) {
+ case 0x14:
+ /* brightness up */
+ mainboard_smi_brightness_up();
+ break;
+ case 0x15:
+ /* brightness down */
+ mainboard_smi_brightness_down();
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << 12))
+ mainboard_smi_handle_ec_sci();
+}
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ u8 tmp;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
+ data);
+
+ if (!pmbase)
+ return 0;
+
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route H8SCI to SCI */
+ outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x02;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route H8SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_FINALIZE:
+ printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/lenovo/x230/thermal.h b/src/mainboard/lenovo/x230/thermal.h
new file mode 100644
index 0000000..9657fe0
--- /dev/null
+++ b/src/mainboard/lenovo/x230/thermal.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_THERMAL_H
+#define BUTTERFLY_THERMAL_H
+
+/* Active Thermal and fans are controlled by the EC. */
+
+ /* Temperature which OS will shutdown at */
+ #define CRITICAL_TEMPERATURE 100
+
+ /* Temperature which OS will throttle CPU */
+ #define PASSIVE_TEMPERATURE 90
+
+#endif
diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl
index a6804ad..7d3d4db 100644
--- a/src/northbridge/intel/sandybridge/acpi/igd.asl
+++ b/src/northbridge/intel/sandybridge/acpi/igd.asl
@@ -23,6 +23,23 @@ Device (GFX0)
{
Name (_ADR, 0x00020000)
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ BAR0, 64
+ }
+
+ OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x48254),
+ BCLV, 16,
+ Offset (0xc8250),
+ CR1, 32,
+ CR2, 32
+ }
+
/* Display Output Switching */
Method (_DOS, 1)
{
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index e19d2c5..a13a971 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -34,8 +34,8 @@
#endif
/* convert a pointer to flash area into the offset inside the flash */
-static inline u32 to_flash_offset(void *p) {
- return ((u32)p + CONFIG_ROM_SIZE);
+static inline u32 to_flash_offset(struct spi_flash *flash, void *p) {
+ return ((u32)p + flash->size);
}
static struct mrc_data_container *next_mrc_block(
@@ -192,7 +192,12 @@ static void update_mrc_cache(void *unused)
// 1. use spi_flash_probe() to find the flash, then
spi_init();
- struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ struct spi_flash *flash = 0;
+
+ if (!spi_is_multichip ())
+ flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!flash)
+ flash = spi_flash_hwseq(0, 0, 1000000, SPI_MODE_3);
if (!flash) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
@@ -212,7 +217,7 @@ static void update_mrc_cache(void *unused)
"Need to erase the MRC cache region of %d bytes at %p\n",
cache_size, cache_base);
- flash->erase(flash, to_flash_offset(cache_base), cache_size);
+ flash->erase(flash, to_flash_offset(flash, cache_base), cache_size);
/* we will start at the beginning again */
cache = cache_base;
@@ -220,7 +225,7 @@ static void update_mrc_cache(void *unused)
// 4. write mrc data with flash->write()
printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n",
cache);
- flash->write(flash, to_flash_offset(cache),
+ flash->write(flash, to_flash_offset(flash, cache),
current->mrc_data_size + sizeof(*current), current);
}
@@ -232,6 +237,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = {
struct mrc_data_container *find_current_mrc_cache(void)
{
+ return NULL;
struct mrc_data_container *cache_base;
u32 cache_size;
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 333a6b5..3dab218 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -219,7 +219,7 @@ static void post_system_agent_init(struct pei_data *pei_data)
void sdram_initialize(struct pei_data *pei_data)
{
struct sys_info sysinfo;
- unsigned long entry;
+ int (*entry) (struct pei_data *pei_data) __attribute__ ((regparm(1)));
report_platform_info();
@@ -252,13 +252,11 @@ void sdram_initialize(struct pei_data *pei_data)
/* Locate and call UEFI System Agent binary. */
/* TODO make MRC blob (0xab?) defined in cbfs_core.h. */
- entry = (unsigned long)cbfs_get_file_content(
+ entry = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab);
if (entry) {
int rv;
- asm volatile (
- "call *%%ecx\n\t"
- :"=a" (rv) : "c" (entry), "a" (pei_data));
+ rv = entry (pei_data);
if (rv) {
switch (rv) {
case -1:
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 90de855..6382481 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -58,6 +58,14 @@ void intel_pch_finalize_smm(void);
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
+int spi_is_multichip(void);
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+#endif
+#endif
+
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
void pch_enable(device_t dev);
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index ec5d7de..959c29c 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
+ * Copyright (C) 2011 Stefan Tauner
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,11 +30,20 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci.h>
+#include <spi_flash.h>
#include <spi-generic.h>
+#include "pch.h"
#define min(a, b) ((a)<(b)?(a):(b))
+#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
+#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
+#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
+#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
+
+
#ifdef __SMM__
#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
@@ -115,7 +126,11 @@ typedef struct ich9_spi_regs {
typedef struct ich_spi_controller {
int locked;
+ int revision;
+ uint32_t flmap0;
+ uint32_t hsfs;
+ ich9_spi_regs *ich9_spi;
uint8_t *opmenu;
int menubytes;
uint16_t *preop;
@@ -356,6 +371,7 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
+ cntlr.revision = ich_version;
switch (ich_version) {
case 7:
{
@@ -381,7 +397,11 @@ void spi_init(void)
const uint16_t ich9_spibar_offset = 0x3800;
ich9_spi_regs *ich9_spi =
(ich9_spi_regs *)(rcrb + ich9_spibar_offset);
- ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ uint16_t hsfs;
+ cntlr.ich9_spi = ich9_spi;
+ hsfs = readw_(&ich9_spi->hsfs);
+ ichspi_lock = hsfs & HSFS_FLOCKDN;
+ cntlr.hsfs = hsfs;
cntlr.opmenu = ich9_spi->opmenu;
cntlr.menubytes = sizeof(ich9_spi->opmenu);
cntlr.optype = &ich9_spi->optype;
@@ -392,6 +412,12 @@ void spi_init(void)
cntlr.control = (uint16_t *)ich9_spi->ssfc;
cntlr.bbar = &ich9_spi->bbar;
cntlr.preop = &ich9_spi->preop;
+
+ if (cntlr.hsfs & HSFS_FDV)
+ {
+ writel_ (4, &ich9_spi->fdoc);
+ cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ }
break;
}
default:
@@ -591,6 +617,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+int spi_is_multichip (void)
+{
+ if (cntlr.revision != 9)
+ return 0;
+ if (!(cntlr.hsfs & HSFS_FDV))
+ return 0;
+ return !!((cntlr.flmap0 >> 8) & 3);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bitsout, void *din, unsigned int bitsin)
{
@@ -743,3 +778,313 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return 0;
}
+
+/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
+static void ich_hwseq_set_addr(uint32_t addr)
+{
+ uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
+ writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
+}
+
+/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
+ Resets all error flags in HSFS.
+ Returns 0 if the cycle completes successfully without errors within
+ timeout us, 1 on errors. */
+static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
+ unsigned int len)
+{
+ uint16_t hsfs;
+ uint32_t addr;
+
+ timeout /= 8; /* scale timeout duration to counter */
+ while ((((hsfs = readw_(cntlr.ich9_spi->hsfs)) &
+ (HSFS_FDONE | HSFS_FCERR)) == 0) &&
+ --timeout) {
+ udelay(8);
+ }
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ if (!timeout) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+
+ if (hsfs & HSFS_FCERR) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+ return 0;
+}
+
+
+static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 start, end, erase_size;
+ int ret;
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ start = offset;
+ end = start + len;
+
+ while (offset < end) {
+ ich_hwseq_set_addr(offset);
+
+ offset += erase_size;
+
+ /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+ if (ich_hwseq_wait_for_cycle_complete(timeout, len))
+ {
+ printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
+ ret = -1;
+ goto out;
+ }
+ }
+
+ printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static void ich_read_data(uint8_t *data, int len)
+{
+ int i;
+ uint32_t temp32 = 0;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = readl_(cntlr.data + i);
+
+ data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
+ }
+}
+
+static int ich_hwseq_read(struct spi_flash *flash,
+ u32 addr, size_t len, void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to read %x-%x which is out of chip\n",
+ (unsigned) addr,
+ (unsigned) addr+(unsigned) len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ block_len = min(len, cntlr.databytes);
+ ich_hwseq_set_addr(addr);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* set read operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ return 1;
+ ich_read_data(buf, block_len);
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ return 0;
+}
+
+/* Fill len bytes from the data array into the fdata/spid registers.
+ *
+ * Note that using len > flash->pgm->spi.max_data_write will trash the registers
+ * following the data registers.
+ */
+static void ich_fill_data(const uint8_t *data, int len)
+{
+ uint32_t temp32 = 0;
+ int i;
+
+ if (len <= 0)
+ return;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = 0;
+
+ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
+
+ if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+ }
+ i--;
+ if ((i % 4) != 3) /* Write remaining data to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+}
+
+static int ich_hwseq_write(struct spi_flash *flash,
+ u32 addr, size_t len, const void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+ uint32_t start = addr;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to write 0x%x-0x%x which is out of chip\n",
+ (unsigned)addr, (unsigned) (addr+len));
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ ich_hwseq_set_addr(addr);
+ block_len = min(len, cntlr.databytes);
+ ich_fill_data(buf, block_len);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ {
+ printk (BIOS_ERR, "SF: write failure at %x\n",
+ addr);
+ return -1;
+ }
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
+ (unsigned) (addr - start), start);
+ return 0;
+}
+
+
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ int ret;
+
+ if (cntlr.revision != 9) {
+ printk(BIOS_WARNING, "SF: Unsupported revision %x\n",
+ cntlr.revision);
+ return NULL;
+ }
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printk(BIOS_WARNING, "SF: Failed to set up slave\n");
+ free (flash);
+ return NULL;
+ }
+
+ spi->rw = SPI_READ_FLAG;
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret);
+ free (flash);
+ return NULL;
+ }
+
+ flash->spi = spi;
+ flash->name = "Opaque HW-sequencing";
+
+ flash->write = ich_hwseq_write;
+ flash->erase = ich_hwseq_erase;
+ flash->read = ich_hwseq_read;
+ switch ((cntlr.hsfs >> 3) & 3)
+ {
+ case 0:
+ flash->sector_size = 256;
+ break;
+ case 1:
+ flash->sector_size = 4096;
+ break;
+ case 2:
+ flash->sector_size = 8192;
+ break;
+ case 3:
+ flash->sector_size = 65536;
+ break;
+ }
+
+ uint32_t flcomp;
+
+ writel_ (0x1000, &cntlr.ich9_spi->fdoc);
+ flcomp = readl_(&cntlr.ich9_spi->fdod);
+
+ flash->size = 1 << (19 + (flcomp & 7));
+
+ if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
+ flash->size += 1 << (19 + ((flcomp >> 3) & 7));
+ printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
+
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
+ printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
+ flash->name, flash->sector_size, flash->size);
+
+ spi_release_bus(spi);
+
+ return flash;
+}
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 356dd8a..2728b54 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -59,6 +59,14 @@ void intel_pch_finalize_smm(void);
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
+int spi_is_multichip(void);
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+#endif
+#endif
+
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
void pch_enable(device_t dev);
diff --git a/src/southbridge/intel/ibexpeak/spi.c b/src/southbridge/intel/ibexpeak/spi.c
index e263b7f..6ff8fce 100644
--- a/src/southbridge/intel/ibexpeak/spi.c
+++ b/src/southbridge/intel/ibexpeak/spi.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
+ * Copyright (C) 2011 Stefan Tauner
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,11 +30,20 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci.h>
+#include <spi_flash.h>
#include <spi-generic.h>
+#include "pch.h"
#define min(a, b) ((a)<(b)?(a):(b))
+#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
+#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
+#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
+#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
+
+
#ifdef __SMM__
#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
@@ -115,7 +126,11 @@ typedef struct ich9_spi_regs {
typedef struct ich_spi_controller {
int locked;
+ int revision;
+ uint32_t flmap0;
+ uint32_t hsfs;
+ ich9_spi_regs *ich9_spi;
uint8_t *opmenu;
int menubytes;
uint16_t *preop;
@@ -357,6 +372,7 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
+ cntlr.revision = ich_version;
switch (ich_version) {
case 7:
{
@@ -382,7 +398,11 @@ void spi_init(void)
const uint16_t ich9_spibar_offset = 0x3800;
ich9_spi_regs *ich9_spi =
(ich9_spi_regs *)(rcrb + ich9_spibar_offset);
- ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ uint16_t hsfs;
+ cntlr.ich9_spi = ich9_spi;
+ hsfs = readw_(&ich9_spi->hsfs);
+ ichspi_lock = hsfs & HSFS_FLOCKDN;
+ cntlr.hsfs = hsfs;
cntlr.opmenu = ich9_spi->opmenu;
cntlr.menubytes = sizeof(ich9_spi->opmenu);
cntlr.optype = &ich9_spi->optype;
@@ -393,6 +413,12 @@ void spi_init(void)
cntlr.control = (uint16_t *)ich9_spi->ssfc;
cntlr.bbar = &ich9_spi->bbar;
cntlr.preop = &ich9_spi->preop;
+
+ if (cntlr.hsfs & HSFS_FDV)
+ {
+ writel_ (4, &ich9_spi->fdoc);
+ cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ }
break;
}
default:
@@ -592,6 +618,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+int spi_is_multichip (void)
+{
+ if (cntlr.revision != 9)
+ return 0;
+ if (!(cntlr.hsfs & HSFS_FDV))
+ return 0;
+ return !!((cntlr.flmap0 >> 8) & 3);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bitsout, void *din, unsigned int bitsin)
{
@@ -744,3 +779,313 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return 0;
}
+
+/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
+static void ich_hwseq_set_addr(uint32_t addr)
+{
+ uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
+ writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
+}
+
+/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
+ Resets all error flags in HSFS.
+ Returns 0 if the cycle completes successfully without errors within
+ timeout us, 1 on errors. */
+static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
+ unsigned int len)
+{
+ uint16_t hsfs;
+ uint32_t addr;
+
+ timeout /= 8; /* scale timeout duration to counter */
+ while ((((hsfs = readw_(cntlr.ich9_spi->hsfs)) &
+ (HSFS_FDONE | HSFS_FCERR)) == 0) &&
+ --timeout) {
+ udelay(8);
+ }
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ if (!timeout) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+
+ if (hsfs & HSFS_FCERR) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+ return 0;
+}
+
+
+static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 start, end, erase_size;
+ int ret;
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ start = offset;
+ end = start + len;
+
+ while (offset < end) {
+ ich_hwseq_set_addr(offset);
+
+ offset += erase_size;
+
+ /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+ if (ich_hwseq_wait_for_cycle_complete(timeout, len))
+ {
+ printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
+ ret = -1;
+ goto out;
+ }
+ }
+
+ printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static void ich_read_data(uint8_t *data, int len)
+{
+ int i;
+ uint32_t temp32 = 0;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = readl_(cntlr.data + i);
+
+ data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
+ }
+}
+
+static int ich_hwseq_read(struct spi_flash *flash,
+ u32 addr, size_t len, void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to read %x-%x which is out of chip\n",
+ (unsigned) addr,
+ (unsigned) addr+(unsigned) len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ block_len = min(len, cntlr.databytes);
+ ich_hwseq_set_addr(addr);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* set read operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ return 1;
+ ich_read_data(buf, block_len);
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ return 0;
+}
+
+/* Fill len bytes from the data array into the fdata/spid registers.
+ *
+ * Note that using len > flash->pgm->spi.max_data_write will trash the registers
+ * following the data registers.
+ */
+static void ich_fill_data(const uint8_t *data, int len)
+{
+ uint32_t temp32 = 0;
+ int i;
+
+ if (len <= 0)
+ return;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = 0;
+
+ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
+
+ if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+ }
+ i--;
+ if ((i % 4) != 3) /* Write remaining data to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+}
+
+static int ich_hwseq_write(struct spi_flash *flash,
+ u32 addr, size_t len, const void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+ uint32_t start = addr;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to write 0x%x-0x%x which is out of chip\n",
+ (unsigned)addr, (unsigned) (addr+len));
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ ich_hwseq_set_addr(addr);
+ block_len = min(len, cntlr.databytes);
+ ich_fill_data(buf, block_len);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ {
+ printk (BIOS_ERR, "SF: write failure at %x\n",
+ addr);
+ return -1;
+ }
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
+ (unsigned) (addr - start), start);
+ return 0;
+}
+
+
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ int ret;
+
+ if (cntlr.revision != 9) {
+ printk(BIOS_WARNING, "SF: Unsupported revision %x\n",
+ cntlr.revision);
+ return NULL;
+ }
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printk(BIOS_WARNING, "SF: Failed to set up slave\n");
+ free (flash);
+ return NULL;
+ }
+
+ spi->rw = SPI_READ_FLAG;
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret);
+ free (flash);
+ return NULL;
+ }
+
+ flash->spi = spi;
+ flash->name = "Opaque HW-sequencing";
+
+ flash->write = ich_hwseq_write;
+ flash->erase = ich_hwseq_erase;
+ flash->read = ich_hwseq_read;
+ switch ((cntlr.hsfs >> 3) & 3)
+ {
+ case 0:
+ flash->sector_size = 256;
+ break;
+ case 1:
+ flash->sector_size = 4096;
+ break;
+ case 2:
+ flash->sector_size = 8192;
+ break;
+ case 3:
+ flash->sector_size = 65536;
+ break;
+ }
+
+ uint32_t flcomp;
+
+ writel_ (0x1000, &cntlr.ich9_spi->fdoc);
+ flcomp = readl_(&cntlr.ich9_spi->fdod);
+
+ flash->size = 1 << (19 + (flcomp & 7));
+
+ if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
+ flash->size += 1 << (19 + ((flcomp >> 3) & 7));
+ printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
+
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
+ printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
+ flash->name, flash->sector_size, flash->size);
+
+ spi_release_bus(spi);
+
+ return flash;
+}
1
0
05 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4614
-gerrit
commit 92eb1adbf8eced368f72df35deb01bb4d2e7bf85
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Jan 5 00:51:12 2014 +0100
X230: current tree as-is.
Known issues:
- No keyboard backlight (thinklight works)
- No S3
- EHCI output sometimes get "stuck" until key is pressed after sysagent execution.
- no S3
- MRC fails if MRC cache is supplied. For now MRC cache is disabled.
- MRC sometimes hangs with message:
System Agent: Initializing PCH
{433e0f9f-05ae-410a-a0c3-bf298ecb2
So a watchdog is reenabled to reboot if this happens
Not tested:
- ultranav
- fingerprint
- dock
Change-Id: Ida1374b8c7f99da7d2415b33c33ccc2c270a2282
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/arch/x86/boot/smbios.c | 7 +-
src/drivers/spi/eon.c | 9 +
src/ec/acpi/ec.c | 2 +
src/mainboard/lenovo/Kconfig | 10 +
src/mainboard/lenovo/x201/Makefile.inc | 1 +
src/mainboard/lenovo/x201/dsdt.asl.orig | 94 ++++++
src/mainboard/lenovo/x201/smihandler.c.orig | 210 +++++++++++++
src/mainboard/lenovo/x201/smihandler.c.rej | 15 +
src/mainboard/lenovo/x230/Kconfig | 62 ++++
src/mainboard/lenovo/x230/Makefile.inc | 20 ++
src/mainboard/lenovo/x230/acpi/ec.asl | 26 ++
src/mainboard/lenovo/x230/acpi/mainboard.asl | 0
src/mainboard/lenovo/x230/acpi/platform.asl | 74 +++++
.../lenovo/x230/acpi/sandybridge_pci_irqs.asl | 65 ++++
src/mainboard/lenovo/x230/acpi/superio.asl | 1 +
src/mainboard/lenovo/x230/acpi/video.asl | 115 +++++++
src/mainboard/lenovo/x230/acpi_tables.c | 271 ++++++++++++++++
src/mainboard/lenovo/x230/cmos.layout | 141 +++++++++
src/mainboard/lenovo/x230/devicetree.cb | 140 +++++++++
src/mainboard/lenovo/x230/dsdt.asl | 59 ++++
src/mainboard/lenovo/x230/ec.c | 29 ++
src/mainboard/lenovo/x230/ec.h | 31 ++
src/mainboard/lenovo/x230/fadt.c | 159 ++++++++++
src/mainboard/lenovo/x230/gpio.h | 304 ++++++++++++++++++
src/mainboard/lenovo/x230/hda_verb.h | 266 ++++++++++++++++
src/mainboard/lenovo/x230/mainboard.c | 186 +++++++++++
src/mainboard/lenovo/x230/onboard.h | 36 +++
src/mainboard/lenovo/x230/romstage.c | 324 +++++++++++++++++++
src/mainboard/lenovo/x230/smi.h | 0
src/mainboard/lenovo/x230/smihandler.c | 174 +++++++++++
src/mainboard/lenovo/x230/thermal.h | 31 ++
src/northbridge/intel/sandybridge/acpi/igd.asl | 17 +
src/northbridge/intel/sandybridge/mrccache.c | 16 +-
src/northbridge/intel/sandybridge/raminit.c | 8 +-
src/southbridge/intel/bd82x6x/pch.h | 8 +
src/southbridge/intel/bd82x6x/spi.c | 347 ++++++++++++++++++++-
src/southbridge/intel/ibexpeak/pch.h | 8 +
src/southbridge/intel/ibexpeak/spi.c | 347 ++++++++++++++++++++-
38 files changed, 3599 insertions(+), 14 deletions(-)
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index 65bf538..25bdb37 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -130,12 +130,15 @@ static int smbios_write_type0(unsigned long *current, int handle)
t->vendor = smbios_add_string(t->eos, "coreboot");
#if !CONFIG_CHROMEOS
+#ifndef CONFIG_VENDOR_VERSION
+#define CONFIG_VENDOR_VERSION ""
+#endif
t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
if (strlen(CONFIG_LOCALVERSION))
- t->bios_version = smbios_add_string(t->eos, CONFIG_LOCALVERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION CONFIG_LOCALVERSION);
else
- t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION COREBOOT_VERSION);
#else
#define SPACES \
" "
diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c
index 21103ae..5a74b84 100644
--- a/src/drivers/spi/eon.c
+++ b/src/drivers/spi/eon.c
@@ -21,6 +21,7 @@
#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */
#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */
+#define EON_ID_EN25Q64 0x17
#define EON_ID_EN25Q128 0x18
struct eon_spi_flash_params {
@@ -52,6 +53,14 @@ static const struct eon_spi_flash_params eon_spi_flash_table[] = {
.nr_sectors = 4096,
.name = "EN25Q128",
},
+ {
+ .idcode1 = EON_ID_EN25Q64,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_sectors = 2048,
+ .name = "EN25Q64",
+ },
};
static int eon_write(struct spi_flash *flash,
diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
index ab287d6..3b984c4 100644
--- a/src/ec/acpi/ec.c
+++ b/src/ec/acpi/ec.c
@@ -104,6 +104,8 @@ u8 recv_ec_data(void)
// return -1;
}
+ udelay(10);
+
data = inb(ec_data_reg);
printk(BIOS_SPEW, "recv_ec_data: 0x%02x\n", data);
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index de9d56f..21413fc 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -17,6 +17,11 @@ config BOARD_LENOVO_X201
help
Lenovo X201 laptop. Consult wiki for details.
+config BOARD_LENOVO_X230
+ bool "ThinkPad X230"
+ help
+ Lenovo X230 laptop. Consult wiki for details.
+
config BOARD_LENOVO_T60
bool "ThinkPad T60 / T60p"
help
@@ -29,10 +34,15 @@ endchoice
source "src/mainboard/lenovo/x60/Kconfig"
source "src/mainboard/lenovo/x201/Kconfig"
+source "src/mainboard/lenovo/x230/Kconfig"
source "src/mainboard/lenovo/t60/Kconfig"
config MAINBOARD_VENDOR
string
default "Lenovo"
+config VENDOR_VERSION
+ string
+ default "CBET4000 "
+
endif # VENDOR_LENOVO
diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc
index 9055c9e..285e0d0 100644
--- a/src/mainboard/lenovo/x201/Makefile.inc
+++ b/src/mainboard/lenovo/x201/Makefile.inc
@@ -18,6 +18,7 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += dock.c
ramstage-y += dock.c
ramstage-y += gma.c
diff --git a/src/mainboard/lenovo/x201/dsdt.asl.orig b/src/mainboard/lenovo/x201/dsdt.asl.orig
new file mode 100644
index 0000000..ca47b13
--- /dev/null
+++ b/src/mainboard/lenovo/x201/dsdt.asl.orig
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20130325 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ #include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ #include "acpi/mainboard.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/nehalem/acpi/nehalem.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ Device (UNCR)
+ {
+ Name (_BBN, 0xFF)
+ Name (_ADR, 0x00)
+ Name (RID, 0x00)
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x00FF, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ Device (SAD)
+ {
+ Name (_ADR, 0x01)
+ Name (RID, 0x00)
+ OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
+ Field (SADC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x40),
+ PAM0, 8,
+ PAM1, 8,
+ PAM2, 8,
+ PAM3, 8,
+ PAM4, 8,
+ PAM5, 8,
+ PAM6, 8
+ }
+ }
+ }
+ }
+
+ #include "acpi/video.asl"
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+
+ // Dock support code
+ #include "acpi/dock.asl"
+}
diff --git a/src/mainboard/lenovo/x201/smihandler.c.orig b/src/mainboard/lenovo/x201/smihandler.c.orig
new file mode 100644
index 0000000..2558a9e
--- /dev/null
+++ b/src/mainboard/lenovo/x201/smihandler.c.orig
@@ -0,0 +1,210 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/ibexpeak/nvs.h"
+#include "southbridge/intel/ibexpeak/pch.h"
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include "dock.h"
+#include "smi.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+static void mainboard_smi_save_cmos(void)
+{
+ u8 val;
+ u8 tmp70, tmp72;
+
+ tmp70 = inb(0x70);
+ tmp72 = inb(0x72);
+
+ val = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);
+ set_option("tft_brightness", &val);
+ val = ec_read(H8_VOLUME_CONTROL);
+ set_option("volume", &val);
+
+ outb(tmp70, 0x70);
+ outb(tmp72, 0x72);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ case SMI_DOCK_CONNECT:
+ ec_clr_bit(0x03, 2);
+ udelay(250000);
+ if (!dock_connect()) {
+ ec_set_bit(0x03, 2);
+ /* set dock LED to indicate status */
+ ec_write(0x0c, 0x09);
+ ec_write(0x0c, 0x88);
+ } else {
+ /* blink dock LED to indicate failure */
+ ec_write(0x0c, 0x08);
+ ec_write(0x0c, 0xc9);
+ }
+ break;
+
+ case SMI_DOCK_DISCONNECT:
+ ec_clr_bit(0x03, 2);
+ dock_disconnect();
+ break;
+
+ case SMI_SAVE_CMOS:
+ mainboard_smi_save_cmos();
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
+ (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch (event) {
+ /* brightness up */
+ case 0x14:
+ mainboard_smi_brightness_up();
+ mainboard_smi_save_cmos();
+ break;
+ /* brightness down */
+ case 0x15:
+ mainboard_smi_brightness_down();
+ mainboard_smi_save_cmos();
+ break;
+ /* Fn-F9 key */
+ case 0x18:
+ /* Power loss */
+ case 0x27:
+ /* Undock Key */
+ case 0x50:
+ mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
+ break;
+ /* Dock Event */
+ case 0x37:
+ case 0x58:
+ mainboard_io_trap_handler(SMI_DOCK_CONNECT);
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << 12))
+ mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ u8 tmp;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
+ data);
+
+ if (!pmbase)
+ return 0;
+
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route H8SCI to SCI */
+ outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x02;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route H8SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/lenovo/x201/smihandler.c.rej b/src/mainboard/lenovo/x201/smihandler.c.rej
new file mode 100644
index 0000000..f52c463
--- /dev/null
+++ b/src/mainboard/lenovo/x201/smihandler.c.rej
@@ -0,0 +1,15 @@
+--- src/mainboard/lenovo/x201/smihandler.c
++++ src/mainboard/lenovo/x201/smihandler.c
+@@ -109,12 +109,10 @@
+ case 0x14:
+ /* brightness up */
+ mainboard_smi_brightness_up();
+- mainboard_smi_save_cmos();
+ break;
+ case 0x15:
+ /* brightness down */
+ mainboard_smi_brightness_down();
+- mainboard_smi_save_cmos();
+ break;
+ case 0x18:
+ /* Fn-F9 key */
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
new file mode 100644
index 0000000..ed6f028
--- /dev/null
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -0,0 +1,62 @@
+if BOARD_LENOVO_X230
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select EC_LENOVO_PMH7
+ select EC_LENOVO_H8
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_SMI_HANDLER
+ select GFXUMA
+ select EARLY_CBMEM_INIT
+
+ # Workaround for EC/KBC IRQ1.
+ select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+ string
+ default lenovo/x230
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "2325TLU"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x17aa
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x21fa
+
+config MAINBOARD_VENDOR
+ string
+ default "LENOVO"
+
+endif # BOARD_LENOVO_X230
diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc
new file mode 100644
index 0000000..d514d4b
--- /dev/null
+++ b/src/mainboard/lenovo/x230/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/lenovo/x230/acpi/ec.asl b/src/mainboard/lenovo/x230/acpi/ec.asl
new file mode 100644
index 0000000..4b3e72c
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+}
diff --git a/src/mainboard/lenovo/x230/acpi/mainboard.asl b/src/mainboard/lenovo/x230/acpi/mainboard.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl
new file mode 100644
index 0000000..73478ea
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/platform.asl
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* Not implemented. */
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..ba725ac
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
+ Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
+ Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
+ Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
+ Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/lenovo/x230/acpi/superio.asl b/src/mainboard/lenovo/x230/acpi/superio.asl
new file mode 100644
index 0000000..a2657f1
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/superio.asl
@@ -0,0 +1 @@
+#include "../../../../drivers/pc80/ps2_controller.asl"
diff --git a/src/mainboard/lenovo/x230/acpi/video.asl b/src/mainboard/lenovo/x230/acpi/video.asl
new file mode 100644
index 0000000..12a268b
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/video.asl
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org>
+ * Copyright (c) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+
+Scope (\_SB.PCI0.GFX0)
+{
+ Device (LCD0)
+ {
+ Name (_ADR, 0x0400)
+ Name (BRCT, 0)
+
+ Name (BRIG, Package (0x12)
+ {
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (_BCL, 0, NotSerialized)
+ {
+ Store (1, BRCT)
+ Return (BRIG)
+ }
+
+ Method (_BCM, 1, NotSerialized)
+ {
+ Store (ShiftLeft (Arg0, 4), ^^BCLV)
+ Store (0x80000000, ^^CR1)
+ Store (0x061a061a, ^^CR2)
+ }
+ Method (_BQC, 0, NotSerialized)
+ {
+ Store (^^BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
+ }
+
+ Method(BRID, 1, NotSerialized)
+ {
+ Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
+ If (LEqual (Local0, Ones))
+ {
+ Return (0x11)
+ }
+ Return (Local0)
+ }
+
+ /* Using Notify is the right way. But Windows doesn't handle
+ it well. So use both method in a way to avoid double action.
+ */
+ Method (DECB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x87)
+ } Else {
+ Store (BRID (_BQC ()), Local0)
+ If (LNotEqual (Local0, 2))
+ {
+ Decrement (Local0)
+ }
+ _BCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+ Method (INCB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x86)
+ } Else {
+ Store (BRID (_BQC ()), Local0)
+ If (LNotEqual (Local0, 0x11))
+ {
+ Increment (Local0)
+ }
+ _BCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c
new file mode 100644
index 0000000..95b45db
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi_tables.c
@@ -0,0 +1,271 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ /* EC handles all thermal and fan control on Butterfly. */
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* CBMEM TOC */
+ gnvs->cmem = (u32)get_cbmem_toc();
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+ // TODO: MLR
+ // The firmware read/write status is a "virtual" switch and
+ // will be handled elsewhere. Until then hard-code to
+ // read/write instead of read-only for developer mode.
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RW;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+#if CONFIG_CHROMEOS
+ // TODO(reinauer) this could move elsewhere?
+ chromeos_init_vboot(&(gnvs->chromeos));
+#endif
+
+ acpi_update_thermal_table(gnvs);
+
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+ "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ /* And tell SMI about it */
+ smm_setup_structures((void *)current, NULL, NULL);
+
+ current += sizeof(global_nvs_t);
+ ALIGN_CURRENT;
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout
new file mode 100644
index 0000000..de8b182
--- /dev/null
+++ b/src/mainboard/lenovo/x230/cmos.layout
@@ -0,0 +1,141 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: EC
+411 1 e 8 first_battery
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 touchpad
+
+#415 569 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
new file mode 100644
index 0000000..94b5839
--- /dev/null
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -0,0 +1,140 @@
+chip northbridge/intel/sandybridge
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
+ register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
+ register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
+ register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ # Coordinate with HW_ALL
+ register "pstate_coord_type" = "0xfe"
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpi1_routing" = "2"
+ register "gpi8_routing" = "2"
+
+ register "ide_legacy_combined" = "0x0"
+ register "sata_ahci" = "0x1"
+ # Enable SATA ports 0 & 1
+ register "sata_port_map" = "0x3"
+ # Set max SATA speed to 3.0 Gb/s
+ register "sata_interface_speed_support" = "0x2"
+
+ register "gen1_dec" = "0x7c1601"
+ register "gen2_dec" = "0x0c15e1"
+ register "gen4_dec" = "0x0c06a1"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug)
+ device pci 1c.1 on end # PCIe Port #2 (ETH0)
+ device pci 1c.2 on end # PCIe Port #3 (Card Reader)
+ #force ASPM for PCIe bridge to Card Reader
+ register "pcie_aspm_f2" = "0x3"
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on #LPC bridge
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
+ end
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ end
+
+ chip ec/lenovo/h8
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+
+ register "config0" = "0xa6"
+ register "config1" = "0x09"
+ register "config2" = "0xa0"
+ register "config3" = "0xe0"
+
+ register "beepmask0" = "0x00"
+ register "beepmask1" = "0x86"
+
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xd0"
+ register "event5_enable" = "0xfc"
+ register "event6_enable" = "0x00"
+ register "event7_enable" = "0x01"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventa_enable" = "0x01"
+ register "eventb_enable" = "0x00"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x0d"
+
+ register "wlan_enable" = "0x01"
+ register "trackpoint_enable" = "0x03"
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl
new file mode 100644
index 0000000..5688f63
--- /dev/null
+++ b/src/mainboard/lenovo/x230/dsdt.asl
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define THINKPAD_EC_GPE 17
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+
+ #include "acpi/video.asl"
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/x230/ec.c b/src/mainboard/lenovo/x230/ec.c
new file mode 100644
index 0000000..96716a4
--- /dev/null
+++ b/src/mainboard/lenovo/x230/ec.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+
+void butterfly_ec_init(void)
+{
+ printk(BIOS_DEBUG, "Butterfly EC Init\n");
+
+
+}
diff --git a/src/mainboard/lenovo/x230/ec.h b/src/mainboard/lenovo/x230/ec.h
new file mode 100644
index 0000000..5bbbd5a
--- /dev/null
+++ b/src/mainboard/lenovo/x230/ec.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_EC_H
+#define BUTTERFLY_EC_H
+
+#define EC_SCI_GPI 13 /* GPIO13 is EC_SCI# */
+
+/* EC SMI sources TODO: MLR- make defines */
+
+#ifndef __ACPI__
+extern void butterfly_ec_init(void);
+#endif
+
+#endif // BUTTERFLY_EC_H
diff --git a/src/mainboard/lenovo/x230/fadt.c b/src/mainboard/lenovo/x230/fadt.c
new file mode 100644
index 0000000..0ce3c72
--- /dev/null
+++ b/src/mainboard/lenovo/x230/fadt.c
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+ 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 16;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 101; /* c2 not supported */
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD |
+ ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 128;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/lenovo/x230/gpio.h b/src/mainboard/lenovo/x230/gpio.h
new file mode 100644
index 0000000..b592e6a
--- /dev/null
+++ b/src/mainboard/lenovo/x230/gpio.h
@@ -0,0 +1,304 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_GPIO_H
+#define BUTTERFLY_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NONE, /* Unused */
+ .gpio1 = GPIO_MODE_NONE, /* Unused */
+ .gpio2 = GPIO_MODE_NONE, /* Unused */
+ .gpio3 = GPIO_MODE_NONE, /* Unused */
+ .gpio4 = GPIO_MODE_NATIVE, /* Native - TPSINT# for TP SMBus IRQ */
+ .gpio5 = GPIO_MODE_NONE, /* Unused */
+ .gpio6 = GPIO_MODE_GPIO, /* Input - BOARD_ID4 */
+ .gpio7 = GPIO_MODE_GPIO, /* Input - BOARD_ID5 */
+ .gpio8 = GPIO_MODE_GPIO, /* Output - BT on/off */
+ .gpio9 = GPIO_MODE_NONE, /* Unused */
+ .gpio10 = GPIO_MODE_NONE, /* Unused */
+ .gpio11 = GPIO_MODE_GPIO, /* Input - TP WAKEUP Event */
+ .gpio12 = GPIO_MODE_NONE, /* Unused */
+ .gpio13 = GPIO_MODE_GPIO, /* Input - SCI from EC */
+ .gpio14 = GPIO_MODE_GPIO, /* Output - AOAC WLAN power control */
+ .gpio15 = GPIO_MODE_GPIO, /* Unused - Do not control WLAN*/
+ .gpio16 = GPIO_MODE_NONE, /* Unused */
+ .gpio17 = GPIO_MODE_GPIO, /* Input - DGPU_PWROK */
+ .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin*/
+ .gpio19 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 0 */
+ .gpio20 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ2# SDCard clock pin */
+ .gpio21 = GPIO_MODE_GPIO, /* Input - EC_ENTERING_RW for Google OS */
+ .gpio22 = GPIO_MODE_GPIO, /* Input - BIOS RECOVERY */
+ .gpio23 = GPIO_MODE_NONE, /* Unused */
+ .gpio24 = GPIO_MODE_GPIO, /* Output - DGPU_HOLD_RST# */
+ .gpio25 = GPIO_MODE_NONE, /* Unused */
+ .gpio26 = GPIO_MODE_NONE, /* Unused */
+ .gpio27 = GPIO_MODE_NONE, /* Unused */
+ .gpio28 = GPIO_MODE_NONE, /* Unused */
+ .gpio29 = GPIO_MODE_NONE, /* Unused */
+ .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# */
+ .gpio31 = GPIO_MODE_NONE, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT, /* Unused */
+ .gpio1 = GPIO_DIR_INPUT, /* Unused */
+ .gpio2 = GPIO_DIR_INPUT, /* Unused */
+ .gpio3 = GPIO_DIR_INPUT, /* Unused */
+ .gpio4 = GPIO_DIR_INPUT, /* Native */
+ .gpio5 = GPIO_DIR_INPUT, /* Unused */
+ .gpio6 = GPIO_DIR_INPUT, /* Input */
+ .gpio7 = GPIO_DIR_INPUT, /* Input */
+ .gpio8 = GPIO_DIR_INPUT, /* Output HIGH - set in mainboard.c */
+ .gpio9 = GPIO_DIR_INPUT, /* Unused */
+ .gpio10 = GPIO_DIR_INPUT, /* Unused */
+ .gpio11 = GPIO_DIR_INPUT, /* Input */
+ .gpio12 = GPIO_DIR_INPUT, /* Unused */
+ .gpio13 = GPIO_DIR_INPUT, /* Input */
+ .gpio14 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio15 = GPIO_DIR_INPUT, /* Unused */
+ .gpio16 = GPIO_DIR_INPUT, /* Unused */
+ .gpio17 = GPIO_DIR_INPUT, /* Input */
+ .gpio18 = GPIO_DIR_INPUT, /* Native */
+ .gpio19 = GPIO_DIR_INPUT, /* Input */
+ .gpio20 = GPIO_DIR_INPUT, /* Native */
+ .gpio21 = GPIO_DIR_INPUT, /* Input */
+ .gpio22 = GPIO_DIR_INPUT, /* Input */
+ .gpio23 = GPIO_DIR_INPUT, /* Unused */
+ .gpio24 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio25 = GPIO_DIR_INPUT, /* Unused */
+ .gpio26 = GPIO_DIR_INPUT, /* Unused */
+ .gpio27 = GPIO_DIR_INPUT, /* Unused */
+ .gpio28 = GPIO_DIR_INPUT, /* Unused */
+ .gpio29 = GPIO_DIR_INPUT, /* Unused */
+ .gpio30 = GPIO_DIR_INPUT, /* Native */
+ .gpio31 = GPIO_DIR_INPUT, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio1 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio2 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio3 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio4 = GPIO_LEVEL_LOW, /* Native */
+ .gpio5 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio6 = GPIO_LEVEL_LOW, /* Input */
+ .gpio7 = GPIO_LEVEL_LOW, /* Input */
+ .gpio8 = GPIO_LEVEL_HIGH, /* Output HIGH - set in mainboard.c */
+ .gpio9 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio10 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio11 = GPIO_LEVEL_LOW, /* Input */
+ .gpio12 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio13 = GPIO_LEVEL_LOW, /* Input */
+ .gpio14 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio15 = GPIO_LEVEL_HIGH, /* Unused */
+ .gpio16 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio17 = GPIO_LEVEL_LOW, /* Input */
+ .gpio18 = GPIO_LEVEL_LOW, /* Native */
+ .gpio19 = GPIO_LEVEL_LOW, /* Input */
+ .gpio20 = GPIO_LEVEL_LOW, /* Native */
+ .gpio21 = GPIO_LEVEL_LOW, /* Input */
+ .gpio22 = GPIO_LEVEL_LOW, /* Input */
+ .gpio23 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio24 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio25 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio26 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio27 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio28 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio29 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio30 = GPIO_LEVEL_LOW, /* Native */
+ .gpio31 = GPIO_LEVEL_LOW, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */
+ .gpio13 = GPIO_INVERT, /* invert EC SCI pin */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */
+ .gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */
+ .gpio34 = GPIO_MODE_NONE, /* Unused */
+ .gpio35 = GPIO_MODE_NONE, /* Unused */
+ .gpio36 = GPIO_MODE_GPIO, /* Output - DGPU_PWR_EN */
+ .gpio37 = GPIO_MODE_GPIO, /* Input - FDI TERM / VOLTAGE OVERRIDE */
+ .gpio38 = GPIO_MODE_GPIO, /* Input - MFG_MODE test */
+ .gpio39 = GPIO_MODE_GPIO, /* Input - DGPU_PRSNT */
+ .gpio40 = GPIO_MODE_NONE, /* Unused */
+ .gpio41 = GPIO_MODE_NONE, /* Unused */
+ .gpio42 = GPIO_MODE_NONE, /* Unused */
+ .gpio43 = GPIO_MODE_NONE, /* Unused */
+ .gpio44 = GPIO_MODE_GPIO, /* Input - BOARD_ID0 */
+ .gpio45 = GPIO_MODE_GPIO, /* Input - BOARD_ID1 */
+ .gpio46 = GPIO_MODE_GPIO, /* Input - BOARD_ID2 */
+ .gpio47 = GPIO_MODE_NATIVE, /* Native - PEGA_GPU clock request */
+ .gpio48 = GPIO_MODE_NONE, /* Unused */
+ .gpio49 = GPIO_MODE_NONE, /* Unused */
+ .gpio50 = GPIO_MODE_NONE, /* Unused */
+ .gpio51 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 1 */
+ .gpio52 = GPIO_MODE_GPIO, /* Input - Google recovery, Pull up +3V */
+ .gpio53 = GPIO_MODE_GPIO, /* Output - G Sensor LED */
+ .gpio54 = GPIO_MODE_GPIO, /* Input - Google Development */
+ .gpio55 = GPIO_MODE_GPIO, /* Input - Top-Block Swap Override */
+ .gpio56 = GPIO_MODE_NONE, /* Unused */
+ .gpio57 = GPIO_MODE_GPIO, /* Input - SV_DET */
+ .gpio58 = GPIO_MODE_NONE, /* Unused */
+ .gpio59 = GPIO_MODE_NONE, /* Unused */
+ .gpio60 = GPIO_MODE_NONE, /* GPO - DRAMRST_CNTRL_PCH */
+ .gpio61 = GPIO_MODE_NONE, /* Unused */
+ .gpio62 = GPIO_MODE_NATIVE, /* Native - Connect to EC 32.768KHz */
+ .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT, /* Native */
+ .gpio33 = GPIO_DIR_INPUT, /* Input */
+ .gpio34 = GPIO_DIR_INPUT, /* Unused */
+ .gpio35 = GPIO_DIR_INPUT, /* Unused */
+ .gpio36 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio37 = GPIO_DIR_INPUT, /* Input */
+ .gpio38 = GPIO_DIR_INPUT, /* Input */
+ .gpio39 = GPIO_DIR_INPUT, /* Input */
+ .gpio40 = GPIO_DIR_INPUT, /* Unused */
+ .gpio41 = GPIO_DIR_INPUT, /* Unused */
+ .gpio42 = GPIO_DIR_INPUT, /* Unused */
+ .gpio43 = GPIO_DIR_INPUT, /* Unused */
+ .gpio44 = GPIO_DIR_INPUT, /* Input */
+ .gpio45 = GPIO_DIR_INPUT, /* Input */
+ .gpio46 = GPIO_DIR_INPUT, /* Input */
+ .gpio47 = GPIO_DIR_INPUT, /* Native */
+ .gpio48 = GPIO_DIR_INPUT, /* Unused */
+ .gpio49 = GPIO_DIR_INPUT, /* Unused */
+ .gpio50 = GPIO_DIR_INPUT, /* Unused */
+ .gpio51 = GPIO_DIR_INPUT, /* Input */
+ .gpio52 = GPIO_DIR_INPUT, /* Input */
+ .gpio53 = GPIO_DIR_OUTPUT, /* Input */
+ .gpio54 = GPIO_DIR_INPUT, /* Input */
+ .gpio55 = GPIO_DIR_INPUT, /* Input */
+ .gpio56 = GPIO_DIR_INPUT, /* Unused */
+ .gpio57 = GPIO_DIR_INPUT, /* Input */
+ .gpio58 = GPIO_DIR_INPUT, /* Unused */
+ .gpio59 = GPIO_DIR_INPUT, /* Unused */
+ .gpio60 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio61 = GPIO_DIR_INPUT, /* Unused */
+ .gpio62 = GPIO_DIR_INPUT, /* Native */
+ .gpio63 = GPIO_DIR_INPUT, /* Native */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_LOW, /* Native */
+ .gpio33 = GPIO_LEVEL_LOW, /* Input */
+ .gpio34 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio35 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio36 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio37 = GPIO_LEVEL_LOW, /* Input */
+ .gpio38 = GPIO_LEVEL_LOW, /* Input */
+ .gpio39 = GPIO_LEVEL_LOW, /* Input */
+ .gpio40 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio41 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio42 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio43 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio44 = GPIO_LEVEL_LOW, /* Input */
+ .gpio45 = GPIO_LEVEL_LOW, /* Input */
+ .gpio46 = GPIO_LEVEL_LOW, /* Input */
+ .gpio47 = GPIO_LEVEL_LOW, /* Native */
+ .gpio48 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio49 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio50 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio51 = GPIO_LEVEL_LOW, /* Input */
+ .gpio52 = GPIO_LEVEL_LOW, /* Input */
+ .gpio53 = GPIO_LEVEL_HIGH, /* Input */
+ .gpio54 = GPIO_LEVEL_LOW, /* Input */
+ .gpio55 = GPIO_LEVEL_LOW, /* Input */
+ .gpio56 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio57 = GPIO_LEVEL_LOW, /* Input */
+ .gpio58 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio59 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio60 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio61 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio62 = GPIO_LEVEL_LOW, /* Native */
+ .gpio63 = GPIO_LEVEL_LOW, /* Native */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NONE, /* Unused */
+ .gpio65 = GPIO_MODE_NONE, /* Unused */
+ .gpio66 = GPIO_MODE_NONE, /* Unused */
+ .gpio67 = GPIO_MODE_NONE, /* Unused */
+ .gpio68 = GPIO_MODE_GPIO, /* Input - DGPU_PWR_EN */
+ .gpio69 = GPIO_MODE_NONE, /* Unused */
+ .gpio70 = GPIO_MODE_NONE, /* Unused */
+ .gpio71 = GPIO_MODE_NONE, /* Unused */
+ .gpio72 = GPIO_MODE_NONE, /* Unused */
+ .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# WLAN clock request */
+ .gpio74 = GPIO_MODE_NONE, /* Unused */
+ .gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT, /* Unused */
+ .gpio65 = GPIO_DIR_INPUT, /* Unused */
+ .gpio66 = GPIO_DIR_INPUT, /* Unused */
+ .gpio67 = GPIO_DIR_INPUT, /* Unused */
+ .gpio68 = GPIO_DIR_INPUT, /* Input */
+ .gpio69 = GPIO_DIR_INPUT, /* Unused */
+ .gpio70 = GPIO_DIR_INPUT, /* Unused */
+ .gpio71 = GPIO_DIR_INPUT, /* Unused */
+ .gpio72 = GPIO_DIR_INPUT, /* Unused */
+ .gpio73 = GPIO_DIR_INPUT, /* Native */
+ .gpio74 = GPIO_DIR_INPUT, /* Unused */
+ .gpio75 = GPIO_DIR_INPUT, /* Input */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio65 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio66 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio67 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio68 = GPIO_LEVEL_LOW, /* Input */
+ .gpio69 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio70 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio71 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio72 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio73 = GPIO_LEVEL_LOW, /* Native */
+ .gpio74 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio75 = GPIO_LEVEL_LOW, /* Input */
+};
+
+const struct pch_gpio_map butterfly_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+#endif
diff --git a/src/mainboard/lenovo/x230/hda_verb.h b/src/mainboard/lenovo/x230/hda_verb.h
new file mode 100644
index 0000000..7d22897
--- /dev/null
+++ b/src/mainboard/lenovo/x230/hda_verb.h
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Vendor Name : IDT
+ * Vendor ID : 0x111d76e5
+ * Subsystem ID : 0x103c18f9
+ * Revision ID : 0x100303
+ */
+
+
+static const u32 mainboard_cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC
+ 0x17aa21fa, // Subsystem ID
+ 0x00000073, // Number of 4 dword sets
+
+/* Bits 31:28 - Codec Address */
+/* Bits 27:20 - NID */
+/* Bits 19:8 - Verb ID */
+/* Bits 7:0 - Payload */
+
+/* NID 0x01 - NodeInfo */
+ 0x001720F9,
+ 0x00172118,
+ 0x0017223C,
+ 0x00172310,
+
+/* NID 0x0A - External Microphone Connector
+ * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
+ */
+ 0x00A71C20,
+ 0x00A71D10,
+ 0x00A71EA1,
+ 0x00A71F04,
+
+/* NID 0x0B - Headphone Connector
+ * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
+ */
+ 0x00B71C1F,
+ 0x00B71D10,
+ 0x00B71E21,
+ 0x00B71F04,
+
+/* NID 0x0C - Not connected
+ * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
+ */
+ 0x00C71CF0,
+ 0x00C71D00,
+ 0x00C71EF0,
+ 0x00C71F40,
+
+/* NID 0x0D - Internal Speakers
+ * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
+ */
+ 0x00D71C10,
+ 0x00D71D01,
+ 0x00D71E17,
+ 0x00D71F90,
+
+/* NID 0x0F - Not connected
+ * Config=0x40F000F0
+ */
+ 0x00F71CF0,
+ 0x00F71D00,
+ 0x00F71EF0,
+ 0x00F71F40,
+
+/* NID 0x11 - Internal Microphone
+ * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
+ */
+ 0x01171C40,
+ 0x01171D01,
+ 0x01171EA3,
+ 0x01171FD5,
+
+ /*
+ * Hardware EQ Parameters
+ * Sample Rate 88200
+ */
+ 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
+ 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80,
+ 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981,
+ 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80,
+ 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
+ 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80,
+ 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E,
+ 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80,
+ 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1,
+ 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80,
+ 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E,
+ 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80,
+ 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983,
+ 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80,
+ 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D,
+ 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80,
+ 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C,
+ 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80,
+ 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3,
+ 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80,
+ 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F,
+ 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80,
+ 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982,
+ 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80,
+ 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E,
+ 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80,
+ 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D,
+ 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80,
+ 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2,
+ 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80,
+ 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F,
+ 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80,
+ 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E,
+ 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80,
+ 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937,
+ 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80,
+ 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971,
+ 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80,
+ 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9,
+ 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80,
+ 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942,
+ 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80,
+ 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C,
+ 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80,
+ 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934,
+ 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80,
+ 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963,
+ 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80,
+ 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9,
+ 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80,
+ 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
+ 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80,
+
+ /*
+ * Hardware EQ Parameters
+ * Sample Rate 96000
+ */
+ 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
+ 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80,
+ 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981,
+ 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80,
+ 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
+ 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80,
+ 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E,
+ 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80,
+ 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1,
+ 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80,
+ 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E,
+ 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80,
+ 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983,
+ 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80,
+ 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D,
+ 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80,
+ 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C,
+ 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80,
+ 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3,
+ 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80,
+ 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F,
+ 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80,
+ 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982,
+ 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80,
+ 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E,
+ 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80,
+ 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D,
+ 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80,
+ 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1,
+ 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80,
+ 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F,
+ 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80,
+ 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D,
+ 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80,
+ 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938,
+ 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80,
+ 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972,
+ 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80,
+ 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8,
+ 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80,
+ 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941,
+ 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80,
+ 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999,
+ 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80,
+ 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934,
+ 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80,
+ 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966,
+ 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80,
+ 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9,
+ 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80,
+ 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
+ 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80,
+
+ /* SAFEDSP Parameters */
+ 0x022782C1, 0x02277127, 0x02277227, 0x02278801,
+ 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14,
+ 0x02278B0F, 0x0017B008,
+
+ /* Misc entries */
+ 0x00B707C0, /* Enable PortB as Output with HP amp */
+ 0x00D70740, /* Enable PortD as Output */
+ 0x0017A200, /* Disable ClkEn of PortSenseTst */
+ 0x0017C621, /* Slave Port - Port A used as microphone input for
+ combo Jack
+ Master Port - Port B used for Jack Presence Detect
+ Enable Combo Jack Detection */
+ 0x0017A208, /* Enable ClkEn of PortSenseTst */
+ 0x00170500, /* Set power state to D0 */
+
+ /* --- Next Codec --- */
+
+/* Vendor Name : Intel
+ * Vendor ID : 0x80862806
+ * Subsystem ID : 0x80860101
+ * Revision ID : 0x100000
+ */
+ /* coreboot specific header */
+ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of IDs
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ 0x30172001,
+ 0x30172101,
+ 0x30172286,
+ 0x30172380,
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ 0x30571c10,
+ 0x30571d00,
+ 0x30571e56,
+ 0x30571f18,
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ 0x30671c20,
+ 0x30671d00,
+ 0x30671e56,
+ 0x30671f18,
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ 0x30771c30,
+ 0x30771d00,
+ 0x30771e56,
+ 0x30771f18
+};
+
+static const u32 mainboard_pc_beep_verbs[] = {
+ 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
+};
+
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
+
+
diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c
new file mode 100644
index 0000000..b6b0b07
--- /dev/null
+++ b/src/mainboard/lenovo/x230/mainboard.c
@@ -0,0 +1,186 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+#include "ec.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <cbfs.h>
+#include <pc80/keyboard.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+ int res = 0;
+
+ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+ __func__, X86_AX);
+
+ switch (X86_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ X86_AX = 0x005f;
+ X86_CL = 0x00; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0001; /* Int-LVDS */
+ res = 1;
+ break;
+ case 0x5f70:
+ switch (X86_CH) {
+ case 0:
+ /* Get Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ X86_CH);
+ break;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+ break;
+ }
+ return res;
+}
+#endif
+
+const char *smbios_mainboard_version(void)
+{
+ return "Lenovo X230";
+}
+
+/* Audio Setup */
+
+extern const u32 *cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 *pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+
+}
+
+static void mainboard_init(device_t dev)
+{
+
+ /* This sneaked in here, because X201 SuperIO chip isn't really
+ connected to anything and hence we don't init it.
+ */
+ pc_keyboard_init(0);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+#if CONFIG_VGA_ROM_RUN
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+ verb_setup();
+}
+
+void h8_mainboard_init_dock (void);
+
+void h8_mainboard_init_dock (void)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/x230/onboard.h b/src/mainboard/lenovo/x230/onboard.h
new file mode 100644
index 0000000..e32e023
--- /dev/null
+++ b/src/mainboard/lenovo/x230/onboard.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_ONBOARD_H
+#define BUTTERFLY_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+/* uses 7-bit I2C address */
+/* must be set to edge triggered */
+#define BUTTERFLY_TRACKPAD_NAME "trackpad"
+#define BUTTERFLY_TRACKPAD_I2C_ADDR 0x67
+#define BUTTERFLY_TRACKPAD_IRQ 22 /* PIRQG - 22 Edge triggered */
+
+/* defines for programming the MAC address */
+#define BUTTERFLY_NIC_VENDOR_ID 0x10EC
+#define BUTTERFLY_NIC_DEVICE_ID 0x8136
+
+/* 0x00: White LINK LED and Amber ACTIVE LED */
+#define BUTTERFLY_NIC_LED_MODE 0x00
+#endif
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
new file mode 100644
index 0000000..1d1daf5
--- /dev/null
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <cbfs.h>
+
+static void pch_enable_lpc(void)
+{
+ /* X230 EC Decode Range Port60/64, Port62/66 */
+ /* Enable EC, PS/2 Keyboard/Mouse */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ COMA_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
+
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+
+ pci_write_config32(PCH_LPC_DEV, 0xac,
+ 0x80010000);
+}
+
+static void rcba_config(void)
+{
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P1IP WLAN INTA -> PIRQB
+ * D28IP_P2IP ETH0 INTB -> PIRQF
+ * D28IP_P3IP SDCARD INTC -> PIRQD
+ * D29IP_E1P EHCI1 INTA -> PIRQD
+ * D26IP_E2P EHCI2 INTA -> PIRQF
+ * D31IP_SIP SATA INTA -> PIRQB (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQH
+ * D31IP_TTIP THRT INTC -> PIRQA
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ *
+ * Trackpad interrupt is edge triggered and cannot be shared.
+ * TRACKPAD -> PIRQG
+
+ */
+
+ /* Device interrupt pin register (board specific) */
+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+ RCBA32(D29IP) = (INTA << D29IP_E1P);
+ RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
+ (INTC << D28IP_P3IP);
+ RCBA32(D27IP) = (INTA << D27IP_ZIP);
+ RCBA32(D26IP) = (INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+ /* Device interrupt route registers */
+ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+ DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+ DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
+ DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+ /* Enable IOAPIC (generic) */
+ RCBA16(OIC) = 0x0100;
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void) RCBA16(OIC);
+
+ /* Disable unused devices (board specific) */
+ RCBA32(FD) = 0x17f81fe3;
+ RCBA32(BUC) = 0;
+}
+
+void main(unsigned long bist)
+{
+ int boot_mode = 0;
+ int cbmem_was_initted;
+ u32 pm1_cnt;
+ u16 pm1_sts;
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ outb(0x6, 0xcf9);
+ hlt ();
+ }
+
+ struct pei_data pei_data = {
+ pei_version: PEI_VERSION,
+ mchbar: DEFAULT_MCHBAR,
+ dmibar: DEFAULT_DMIBAR,
+ epbar: DEFAULT_EPBAR,
+ pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+ smbusbar: SMBUS_IO_BASE,
+ wdbbar: 0x4000000,
+ wdbsize: 0x1000,
+ hpet_address: CONFIG_HPET_ADDRESS,
+ rcba: DEFAULT_RCBABASE,
+ pmbase: DEFAULT_PMBASE,
+ gpiobase: DEFAULT_GPIOBASE,
+ thermalbase: 0xfed08000,
+ system_type: 0, // 0 Mobile, 1 Desktop/Server
+ tseg_size: CONFIG_SMM_TSEG_SIZE,
+ spd_addresses: { 0xA0, 0x00,0xA2,0x00 },
+ ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+ ec_present: 1,
+ gbe_enable: 1,
+ ddr3lv_support: 0,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ dimm_channel0_disabled: 2,
+ dimm_channel1_disabled: 2,
+ max_ddr3_freq: 1600,
+ usb_port_config: {
+ /* enabled usb oc pin length */
+ { 1, 0, 0x0080 }, /* P0 */
+ { 1, 0, 0x0080 }, /* P1 */
+ { 1, 0, 0x0080 }, /* P3 */
+ { 1, 0, 0x0080 }, /* P4 */
+ { 1, 0, 0x0080 }, /* P5 */
+ { 1, 0, 0x0080 }, /* P6 */
+ { 1, 0, 0x0080 }, /* P7 */
+ { 1, 0, 0x0080 }, /* P8 */
+ { 1, 0, 0x0080 }, /* P9 */
+ { 1, 0, 0x0080 }, /* P10 */
+ { 1, 0, 0x0080 }, /* P11 */
+ { 1, 0, 0x0080 }, /* P12 */
+ { 1, 0, 0x0080 }, /* P13 */
+ { 1, 0, 0x0080 }, /* P14 */
+ { 1, 0, 0x0080 }, /* P15 */
+ },
+ ddr_refresh_rate_config: 2, /* Force double refresh rate */
+ };
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ if (bist == 0)
+ enable_lapic();
+
+
+ pch_enable_lpc();
+
+ /* Enable GPIOs */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+
+ // setup_pch_gpios(&butterfly_gpio_map);
+ outl (0x3962a5ff, DEFAULT_GPIOBASE | 0x0000);
+ outl (0x8ebf6aff, DEFAULT_GPIOBASE | 0x0004);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0008);
+ outl (0x66ff7efb, DEFAULT_GPIOBASE | 0x000c);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0010);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0014);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0018);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x001c);
+ outl (0x00080000, DEFAULT_GPIOBASE | 0x0020);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0024);
+ outw (0x0000, DEFAULT_GPIOBASE | 0x0028);
+ outw (0x0000, DEFAULT_GPIOBASE | 0x002a);
+ outl (0x00002042, DEFAULT_GPIOBASE | 0x002c);
+ outl (0x02ff08fe, DEFAULT_GPIOBASE | 0x0030);
+ outl (0x1f47f7fd, DEFAULT_GPIOBASE | 0x0034);
+ outl (0xbfffff43, DEFAULT_GPIOBASE | 0x0038);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x003c);
+ outl (0x000000ff, DEFAULT_GPIOBASE | 0x0040);
+ outl (0x00000fff, DEFAULT_GPIOBASE | 0x0044);
+ outl (0x00000fcf, DEFAULT_GPIOBASE | 0x0048);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x004c);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0050);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0054);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0058);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x005c);
+ outl (0x01000000, DEFAULT_GPIOBASE | 0x0060);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0064);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0068);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x006c);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0070);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0074);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0078);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x007c);
+
+ /* Initialize console device(s) */
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+ printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+ if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+ }
+
+ post_code(0x38);
+ /* Enable SPD ROMs and DDR-III DRAM */
+ enable_smbus();
+
+ /* Prepare USB controller early in S3 resume */
+ if (boot_mode == 2)
+ enable_usb_bar();
+
+ post_code(0x39);
+
+ post_code(0x3a);
+ pei_data.boot_mode = boot_mode;
+ timestamp_add_now(TS_BEFORE_INITRAM);
+
+ /* MRC.bin has a bug and sometimes halts (instead of reboot?).
+ */
+ if (boot_mode != 2)
+ {
+ RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */
+ outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */
+ }
+
+ sdram_initialize(&pei_data);
+
+ if (boot_mode != 2)
+ {
+ RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
+ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
+ }
+
+ timestamp_add_now(TS_AFTER_INITRAM);
+ post_code(0x3c);
+
+ rcba_config();
+ post_code(0x3d);
+
+ quick_ram_check();
+ post_code(0x3e);
+
+ MCHBAR16(SSKPD) = 0xCAFE;
+ cbmem_was_initted = !cbmem_initialize();
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+
+ *(u32 *)CBMEM_BOOT_MODE = 0;
+ *(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+ if ((boot_mode == 2) && cbmem_was_initted) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+ if (resume_backup_memory) {
+ *(u32 *)CBMEM_BOOT_MODE = boot_mode;
+ *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+ }
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ } else if (boot_mode == 2) {
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0x6, 0xcf9);
+ hlt();
+ } else {
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ }
+#endif
+ post_code(0x3f);
+#if CONFIG_CHROMEOS
+ init_chromeos(boot_mode);
+#endif
+ timestamp_add_now(TS_END_ROMSTAGE);
+}
diff --git a/src/mainboard/lenovo/x230/smi.h b/src/mainboard/lenovo/x230/smi.h
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c
new file mode 100644
index 0000000..ca92091
--- /dev/null
+++ b/src/mainboard/lenovo/x230/smihandler.c
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include "smi.h"
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
+ (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch (event) {
+ case 0x14:
+ /* brightness up */
+ mainboard_smi_brightness_up();
+ break;
+ case 0x15:
+ /* brightness down */
+ mainboard_smi_brightness_down();
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << 12))
+ mainboard_smi_handle_ec_sci();
+}
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ u8 tmp;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
+ data);
+
+ if (!pmbase)
+ return 0;
+
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route H8SCI to SCI */
+ outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x02;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route H8SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_FINALIZE:
+ printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/lenovo/x230/thermal.h b/src/mainboard/lenovo/x230/thermal.h
new file mode 100644
index 0000000..9657fe0
--- /dev/null
+++ b/src/mainboard/lenovo/x230/thermal.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_THERMAL_H
+#define BUTTERFLY_THERMAL_H
+
+/* Active Thermal and fans are controlled by the EC. */
+
+ /* Temperature which OS will shutdown at */
+ #define CRITICAL_TEMPERATURE 100
+
+ /* Temperature which OS will throttle CPU */
+ #define PASSIVE_TEMPERATURE 90
+
+#endif
diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl
index a6804ad..7d3d4db 100644
--- a/src/northbridge/intel/sandybridge/acpi/igd.asl
+++ b/src/northbridge/intel/sandybridge/acpi/igd.asl
@@ -23,6 +23,23 @@ Device (GFX0)
{
Name (_ADR, 0x00020000)
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ BAR0, 64
+ }
+
+ OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x48254),
+ BCLV, 16,
+ Offset (0xc8250),
+ CR1, 32,
+ CR2, 32
+ }
+
/* Display Output Switching */
Method (_DOS, 1)
{
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index e19d2c5..a13a971 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -34,8 +34,8 @@
#endif
/* convert a pointer to flash area into the offset inside the flash */
-static inline u32 to_flash_offset(void *p) {
- return ((u32)p + CONFIG_ROM_SIZE);
+static inline u32 to_flash_offset(struct spi_flash *flash, void *p) {
+ return ((u32)p + flash->size);
}
static struct mrc_data_container *next_mrc_block(
@@ -192,7 +192,12 @@ static void update_mrc_cache(void *unused)
// 1. use spi_flash_probe() to find the flash, then
spi_init();
- struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ struct spi_flash *flash = 0;
+
+ if (!spi_is_multichip ())
+ flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!flash)
+ flash = spi_flash_hwseq(0, 0, 1000000, SPI_MODE_3);
if (!flash) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
@@ -212,7 +217,7 @@ static void update_mrc_cache(void *unused)
"Need to erase the MRC cache region of %d bytes at %p\n",
cache_size, cache_base);
- flash->erase(flash, to_flash_offset(cache_base), cache_size);
+ flash->erase(flash, to_flash_offset(flash, cache_base), cache_size);
/* we will start at the beginning again */
cache = cache_base;
@@ -220,7 +225,7 @@ static void update_mrc_cache(void *unused)
// 4. write mrc data with flash->write()
printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n",
cache);
- flash->write(flash, to_flash_offset(cache),
+ flash->write(flash, to_flash_offset(flash, cache),
current->mrc_data_size + sizeof(*current), current);
}
@@ -232,6 +237,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = {
struct mrc_data_container *find_current_mrc_cache(void)
{
+ return NULL;
struct mrc_data_container *cache_base;
u32 cache_size;
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 333a6b5..3dab218 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -219,7 +219,7 @@ static void post_system_agent_init(struct pei_data *pei_data)
void sdram_initialize(struct pei_data *pei_data)
{
struct sys_info sysinfo;
- unsigned long entry;
+ int (*entry) (struct pei_data *pei_data) __attribute__ ((regparm(1)));
report_platform_info();
@@ -252,13 +252,11 @@ void sdram_initialize(struct pei_data *pei_data)
/* Locate and call UEFI System Agent binary. */
/* TODO make MRC blob (0xab?) defined in cbfs_core.h. */
- entry = (unsigned long)cbfs_get_file_content(
+ entry = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab);
if (entry) {
int rv;
- asm volatile (
- "call *%%ecx\n\t"
- :"=a" (rv) : "c" (entry), "a" (pei_data));
+ rv = entry (pei_data);
if (rv) {
switch (rv) {
case -1:
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 90de855..6382481 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -58,6 +58,14 @@ void intel_pch_finalize_smm(void);
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
+int spi_is_multichip(void);
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+#endif
+#endif
+
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
void pch_enable(device_t dev);
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index ec5d7de..959c29c 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
+ * Copyright (C) 2011 Stefan Tauner
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,11 +30,20 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci.h>
+#include <spi_flash.h>
#include <spi-generic.h>
+#include "pch.h"
#define min(a, b) ((a)<(b)?(a):(b))
+#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
+#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
+#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
+#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
+
+
#ifdef __SMM__
#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
@@ -115,7 +126,11 @@ typedef struct ich9_spi_regs {
typedef struct ich_spi_controller {
int locked;
+ int revision;
+ uint32_t flmap0;
+ uint32_t hsfs;
+ ich9_spi_regs *ich9_spi;
uint8_t *opmenu;
int menubytes;
uint16_t *preop;
@@ -356,6 +371,7 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
+ cntlr.revision = ich_version;
switch (ich_version) {
case 7:
{
@@ -381,7 +397,11 @@ void spi_init(void)
const uint16_t ich9_spibar_offset = 0x3800;
ich9_spi_regs *ich9_spi =
(ich9_spi_regs *)(rcrb + ich9_spibar_offset);
- ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ uint16_t hsfs;
+ cntlr.ich9_spi = ich9_spi;
+ hsfs = readw_(&ich9_spi->hsfs);
+ ichspi_lock = hsfs & HSFS_FLOCKDN;
+ cntlr.hsfs = hsfs;
cntlr.opmenu = ich9_spi->opmenu;
cntlr.menubytes = sizeof(ich9_spi->opmenu);
cntlr.optype = &ich9_spi->optype;
@@ -392,6 +412,12 @@ void spi_init(void)
cntlr.control = (uint16_t *)ich9_spi->ssfc;
cntlr.bbar = &ich9_spi->bbar;
cntlr.preop = &ich9_spi->preop;
+
+ if (cntlr.hsfs & HSFS_FDV)
+ {
+ writel_ (4, &ich9_spi->fdoc);
+ cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ }
break;
}
default:
@@ -591,6 +617,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+int spi_is_multichip (void)
+{
+ if (cntlr.revision != 9)
+ return 0;
+ if (!(cntlr.hsfs & HSFS_FDV))
+ return 0;
+ return !!((cntlr.flmap0 >> 8) & 3);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bitsout, void *din, unsigned int bitsin)
{
@@ -743,3 +778,313 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return 0;
}
+
+/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
+static void ich_hwseq_set_addr(uint32_t addr)
+{
+ uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
+ writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
+}
+
+/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
+ Resets all error flags in HSFS.
+ Returns 0 if the cycle completes successfully without errors within
+ timeout us, 1 on errors. */
+static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
+ unsigned int len)
+{
+ uint16_t hsfs;
+ uint32_t addr;
+
+ timeout /= 8; /* scale timeout duration to counter */
+ while ((((hsfs = readw_(cntlr.ich9_spi->hsfs)) &
+ (HSFS_FDONE | HSFS_FCERR)) == 0) &&
+ --timeout) {
+ udelay(8);
+ }
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ if (!timeout) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+
+ if (hsfs & HSFS_FCERR) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+ return 0;
+}
+
+
+static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 start, end, erase_size;
+ int ret;
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ start = offset;
+ end = start + len;
+
+ while (offset < end) {
+ ich_hwseq_set_addr(offset);
+
+ offset += erase_size;
+
+ /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+ if (ich_hwseq_wait_for_cycle_complete(timeout, len))
+ {
+ printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
+ ret = -1;
+ goto out;
+ }
+ }
+
+ printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static void ich_read_data(uint8_t *data, int len)
+{
+ int i;
+ uint32_t temp32 = 0;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = readl_(cntlr.data + i);
+
+ data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
+ }
+}
+
+static int ich_hwseq_read(struct spi_flash *flash,
+ u32 addr, size_t len, void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to read %x-%x which is out of chip\n",
+ (unsigned) addr,
+ (unsigned) addr+(unsigned) len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ block_len = min(len, cntlr.databytes);
+ ich_hwseq_set_addr(addr);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* set read operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ return 1;
+ ich_read_data(buf, block_len);
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ return 0;
+}
+
+/* Fill len bytes from the data array into the fdata/spid registers.
+ *
+ * Note that using len > flash->pgm->spi.max_data_write will trash the registers
+ * following the data registers.
+ */
+static void ich_fill_data(const uint8_t *data, int len)
+{
+ uint32_t temp32 = 0;
+ int i;
+
+ if (len <= 0)
+ return;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = 0;
+
+ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
+
+ if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+ }
+ i--;
+ if ((i % 4) != 3) /* Write remaining data to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+}
+
+static int ich_hwseq_write(struct spi_flash *flash,
+ u32 addr, size_t len, const void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+ uint32_t start = addr;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to write 0x%x-0x%x which is out of chip\n",
+ (unsigned)addr, (unsigned) (addr+len));
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ ich_hwseq_set_addr(addr);
+ block_len = min(len, cntlr.databytes);
+ ich_fill_data(buf, block_len);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ {
+ printk (BIOS_ERR, "SF: write failure at %x\n",
+ addr);
+ return -1;
+ }
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
+ (unsigned) (addr - start), start);
+ return 0;
+}
+
+
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ int ret;
+
+ if (cntlr.revision != 9) {
+ printk(BIOS_WARNING, "SF: Unsupported revision %x\n",
+ cntlr.revision);
+ return NULL;
+ }
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printk(BIOS_WARNING, "SF: Failed to set up slave\n");
+ free (flash);
+ return NULL;
+ }
+
+ spi->rw = SPI_READ_FLAG;
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret);
+ free (flash);
+ return NULL;
+ }
+
+ flash->spi = spi;
+ flash->name = "Opaque HW-sequencing";
+
+ flash->write = ich_hwseq_write;
+ flash->erase = ich_hwseq_erase;
+ flash->read = ich_hwseq_read;
+ switch ((cntlr.hsfs >> 3) & 3)
+ {
+ case 0:
+ flash->sector_size = 256;
+ break;
+ case 1:
+ flash->sector_size = 4096;
+ break;
+ case 2:
+ flash->sector_size = 8192;
+ break;
+ case 3:
+ flash->sector_size = 65536;
+ break;
+ }
+
+ uint32_t flcomp;
+
+ writel_ (0x1000, &cntlr.ich9_spi->fdoc);
+ flcomp = readl_(&cntlr.ich9_spi->fdod);
+
+ flash->size = 1 << (19 + (flcomp & 7));
+
+ if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
+ flash->size += 1 << (19 + ((flcomp >> 3) & 7));
+ printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
+
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
+ printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
+ flash->name, flash->sector_size, flash->size);
+
+ spi_release_bus(spi);
+
+ return flash;
+}
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 356dd8a..2728b54 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -59,6 +59,14 @@ void intel_pch_finalize_smm(void);
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
+int spi_is_multichip(void);
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+#endif
+#endif
+
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
void pch_enable(device_t dev);
diff --git a/src/southbridge/intel/ibexpeak/spi.c b/src/southbridge/intel/ibexpeak/spi.c
index e263b7f..6ff8fce 100644
--- a/src/southbridge/intel/ibexpeak/spi.c
+++ b/src/southbridge/intel/ibexpeak/spi.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
+ * Copyright (C) 2011 Stefan Tauner
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,11 +30,20 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci.h>
+#include <spi_flash.h>
#include <spi-generic.h>
+#include "pch.h"
#define min(a, b) ((a)<(b)?(a):(b))
+#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
+#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
+#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
+#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
+
+
#ifdef __SMM__
#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
@@ -115,7 +126,11 @@ typedef struct ich9_spi_regs {
typedef struct ich_spi_controller {
int locked;
+ int revision;
+ uint32_t flmap0;
+ uint32_t hsfs;
+ ich9_spi_regs *ich9_spi;
uint8_t *opmenu;
int menubytes;
uint16_t *preop;
@@ -357,6 +372,7 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
+ cntlr.revision = ich_version;
switch (ich_version) {
case 7:
{
@@ -382,7 +398,11 @@ void spi_init(void)
const uint16_t ich9_spibar_offset = 0x3800;
ich9_spi_regs *ich9_spi =
(ich9_spi_regs *)(rcrb + ich9_spibar_offset);
- ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ uint16_t hsfs;
+ cntlr.ich9_spi = ich9_spi;
+ hsfs = readw_(&ich9_spi->hsfs);
+ ichspi_lock = hsfs & HSFS_FLOCKDN;
+ cntlr.hsfs = hsfs;
cntlr.opmenu = ich9_spi->opmenu;
cntlr.menubytes = sizeof(ich9_spi->opmenu);
cntlr.optype = &ich9_spi->optype;
@@ -393,6 +413,12 @@ void spi_init(void)
cntlr.control = (uint16_t *)ich9_spi->ssfc;
cntlr.bbar = &ich9_spi->bbar;
cntlr.preop = &ich9_spi->preop;
+
+ if (cntlr.hsfs & HSFS_FDV)
+ {
+ writel_ (4, &ich9_spi->fdoc);
+ cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ }
break;
}
default:
@@ -592,6 +618,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+int spi_is_multichip (void)
+{
+ if (cntlr.revision != 9)
+ return 0;
+ if (!(cntlr.hsfs & HSFS_FDV))
+ return 0;
+ return !!((cntlr.flmap0 >> 8) & 3);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bitsout, void *din, unsigned int bitsin)
{
@@ -744,3 +779,313 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return 0;
}
+
+/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
+static void ich_hwseq_set_addr(uint32_t addr)
+{
+ uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
+ writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
+}
+
+/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
+ Resets all error flags in HSFS.
+ Returns 0 if the cycle completes successfully without errors within
+ timeout us, 1 on errors. */
+static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
+ unsigned int len)
+{
+ uint16_t hsfs;
+ uint32_t addr;
+
+ timeout /= 8; /* scale timeout duration to counter */
+ while ((((hsfs = readw_(cntlr.ich9_spi->hsfs)) &
+ (HSFS_FDONE | HSFS_FCERR)) == 0) &&
+ --timeout) {
+ udelay(8);
+ }
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ if (!timeout) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+
+ if (hsfs & HSFS_FCERR) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+ return 0;
+}
+
+
+static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 start, end, erase_size;
+ int ret;
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ start = offset;
+ end = start + len;
+
+ while (offset < end) {
+ ich_hwseq_set_addr(offset);
+
+ offset += erase_size;
+
+ /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+ if (ich_hwseq_wait_for_cycle_complete(timeout, len))
+ {
+ printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
+ ret = -1;
+ goto out;
+ }
+ }
+
+ printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static void ich_read_data(uint8_t *data, int len)
+{
+ int i;
+ uint32_t temp32 = 0;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = readl_(cntlr.data + i);
+
+ data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
+ }
+}
+
+static int ich_hwseq_read(struct spi_flash *flash,
+ u32 addr, size_t len, void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to read %x-%x which is out of chip\n",
+ (unsigned) addr,
+ (unsigned) addr+(unsigned) len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ block_len = min(len, cntlr.databytes);
+ ich_hwseq_set_addr(addr);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* set read operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ return 1;
+ ich_read_data(buf, block_len);
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ return 0;
+}
+
+/* Fill len bytes from the data array into the fdata/spid registers.
+ *
+ * Note that using len > flash->pgm->spi.max_data_write will trash the registers
+ * following the data registers.
+ */
+static void ich_fill_data(const uint8_t *data, int len)
+{
+ uint32_t temp32 = 0;
+ int i;
+
+ if (len <= 0)
+ return;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = 0;
+
+ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
+
+ if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+ }
+ i--;
+ if ((i % 4) != 3) /* Write remaining data to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+}
+
+static int ich_hwseq_write(struct spi_flash *flash,
+ u32 addr, size_t len, const void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+ uint32_t start = addr;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to write 0x%x-0x%x which is out of chip\n",
+ (unsigned)addr, (unsigned) (addr+len));
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ ich_hwseq_set_addr(addr);
+ block_len = min(len, cntlr.databytes);
+ ich_fill_data(buf, block_len);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ {
+ printk (BIOS_ERR, "SF: write failure at %x\n",
+ addr);
+ return -1;
+ }
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
+ (unsigned) (addr - start), start);
+ return 0;
+}
+
+
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ int ret;
+
+ if (cntlr.revision != 9) {
+ printk(BIOS_WARNING, "SF: Unsupported revision %x\n",
+ cntlr.revision);
+ return NULL;
+ }
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printk(BIOS_WARNING, "SF: Failed to set up slave\n");
+ free (flash);
+ return NULL;
+ }
+
+ spi->rw = SPI_READ_FLAG;
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret);
+ free (flash);
+ return NULL;
+ }
+
+ flash->spi = spi;
+ flash->name = "Opaque HW-sequencing";
+
+ flash->write = ich_hwseq_write;
+ flash->erase = ich_hwseq_erase;
+ flash->read = ich_hwseq_read;
+ switch ((cntlr.hsfs >> 3) & 3)
+ {
+ case 0:
+ flash->sector_size = 256;
+ break;
+ case 1:
+ flash->sector_size = 4096;
+ break;
+ case 2:
+ flash->sector_size = 8192;
+ break;
+ case 3:
+ flash->sector_size = 65536;
+ break;
+ }
+
+ uint32_t flcomp;
+
+ writel_ (0x1000, &cntlr.ich9_spi->fdoc);
+ flcomp = readl_(&cntlr.ich9_spi->fdod);
+
+ flash->size = 1 << (19 + (flcomp & 7));
+
+ if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
+ flash->size += 1 << (19 + ((flcomp >> 3) & 7));
+ printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
+
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
+ printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
+ flash->name, flash->sector_size, flash->size);
+
+ spi_release_bus(spi);
+
+ return flash;
+}
1
0
New patch to review for coreboot: 25aec29 X230: current tree as-is.
by Vladimir Serbinenko 05 Jan '14
by Vladimir Serbinenko 05 Jan '14
05 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4614
-gerrit
commit 25aec295958292ceca73fbce446ccc05bc6f3c39
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Jan 5 00:51:12 2014 +0100
X230: current tree as-is.
Known issues:
- No keyboard backlight (thinklight works)
- No S3
- EHCI output sometimes get "stuck" until key is pressed after sysagent execution.
- no S3
- MRC fails if MRC cache is supplied. For now MRC cache is disabled.
- MRC sometimes hangs with message:
System Agent: Initializing PCH
{433e0f9f-05ae-410a-a0c3-bf298ecb2
So a watchdog is reenabled to reboot if this happens
Not tested:
- ultranav
- fingerprint
- dock
Change-Id: Ida1374b8c7f99da7d2415b33c33ccc2c270a2282
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/arch/x86/boot/smbios.c | 7 +-
src/drivers/spi/eon.c | 9 +
src/ec/acpi/ec.c | 2 +
src/mainboard/lenovo/Kconfig | 10 +
src/mainboard/lenovo/x201/Makefile.inc | 1 +
src/mainboard/lenovo/x201/dsdt.asl.orig | 94 ++++++
src/mainboard/lenovo/x201/smihandler.c.orig | 210 +++++++++++++
src/mainboard/lenovo/x201/smihandler.c.rej | 15 +
src/mainboard/lenovo/x230/Kconfig | 62 ++++
src/mainboard/lenovo/x230/Makefile.inc | 20 ++
src/mainboard/lenovo/x230/acpi/ec.asl | 26 ++
src/mainboard/lenovo/x230/acpi/mainboard.asl | 0
src/mainboard/lenovo/x230/acpi/platform.asl | 74 +++++
.../lenovo/x230/acpi/sandybridge_pci_irqs.asl | 65 ++++
src/mainboard/lenovo/x230/acpi/superio.asl | 1 +
src/mainboard/lenovo/x230/acpi/video.asl | 115 +++++++
src/mainboard/lenovo/x230/acpi_tables.c | 271 ++++++++++++++++
src/mainboard/lenovo/x230/cmos.layout | 141 +++++++++
src/mainboard/lenovo/x230/devicetree.cb | 140 +++++++++
src/mainboard/lenovo/x230/dsdt.asl | 59 ++++
src/mainboard/lenovo/x230/ec.c | 29 ++
src/mainboard/lenovo/x230/ec.h | 31 ++
src/mainboard/lenovo/x230/fadt.c | 159 ++++++++++
src/mainboard/lenovo/x230/gpio.h | 304 ++++++++++++++++++
src/mainboard/lenovo/x230/hda_verb.h | 266 ++++++++++++++++
src/mainboard/lenovo/x230/mainboard.c | 186 +++++++++++
src/mainboard/lenovo/x230/onboard.h | 36 +++
src/mainboard/lenovo/x230/romstage.c | 324 +++++++++++++++++++
src/mainboard/lenovo/x230/smi.h | 0
src/mainboard/lenovo/x230/smihandler.c | 174 +++++++++++
src/mainboard/lenovo/x230/thermal.h | 31 ++
src/northbridge/intel/sandybridge/acpi/igd.asl | 17 +
src/northbridge/intel/sandybridge/mrccache.c | 16 +-
src/northbridge/intel/sandybridge/raminit.c | 8 +-
src/southbridge/intel/bd82x6x/pch.h | 8 +
src/southbridge/intel/bd82x6x/spi.c | 343 ++++++++++++++++++++-
36 files changed, 3241 insertions(+), 13 deletions(-)
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index 65bf538..25bdb37 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -130,12 +130,15 @@ static int smbios_write_type0(unsigned long *current, int handle)
t->vendor = smbios_add_string(t->eos, "coreboot");
#if !CONFIG_CHROMEOS
+#ifndef CONFIG_VENDOR_VERSION
+#define CONFIG_VENDOR_VERSION ""
+#endif
t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
if (strlen(CONFIG_LOCALVERSION))
- t->bios_version = smbios_add_string(t->eos, CONFIG_LOCALVERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION CONFIG_LOCALVERSION);
else
- t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION COREBOOT_VERSION);
#else
#define SPACES \
" "
diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c
index 21103ae..5a74b84 100644
--- a/src/drivers/spi/eon.c
+++ b/src/drivers/spi/eon.c
@@ -21,6 +21,7 @@
#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */
#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */
+#define EON_ID_EN25Q64 0x17
#define EON_ID_EN25Q128 0x18
struct eon_spi_flash_params {
@@ -52,6 +53,14 @@ static const struct eon_spi_flash_params eon_spi_flash_table[] = {
.nr_sectors = 4096,
.name = "EN25Q128",
},
+ {
+ .idcode1 = EON_ID_EN25Q64,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_sectors = 2048,
+ .name = "EN25Q64",
+ },
};
static int eon_write(struct spi_flash *flash,
diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
index ab287d6..3b984c4 100644
--- a/src/ec/acpi/ec.c
+++ b/src/ec/acpi/ec.c
@@ -104,6 +104,8 @@ u8 recv_ec_data(void)
// return -1;
}
+ udelay(10);
+
data = inb(ec_data_reg);
printk(BIOS_SPEW, "recv_ec_data: 0x%02x\n", data);
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index de9d56f..21413fc 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -17,6 +17,11 @@ config BOARD_LENOVO_X201
help
Lenovo X201 laptop. Consult wiki for details.
+config BOARD_LENOVO_X230
+ bool "ThinkPad X230"
+ help
+ Lenovo X230 laptop. Consult wiki for details.
+
config BOARD_LENOVO_T60
bool "ThinkPad T60 / T60p"
help
@@ -29,10 +34,15 @@ endchoice
source "src/mainboard/lenovo/x60/Kconfig"
source "src/mainboard/lenovo/x201/Kconfig"
+source "src/mainboard/lenovo/x230/Kconfig"
source "src/mainboard/lenovo/t60/Kconfig"
config MAINBOARD_VENDOR
string
default "Lenovo"
+config VENDOR_VERSION
+ string
+ default "CBET4000 "
+
endif # VENDOR_LENOVO
diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc
index 9055c9e..285e0d0 100644
--- a/src/mainboard/lenovo/x201/Makefile.inc
+++ b/src/mainboard/lenovo/x201/Makefile.inc
@@ -18,6 +18,7 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += dock.c
ramstage-y += dock.c
ramstage-y += gma.c
diff --git a/src/mainboard/lenovo/x201/dsdt.asl.orig b/src/mainboard/lenovo/x201/dsdt.asl.orig
new file mode 100644
index 0000000..ca47b13
--- /dev/null
+++ b/src/mainboard/lenovo/x201/dsdt.asl.orig
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20130325 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ #include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ #include "acpi/mainboard.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/nehalem/acpi/nehalem.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ Device (UNCR)
+ {
+ Name (_BBN, 0xFF)
+ Name (_ADR, 0x00)
+ Name (RID, 0x00)
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x00FF, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ Device (SAD)
+ {
+ Name (_ADR, 0x01)
+ Name (RID, 0x00)
+ OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
+ Field (SADC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x40),
+ PAM0, 8,
+ PAM1, 8,
+ PAM2, 8,
+ PAM3, 8,
+ PAM4, 8,
+ PAM5, 8,
+ PAM6, 8
+ }
+ }
+ }
+ }
+
+ #include "acpi/video.asl"
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+
+ // Dock support code
+ #include "acpi/dock.asl"
+}
diff --git a/src/mainboard/lenovo/x201/smihandler.c.orig b/src/mainboard/lenovo/x201/smihandler.c.orig
new file mode 100644
index 0000000..2558a9e
--- /dev/null
+++ b/src/mainboard/lenovo/x201/smihandler.c.orig
@@ -0,0 +1,210 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/ibexpeak/nvs.h"
+#include "southbridge/intel/ibexpeak/pch.h"
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include "dock.h"
+#include "smi.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+static void mainboard_smi_save_cmos(void)
+{
+ u8 val;
+ u8 tmp70, tmp72;
+
+ tmp70 = inb(0x70);
+ tmp72 = inb(0x72);
+
+ val = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);
+ set_option("tft_brightness", &val);
+ val = ec_read(H8_VOLUME_CONTROL);
+ set_option("volume", &val);
+
+ outb(tmp70, 0x70);
+ outb(tmp72, 0x72);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ case SMI_DOCK_CONNECT:
+ ec_clr_bit(0x03, 2);
+ udelay(250000);
+ if (!dock_connect()) {
+ ec_set_bit(0x03, 2);
+ /* set dock LED to indicate status */
+ ec_write(0x0c, 0x09);
+ ec_write(0x0c, 0x88);
+ } else {
+ /* blink dock LED to indicate failure */
+ ec_write(0x0c, 0x08);
+ ec_write(0x0c, 0xc9);
+ }
+ break;
+
+ case SMI_DOCK_DISCONNECT:
+ ec_clr_bit(0x03, 2);
+ dock_disconnect();
+ break;
+
+ case SMI_SAVE_CMOS:
+ mainboard_smi_save_cmos();
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
+ (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch (event) {
+ /* brightness up */
+ case 0x14:
+ mainboard_smi_brightness_up();
+ mainboard_smi_save_cmos();
+ break;
+ /* brightness down */
+ case 0x15:
+ mainboard_smi_brightness_down();
+ mainboard_smi_save_cmos();
+ break;
+ /* Fn-F9 key */
+ case 0x18:
+ /* Power loss */
+ case 0x27:
+ /* Undock Key */
+ case 0x50:
+ mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
+ break;
+ /* Dock Event */
+ case 0x37:
+ case 0x58:
+ mainboard_io_trap_handler(SMI_DOCK_CONNECT);
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << 12))
+ mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ u8 tmp;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
+ data);
+
+ if (!pmbase)
+ return 0;
+
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route H8SCI to SCI */
+ outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x02;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route H8SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/lenovo/x201/smihandler.c.rej b/src/mainboard/lenovo/x201/smihandler.c.rej
new file mode 100644
index 0000000..f52c463
--- /dev/null
+++ b/src/mainboard/lenovo/x201/smihandler.c.rej
@@ -0,0 +1,15 @@
+--- src/mainboard/lenovo/x201/smihandler.c
++++ src/mainboard/lenovo/x201/smihandler.c
+@@ -109,12 +109,10 @@
+ case 0x14:
+ /* brightness up */
+ mainboard_smi_brightness_up();
+- mainboard_smi_save_cmos();
+ break;
+ case 0x15:
+ /* brightness down */
+ mainboard_smi_brightness_down();
+- mainboard_smi_save_cmos();
+ break;
+ case 0x18:
+ /* Fn-F9 key */
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
new file mode 100644
index 0000000..ed6f028
--- /dev/null
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -0,0 +1,62 @@
+if BOARD_LENOVO_X230
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select EC_LENOVO_PMH7
+ select EC_LENOVO_H8
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_SMI_HANDLER
+ select GFXUMA
+ select EARLY_CBMEM_INIT
+
+ # Workaround for EC/KBC IRQ1.
+ select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+ string
+ default lenovo/x230
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "2325TLU"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x17aa
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x21fa
+
+config MAINBOARD_VENDOR
+ string
+ default "LENOVO"
+
+endif # BOARD_LENOVO_X230
diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc
new file mode 100644
index 0000000..d514d4b
--- /dev/null
+++ b/src/mainboard/lenovo/x230/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/lenovo/x230/acpi/ec.asl b/src/mainboard/lenovo/x230/acpi/ec.asl
new file mode 100644
index 0000000..4b3e72c
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+}
diff --git a/src/mainboard/lenovo/x230/acpi/mainboard.asl b/src/mainboard/lenovo/x230/acpi/mainboard.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl
new file mode 100644
index 0000000..73478ea
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/platform.asl
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* Not implemented. */
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..ba725ac
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
+ Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
+ Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
+ Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
+ Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/lenovo/x230/acpi/superio.asl b/src/mainboard/lenovo/x230/acpi/superio.asl
new file mode 100644
index 0000000..a2657f1
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/superio.asl
@@ -0,0 +1 @@
+#include "../../../../drivers/pc80/ps2_controller.asl"
diff --git a/src/mainboard/lenovo/x230/acpi/video.asl b/src/mainboard/lenovo/x230/acpi/video.asl
new file mode 100644
index 0000000..12a268b
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/video.asl
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org>
+ * Copyright (c) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+
+Scope (\_SB.PCI0.GFX0)
+{
+ Device (LCD0)
+ {
+ Name (_ADR, 0x0400)
+ Name (BRCT, 0)
+
+ Name (BRIG, Package (0x12)
+ {
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (_BCL, 0, NotSerialized)
+ {
+ Store (1, BRCT)
+ Return (BRIG)
+ }
+
+ Method (_BCM, 1, NotSerialized)
+ {
+ Store (ShiftLeft (Arg0, 4), ^^BCLV)
+ Store (0x80000000, ^^CR1)
+ Store (0x061a061a, ^^CR2)
+ }
+ Method (_BQC, 0, NotSerialized)
+ {
+ Store (^^BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
+ }
+
+ Method(BRID, 1, NotSerialized)
+ {
+ Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
+ If (LEqual (Local0, Ones))
+ {
+ Return (0x11)
+ }
+ Return (Local0)
+ }
+
+ /* Using Notify is the right way. But Windows doesn't handle
+ it well. So use both method in a way to avoid double action.
+ */
+ Method (DECB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x87)
+ } Else {
+ Store (BRID (_BQC ()), Local0)
+ If (LNotEqual (Local0, 2))
+ {
+ Decrement (Local0)
+ }
+ _BCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+ Method (INCB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x86)
+ } Else {
+ Store (BRID (_BQC ()), Local0)
+ If (LNotEqual (Local0, 0x11))
+ {
+ Increment (Local0)
+ }
+ _BCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c
new file mode 100644
index 0000000..95b45db
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi_tables.c
@@ -0,0 +1,271 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ /* EC handles all thermal and fan control on Butterfly. */
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* CBMEM TOC */
+ gnvs->cmem = (u32)get_cbmem_toc();
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+ // TODO: MLR
+ // The firmware read/write status is a "virtual" switch and
+ // will be handled elsewhere. Until then hard-code to
+ // read/write instead of read-only for developer mode.
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RW;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+#if CONFIG_CHROMEOS
+ // TODO(reinauer) this could move elsewhere?
+ chromeos_init_vboot(&(gnvs->chromeos));
+#endif
+
+ acpi_update_thermal_table(gnvs);
+
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+ "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ /* And tell SMI about it */
+ smm_setup_structures((void *)current, NULL, NULL);
+
+ current += sizeof(global_nvs_t);
+ ALIGN_CURRENT;
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout
new file mode 100644
index 0000000..de8b182
--- /dev/null
+++ b/src/mainboard/lenovo/x230/cmos.layout
@@ -0,0 +1,141 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: EC
+411 1 e 8 first_battery
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 touchpad
+
+#415 569 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
new file mode 100644
index 0000000..94b5839
--- /dev/null
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -0,0 +1,140 @@
+chip northbridge/intel/sandybridge
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
+ register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
+ register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
+ register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ # Coordinate with HW_ALL
+ register "pstate_coord_type" = "0xfe"
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpi1_routing" = "2"
+ register "gpi8_routing" = "2"
+
+ register "ide_legacy_combined" = "0x0"
+ register "sata_ahci" = "0x1"
+ # Enable SATA ports 0 & 1
+ register "sata_port_map" = "0x3"
+ # Set max SATA speed to 3.0 Gb/s
+ register "sata_interface_speed_support" = "0x2"
+
+ register "gen1_dec" = "0x7c1601"
+ register "gen2_dec" = "0x0c15e1"
+ register "gen4_dec" = "0x0c06a1"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug)
+ device pci 1c.1 on end # PCIe Port #2 (ETH0)
+ device pci 1c.2 on end # PCIe Port #3 (Card Reader)
+ #force ASPM for PCIe bridge to Card Reader
+ register "pcie_aspm_f2" = "0x3"
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on #LPC bridge
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
+ end
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ end
+
+ chip ec/lenovo/h8
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+
+ register "config0" = "0xa6"
+ register "config1" = "0x09"
+ register "config2" = "0xa0"
+ register "config3" = "0xe0"
+
+ register "beepmask0" = "0x00"
+ register "beepmask1" = "0x86"
+
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xd0"
+ register "event5_enable" = "0xfc"
+ register "event6_enable" = "0x00"
+ register "event7_enable" = "0x01"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventa_enable" = "0x01"
+ register "eventb_enable" = "0x00"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x0d"
+
+ register "wlan_enable" = "0x01"
+ register "trackpoint_enable" = "0x03"
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl
new file mode 100644
index 0000000..5688f63
--- /dev/null
+++ b/src/mainboard/lenovo/x230/dsdt.asl
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define THINKPAD_EC_GPE 17
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+
+ #include "acpi/video.asl"
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/x230/ec.c b/src/mainboard/lenovo/x230/ec.c
new file mode 100644
index 0000000..96716a4
--- /dev/null
+++ b/src/mainboard/lenovo/x230/ec.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+
+void butterfly_ec_init(void)
+{
+ printk(BIOS_DEBUG, "Butterfly EC Init\n");
+
+
+}
diff --git a/src/mainboard/lenovo/x230/ec.h b/src/mainboard/lenovo/x230/ec.h
new file mode 100644
index 0000000..5bbbd5a
--- /dev/null
+++ b/src/mainboard/lenovo/x230/ec.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_EC_H
+#define BUTTERFLY_EC_H
+
+#define EC_SCI_GPI 13 /* GPIO13 is EC_SCI# */
+
+/* EC SMI sources TODO: MLR- make defines */
+
+#ifndef __ACPI__
+extern void butterfly_ec_init(void);
+#endif
+
+#endif // BUTTERFLY_EC_H
diff --git a/src/mainboard/lenovo/x230/fadt.c b/src/mainboard/lenovo/x230/fadt.c
new file mode 100644
index 0000000..0ce3c72
--- /dev/null
+++ b/src/mainboard/lenovo/x230/fadt.c
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+ 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 16;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 101; /* c2 not supported */
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD |
+ ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 128;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/lenovo/x230/gpio.h b/src/mainboard/lenovo/x230/gpio.h
new file mode 100644
index 0000000..b592e6a
--- /dev/null
+++ b/src/mainboard/lenovo/x230/gpio.h
@@ -0,0 +1,304 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_GPIO_H
+#define BUTTERFLY_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NONE, /* Unused */
+ .gpio1 = GPIO_MODE_NONE, /* Unused */
+ .gpio2 = GPIO_MODE_NONE, /* Unused */
+ .gpio3 = GPIO_MODE_NONE, /* Unused */
+ .gpio4 = GPIO_MODE_NATIVE, /* Native - TPSINT# for TP SMBus IRQ */
+ .gpio5 = GPIO_MODE_NONE, /* Unused */
+ .gpio6 = GPIO_MODE_GPIO, /* Input - BOARD_ID4 */
+ .gpio7 = GPIO_MODE_GPIO, /* Input - BOARD_ID5 */
+ .gpio8 = GPIO_MODE_GPIO, /* Output - BT on/off */
+ .gpio9 = GPIO_MODE_NONE, /* Unused */
+ .gpio10 = GPIO_MODE_NONE, /* Unused */
+ .gpio11 = GPIO_MODE_GPIO, /* Input - TP WAKEUP Event */
+ .gpio12 = GPIO_MODE_NONE, /* Unused */
+ .gpio13 = GPIO_MODE_GPIO, /* Input - SCI from EC */
+ .gpio14 = GPIO_MODE_GPIO, /* Output - AOAC WLAN power control */
+ .gpio15 = GPIO_MODE_GPIO, /* Unused - Do not control WLAN*/
+ .gpio16 = GPIO_MODE_NONE, /* Unused */
+ .gpio17 = GPIO_MODE_GPIO, /* Input - DGPU_PWROK */
+ .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin*/
+ .gpio19 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 0 */
+ .gpio20 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ2# SDCard clock pin */
+ .gpio21 = GPIO_MODE_GPIO, /* Input - EC_ENTERING_RW for Google OS */
+ .gpio22 = GPIO_MODE_GPIO, /* Input - BIOS RECOVERY */
+ .gpio23 = GPIO_MODE_NONE, /* Unused */
+ .gpio24 = GPIO_MODE_GPIO, /* Output - DGPU_HOLD_RST# */
+ .gpio25 = GPIO_MODE_NONE, /* Unused */
+ .gpio26 = GPIO_MODE_NONE, /* Unused */
+ .gpio27 = GPIO_MODE_NONE, /* Unused */
+ .gpio28 = GPIO_MODE_NONE, /* Unused */
+ .gpio29 = GPIO_MODE_NONE, /* Unused */
+ .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# */
+ .gpio31 = GPIO_MODE_NONE, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT, /* Unused */
+ .gpio1 = GPIO_DIR_INPUT, /* Unused */
+ .gpio2 = GPIO_DIR_INPUT, /* Unused */
+ .gpio3 = GPIO_DIR_INPUT, /* Unused */
+ .gpio4 = GPIO_DIR_INPUT, /* Native */
+ .gpio5 = GPIO_DIR_INPUT, /* Unused */
+ .gpio6 = GPIO_DIR_INPUT, /* Input */
+ .gpio7 = GPIO_DIR_INPUT, /* Input */
+ .gpio8 = GPIO_DIR_INPUT, /* Output HIGH - set in mainboard.c */
+ .gpio9 = GPIO_DIR_INPUT, /* Unused */
+ .gpio10 = GPIO_DIR_INPUT, /* Unused */
+ .gpio11 = GPIO_DIR_INPUT, /* Input */
+ .gpio12 = GPIO_DIR_INPUT, /* Unused */
+ .gpio13 = GPIO_DIR_INPUT, /* Input */
+ .gpio14 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio15 = GPIO_DIR_INPUT, /* Unused */
+ .gpio16 = GPIO_DIR_INPUT, /* Unused */
+ .gpio17 = GPIO_DIR_INPUT, /* Input */
+ .gpio18 = GPIO_DIR_INPUT, /* Native */
+ .gpio19 = GPIO_DIR_INPUT, /* Input */
+ .gpio20 = GPIO_DIR_INPUT, /* Native */
+ .gpio21 = GPIO_DIR_INPUT, /* Input */
+ .gpio22 = GPIO_DIR_INPUT, /* Input */
+ .gpio23 = GPIO_DIR_INPUT, /* Unused */
+ .gpio24 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio25 = GPIO_DIR_INPUT, /* Unused */
+ .gpio26 = GPIO_DIR_INPUT, /* Unused */
+ .gpio27 = GPIO_DIR_INPUT, /* Unused */
+ .gpio28 = GPIO_DIR_INPUT, /* Unused */
+ .gpio29 = GPIO_DIR_INPUT, /* Unused */
+ .gpio30 = GPIO_DIR_INPUT, /* Native */
+ .gpio31 = GPIO_DIR_INPUT, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio1 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio2 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio3 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio4 = GPIO_LEVEL_LOW, /* Native */
+ .gpio5 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio6 = GPIO_LEVEL_LOW, /* Input */
+ .gpio7 = GPIO_LEVEL_LOW, /* Input */
+ .gpio8 = GPIO_LEVEL_HIGH, /* Output HIGH - set in mainboard.c */
+ .gpio9 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio10 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio11 = GPIO_LEVEL_LOW, /* Input */
+ .gpio12 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio13 = GPIO_LEVEL_LOW, /* Input */
+ .gpio14 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio15 = GPIO_LEVEL_HIGH, /* Unused */
+ .gpio16 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio17 = GPIO_LEVEL_LOW, /* Input */
+ .gpio18 = GPIO_LEVEL_LOW, /* Native */
+ .gpio19 = GPIO_LEVEL_LOW, /* Input */
+ .gpio20 = GPIO_LEVEL_LOW, /* Native */
+ .gpio21 = GPIO_LEVEL_LOW, /* Input */
+ .gpio22 = GPIO_LEVEL_LOW, /* Input */
+ .gpio23 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio24 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio25 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio26 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio27 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio28 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio29 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio30 = GPIO_LEVEL_LOW, /* Native */
+ .gpio31 = GPIO_LEVEL_LOW, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */
+ .gpio13 = GPIO_INVERT, /* invert EC SCI pin */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */
+ .gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */
+ .gpio34 = GPIO_MODE_NONE, /* Unused */
+ .gpio35 = GPIO_MODE_NONE, /* Unused */
+ .gpio36 = GPIO_MODE_GPIO, /* Output - DGPU_PWR_EN */
+ .gpio37 = GPIO_MODE_GPIO, /* Input - FDI TERM / VOLTAGE OVERRIDE */
+ .gpio38 = GPIO_MODE_GPIO, /* Input - MFG_MODE test */
+ .gpio39 = GPIO_MODE_GPIO, /* Input - DGPU_PRSNT */
+ .gpio40 = GPIO_MODE_NONE, /* Unused */
+ .gpio41 = GPIO_MODE_NONE, /* Unused */
+ .gpio42 = GPIO_MODE_NONE, /* Unused */
+ .gpio43 = GPIO_MODE_NONE, /* Unused */
+ .gpio44 = GPIO_MODE_GPIO, /* Input - BOARD_ID0 */
+ .gpio45 = GPIO_MODE_GPIO, /* Input - BOARD_ID1 */
+ .gpio46 = GPIO_MODE_GPIO, /* Input - BOARD_ID2 */
+ .gpio47 = GPIO_MODE_NATIVE, /* Native - PEGA_GPU clock request */
+ .gpio48 = GPIO_MODE_NONE, /* Unused */
+ .gpio49 = GPIO_MODE_NONE, /* Unused */
+ .gpio50 = GPIO_MODE_NONE, /* Unused */
+ .gpio51 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 1 */
+ .gpio52 = GPIO_MODE_GPIO, /* Input - Google recovery, Pull up +3V */
+ .gpio53 = GPIO_MODE_GPIO, /* Output - G Sensor LED */
+ .gpio54 = GPIO_MODE_GPIO, /* Input - Google Development */
+ .gpio55 = GPIO_MODE_GPIO, /* Input - Top-Block Swap Override */
+ .gpio56 = GPIO_MODE_NONE, /* Unused */
+ .gpio57 = GPIO_MODE_GPIO, /* Input - SV_DET */
+ .gpio58 = GPIO_MODE_NONE, /* Unused */
+ .gpio59 = GPIO_MODE_NONE, /* Unused */
+ .gpio60 = GPIO_MODE_NONE, /* GPO - DRAMRST_CNTRL_PCH */
+ .gpio61 = GPIO_MODE_NONE, /* Unused */
+ .gpio62 = GPIO_MODE_NATIVE, /* Native - Connect to EC 32.768KHz */
+ .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT, /* Native */
+ .gpio33 = GPIO_DIR_INPUT, /* Input */
+ .gpio34 = GPIO_DIR_INPUT, /* Unused */
+ .gpio35 = GPIO_DIR_INPUT, /* Unused */
+ .gpio36 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio37 = GPIO_DIR_INPUT, /* Input */
+ .gpio38 = GPIO_DIR_INPUT, /* Input */
+ .gpio39 = GPIO_DIR_INPUT, /* Input */
+ .gpio40 = GPIO_DIR_INPUT, /* Unused */
+ .gpio41 = GPIO_DIR_INPUT, /* Unused */
+ .gpio42 = GPIO_DIR_INPUT, /* Unused */
+ .gpio43 = GPIO_DIR_INPUT, /* Unused */
+ .gpio44 = GPIO_DIR_INPUT, /* Input */
+ .gpio45 = GPIO_DIR_INPUT, /* Input */
+ .gpio46 = GPIO_DIR_INPUT, /* Input */
+ .gpio47 = GPIO_DIR_INPUT, /* Native */
+ .gpio48 = GPIO_DIR_INPUT, /* Unused */
+ .gpio49 = GPIO_DIR_INPUT, /* Unused */
+ .gpio50 = GPIO_DIR_INPUT, /* Unused */
+ .gpio51 = GPIO_DIR_INPUT, /* Input */
+ .gpio52 = GPIO_DIR_INPUT, /* Input */
+ .gpio53 = GPIO_DIR_OUTPUT, /* Input */
+ .gpio54 = GPIO_DIR_INPUT, /* Input */
+ .gpio55 = GPIO_DIR_INPUT, /* Input */
+ .gpio56 = GPIO_DIR_INPUT, /* Unused */
+ .gpio57 = GPIO_DIR_INPUT, /* Input */
+ .gpio58 = GPIO_DIR_INPUT, /* Unused */
+ .gpio59 = GPIO_DIR_INPUT, /* Unused */
+ .gpio60 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio61 = GPIO_DIR_INPUT, /* Unused */
+ .gpio62 = GPIO_DIR_INPUT, /* Native */
+ .gpio63 = GPIO_DIR_INPUT, /* Native */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_LOW, /* Native */
+ .gpio33 = GPIO_LEVEL_LOW, /* Input */
+ .gpio34 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio35 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio36 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio37 = GPIO_LEVEL_LOW, /* Input */
+ .gpio38 = GPIO_LEVEL_LOW, /* Input */
+ .gpio39 = GPIO_LEVEL_LOW, /* Input */
+ .gpio40 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio41 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio42 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio43 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio44 = GPIO_LEVEL_LOW, /* Input */
+ .gpio45 = GPIO_LEVEL_LOW, /* Input */
+ .gpio46 = GPIO_LEVEL_LOW, /* Input */
+ .gpio47 = GPIO_LEVEL_LOW, /* Native */
+ .gpio48 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio49 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio50 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio51 = GPIO_LEVEL_LOW, /* Input */
+ .gpio52 = GPIO_LEVEL_LOW, /* Input */
+ .gpio53 = GPIO_LEVEL_HIGH, /* Input */
+ .gpio54 = GPIO_LEVEL_LOW, /* Input */
+ .gpio55 = GPIO_LEVEL_LOW, /* Input */
+ .gpio56 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio57 = GPIO_LEVEL_LOW, /* Input */
+ .gpio58 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio59 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio60 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio61 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio62 = GPIO_LEVEL_LOW, /* Native */
+ .gpio63 = GPIO_LEVEL_LOW, /* Native */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NONE, /* Unused */
+ .gpio65 = GPIO_MODE_NONE, /* Unused */
+ .gpio66 = GPIO_MODE_NONE, /* Unused */
+ .gpio67 = GPIO_MODE_NONE, /* Unused */
+ .gpio68 = GPIO_MODE_GPIO, /* Input - DGPU_PWR_EN */
+ .gpio69 = GPIO_MODE_NONE, /* Unused */
+ .gpio70 = GPIO_MODE_NONE, /* Unused */
+ .gpio71 = GPIO_MODE_NONE, /* Unused */
+ .gpio72 = GPIO_MODE_NONE, /* Unused */
+ .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# WLAN clock request */
+ .gpio74 = GPIO_MODE_NONE, /* Unused */
+ .gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT, /* Unused */
+ .gpio65 = GPIO_DIR_INPUT, /* Unused */
+ .gpio66 = GPIO_DIR_INPUT, /* Unused */
+ .gpio67 = GPIO_DIR_INPUT, /* Unused */
+ .gpio68 = GPIO_DIR_INPUT, /* Input */
+ .gpio69 = GPIO_DIR_INPUT, /* Unused */
+ .gpio70 = GPIO_DIR_INPUT, /* Unused */
+ .gpio71 = GPIO_DIR_INPUT, /* Unused */
+ .gpio72 = GPIO_DIR_INPUT, /* Unused */
+ .gpio73 = GPIO_DIR_INPUT, /* Native */
+ .gpio74 = GPIO_DIR_INPUT, /* Unused */
+ .gpio75 = GPIO_DIR_INPUT, /* Input */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio65 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio66 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio67 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio68 = GPIO_LEVEL_LOW, /* Input */
+ .gpio69 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio70 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio71 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio72 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio73 = GPIO_LEVEL_LOW, /* Native */
+ .gpio74 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio75 = GPIO_LEVEL_LOW, /* Input */
+};
+
+const struct pch_gpio_map butterfly_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+#endif
diff --git a/src/mainboard/lenovo/x230/hda_verb.h b/src/mainboard/lenovo/x230/hda_verb.h
new file mode 100644
index 0000000..7d22897
--- /dev/null
+++ b/src/mainboard/lenovo/x230/hda_verb.h
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Vendor Name : IDT
+ * Vendor ID : 0x111d76e5
+ * Subsystem ID : 0x103c18f9
+ * Revision ID : 0x100303
+ */
+
+
+static const u32 mainboard_cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC
+ 0x17aa21fa, // Subsystem ID
+ 0x00000073, // Number of 4 dword sets
+
+/* Bits 31:28 - Codec Address */
+/* Bits 27:20 - NID */
+/* Bits 19:8 - Verb ID */
+/* Bits 7:0 - Payload */
+
+/* NID 0x01 - NodeInfo */
+ 0x001720F9,
+ 0x00172118,
+ 0x0017223C,
+ 0x00172310,
+
+/* NID 0x0A - External Microphone Connector
+ * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
+ */
+ 0x00A71C20,
+ 0x00A71D10,
+ 0x00A71EA1,
+ 0x00A71F04,
+
+/* NID 0x0B - Headphone Connector
+ * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
+ */
+ 0x00B71C1F,
+ 0x00B71D10,
+ 0x00B71E21,
+ 0x00B71F04,
+
+/* NID 0x0C - Not connected
+ * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
+ */
+ 0x00C71CF0,
+ 0x00C71D00,
+ 0x00C71EF0,
+ 0x00C71F40,
+
+/* NID 0x0D - Internal Speakers
+ * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
+ */
+ 0x00D71C10,
+ 0x00D71D01,
+ 0x00D71E17,
+ 0x00D71F90,
+
+/* NID 0x0F - Not connected
+ * Config=0x40F000F0
+ */
+ 0x00F71CF0,
+ 0x00F71D00,
+ 0x00F71EF0,
+ 0x00F71F40,
+
+/* NID 0x11 - Internal Microphone
+ * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
+ */
+ 0x01171C40,
+ 0x01171D01,
+ 0x01171EA3,
+ 0x01171FD5,
+
+ /*
+ * Hardware EQ Parameters
+ * Sample Rate 88200
+ */
+ 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
+ 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80,
+ 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981,
+ 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80,
+ 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
+ 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80,
+ 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E,
+ 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80,
+ 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1,
+ 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80,
+ 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E,
+ 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80,
+ 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983,
+ 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80,
+ 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D,
+ 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80,
+ 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C,
+ 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80,
+ 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3,
+ 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80,
+ 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F,
+ 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80,
+ 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982,
+ 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80,
+ 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E,
+ 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80,
+ 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D,
+ 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80,
+ 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2,
+ 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80,
+ 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F,
+ 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80,
+ 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E,
+ 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80,
+ 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937,
+ 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80,
+ 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971,
+ 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80,
+ 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9,
+ 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80,
+ 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942,
+ 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80,
+ 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C,
+ 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80,
+ 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934,
+ 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80,
+ 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963,
+ 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80,
+ 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9,
+ 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80,
+ 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
+ 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80,
+
+ /*
+ * Hardware EQ Parameters
+ * Sample Rate 96000
+ */
+ 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
+ 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80,
+ 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981,
+ 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80,
+ 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
+ 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80,
+ 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E,
+ 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80,
+ 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1,
+ 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80,
+ 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E,
+ 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80,
+ 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983,
+ 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80,
+ 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D,
+ 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80,
+ 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C,
+ 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80,
+ 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3,
+ 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80,
+ 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F,
+ 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80,
+ 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982,
+ 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80,
+ 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E,
+ 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80,
+ 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D,
+ 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80,
+ 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1,
+ 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80,
+ 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F,
+ 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80,
+ 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D,
+ 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80,
+ 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938,
+ 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80,
+ 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972,
+ 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80,
+ 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8,
+ 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80,
+ 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941,
+ 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80,
+ 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999,
+ 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80,
+ 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934,
+ 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80,
+ 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966,
+ 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80,
+ 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9,
+ 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80,
+ 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
+ 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80,
+
+ /* SAFEDSP Parameters */
+ 0x022782C1, 0x02277127, 0x02277227, 0x02278801,
+ 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14,
+ 0x02278B0F, 0x0017B008,
+
+ /* Misc entries */
+ 0x00B707C0, /* Enable PortB as Output with HP amp */
+ 0x00D70740, /* Enable PortD as Output */
+ 0x0017A200, /* Disable ClkEn of PortSenseTst */
+ 0x0017C621, /* Slave Port - Port A used as microphone input for
+ combo Jack
+ Master Port - Port B used for Jack Presence Detect
+ Enable Combo Jack Detection */
+ 0x0017A208, /* Enable ClkEn of PortSenseTst */
+ 0x00170500, /* Set power state to D0 */
+
+ /* --- Next Codec --- */
+
+/* Vendor Name : Intel
+ * Vendor ID : 0x80862806
+ * Subsystem ID : 0x80860101
+ * Revision ID : 0x100000
+ */
+ /* coreboot specific header */
+ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of IDs
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ 0x30172001,
+ 0x30172101,
+ 0x30172286,
+ 0x30172380,
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ 0x30571c10,
+ 0x30571d00,
+ 0x30571e56,
+ 0x30571f18,
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ 0x30671c20,
+ 0x30671d00,
+ 0x30671e56,
+ 0x30671f18,
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ 0x30771c30,
+ 0x30771d00,
+ 0x30771e56,
+ 0x30771f18
+};
+
+static const u32 mainboard_pc_beep_verbs[] = {
+ 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
+};
+
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
+
+
diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c
new file mode 100644
index 0000000..b6b0b07
--- /dev/null
+++ b/src/mainboard/lenovo/x230/mainboard.c
@@ -0,0 +1,186 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+#include "ec.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <cbfs.h>
+#include <pc80/keyboard.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+ int res = 0;
+
+ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+ __func__, X86_AX);
+
+ switch (X86_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ X86_AX = 0x005f;
+ X86_CL = 0x00; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0001; /* Int-LVDS */
+ res = 1;
+ break;
+ case 0x5f70:
+ switch (X86_CH) {
+ case 0:
+ /* Get Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ X86_CH);
+ break;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+ break;
+ }
+ return res;
+}
+#endif
+
+const char *smbios_mainboard_version(void)
+{
+ return "Lenovo X230";
+}
+
+/* Audio Setup */
+
+extern const u32 *cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 *pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+
+}
+
+static void mainboard_init(device_t dev)
+{
+
+ /* This sneaked in here, because X201 SuperIO chip isn't really
+ connected to anything and hence we don't init it.
+ */
+ pc_keyboard_init(0);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+#if CONFIG_VGA_ROM_RUN
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+ verb_setup();
+}
+
+void h8_mainboard_init_dock (void);
+
+void h8_mainboard_init_dock (void)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/x230/onboard.h b/src/mainboard/lenovo/x230/onboard.h
new file mode 100644
index 0000000..e32e023
--- /dev/null
+++ b/src/mainboard/lenovo/x230/onboard.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_ONBOARD_H
+#define BUTTERFLY_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+/* uses 7-bit I2C address */
+/* must be set to edge triggered */
+#define BUTTERFLY_TRACKPAD_NAME "trackpad"
+#define BUTTERFLY_TRACKPAD_I2C_ADDR 0x67
+#define BUTTERFLY_TRACKPAD_IRQ 22 /* PIRQG - 22 Edge triggered */
+
+/* defines for programming the MAC address */
+#define BUTTERFLY_NIC_VENDOR_ID 0x10EC
+#define BUTTERFLY_NIC_DEVICE_ID 0x8136
+
+/* 0x00: White LINK LED and Amber ACTIVE LED */
+#define BUTTERFLY_NIC_LED_MODE 0x00
+#endif
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
new file mode 100644
index 0000000..1d1daf5
--- /dev/null
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <cbfs.h>
+
+static void pch_enable_lpc(void)
+{
+ /* X230 EC Decode Range Port60/64, Port62/66 */
+ /* Enable EC, PS/2 Keyboard/Mouse */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ COMA_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
+
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+
+ pci_write_config32(PCH_LPC_DEV, 0xac,
+ 0x80010000);
+}
+
+static void rcba_config(void)
+{
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P1IP WLAN INTA -> PIRQB
+ * D28IP_P2IP ETH0 INTB -> PIRQF
+ * D28IP_P3IP SDCARD INTC -> PIRQD
+ * D29IP_E1P EHCI1 INTA -> PIRQD
+ * D26IP_E2P EHCI2 INTA -> PIRQF
+ * D31IP_SIP SATA INTA -> PIRQB (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQH
+ * D31IP_TTIP THRT INTC -> PIRQA
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ *
+ * Trackpad interrupt is edge triggered and cannot be shared.
+ * TRACKPAD -> PIRQG
+
+ */
+
+ /* Device interrupt pin register (board specific) */
+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+ RCBA32(D29IP) = (INTA << D29IP_E1P);
+ RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
+ (INTC << D28IP_P3IP);
+ RCBA32(D27IP) = (INTA << D27IP_ZIP);
+ RCBA32(D26IP) = (INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+ /* Device interrupt route registers */
+ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+ DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+ DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
+ DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+ /* Enable IOAPIC (generic) */
+ RCBA16(OIC) = 0x0100;
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void) RCBA16(OIC);
+
+ /* Disable unused devices (board specific) */
+ RCBA32(FD) = 0x17f81fe3;
+ RCBA32(BUC) = 0;
+}
+
+void main(unsigned long bist)
+{
+ int boot_mode = 0;
+ int cbmem_was_initted;
+ u32 pm1_cnt;
+ u16 pm1_sts;
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ outb(0x6, 0xcf9);
+ hlt ();
+ }
+
+ struct pei_data pei_data = {
+ pei_version: PEI_VERSION,
+ mchbar: DEFAULT_MCHBAR,
+ dmibar: DEFAULT_DMIBAR,
+ epbar: DEFAULT_EPBAR,
+ pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+ smbusbar: SMBUS_IO_BASE,
+ wdbbar: 0x4000000,
+ wdbsize: 0x1000,
+ hpet_address: CONFIG_HPET_ADDRESS,
+ rcba: DEFAULT_RCBABASE,
+ pmbase: DEFAULT_PMBASE,
+ gpiobase: DEFAULT_GPIOBASE,
+ thermalbase: 0xfed08000,
+ system_type: 0, // 0 Mobile, 1 Desktop/Server
+ tseg_size: CONFIG_SMM_TSEG_SIZE,
+ spd_addresses: { 0xA0, 0x00,0xA2,0x00 },
+ ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+ ec_present: 1,
+ gbe_enable: 1,
+ ddr3lv_support: 0,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ dimm_channel0_disabled: 2,
+ dimm_channel1_disabled: 2,
+ max_ddr3_freq: 1600,
+ usb_port_config: {
+ /* enabled usb oc pin length */
+ { 1, 0, 0x0080 }, /* P0 */
+ { 1, 0, 0x0080 }, /* P1 */
+ { 1, 0, 0x0080 }, /* P3 */
+ { 1, 0, 0x0080 }, /* P4 */
+ { 1, 0, 0x0080 }, /* P5 */
+ { 1, 0, 0x0080 }, /* P6 */
+ { 1, 0, 0x0080 }, /* P7 */
+ { 1, 0, 0x0080 }, /* P8 */
+ { 1, 0, 0x0080 }, /* P9 */
+ { 1, 0, 0x0080 }, /* P10 */
+ { 1, 0, 0x0080 }, /* P11 */
+ { 1, 0, 0x0080 }, /* P12 */
+ { 1, 0, 0x0080 }, /* P13 */
+ { 1, 0, 0x0080 }, /* P14 */
+ { 1, 0, 0x0080 }, /* P15 */
+ },
+ ddr_refresh_rate_config: 2, /* Force double refresh rate */
+ };
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ if (bist == 0)
+ enable_lapic();
+
+
+ pch_enable_lpc();
+
+ /* Enable GPIOs */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+
+ // setup_pch_gpios(&butterfly_gpio_map);
+ outl (0x3962a5ff, DEFAULT_GPIOBASE | 0x0000);
+ outl (0x8ebf6aff, DEFAULT_GPIOBASE | 0x0004);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0008);
+ outl (0x66ff7efb, DEFAULT_GPIOBASE | 0x000c);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0010);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0014);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0018);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x001c);
+ outl (0x00080000, DEFAULT_GPIOBASE | 0x0020);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0024);
+ outw (0x0000, DEFAULT_GPIOBASE | 0x0028);
+ outw (0x0000, DEFAULT_GPIOBASE | 0x002a);
+ outl (0x00002042, DEFAULT_GPIOBASE | 0x002c);
+ outl (0x02ff08fe, DEFAULT_GPIOBASE | 0x0030);
+ outl (0x1f47f7fd, DEFAULT_GPIOBASE | 0x0034);
+ outl (0xbfffff43, DEFAULT_GPIOBASE | 0x0038);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x003c);
+ outl (0x000000ff, DEFAULT_GPIOBASE | 0x0040);
+ outl (0x00000fff, DEFAULT_GPIOBASE | 0x0044);
+ outl (0x00000fcf, DEFAULT_GPIOBASE | 0x0048);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x004c);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0050);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0054);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0058);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x005c);
+ outl (0x01000000, DEFAULT_GPIOBASE | 0x0060);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0064);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0068);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x006c);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0070);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0074);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x0078);
+ outl (0x00000000, DEFAULT_GPIOBASE | 0x007c);
+
+ /* Initialize console device(s) */
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+ printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+ if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+ }
+
+ post_code(0x38);
+ /* Enable SPD ROMs and DDR-III DRAM */
+ enable_smbus();
+
+ /* Prepare USB controller early in S3 resume */
+ if (boot_mode == 2)
+ enable_usb_bar();
+
+ post_code(0x39);
+
+ post_code(0x3a);
+ pei_data.boot_mode = boot_mode;
+ timestamp_add_now(TS_BEFORE_INITRAM);
+
+ /* MRC.bin has a bug and sometimes halts (instead of reboot?).
+ */
+ if (boot_mode != 2)
+ {
+ RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */
+ outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */
+ }
+
+ sdram_initialize(&pei_data);
+
+ if (boot_mode != 2)
+ {
+ RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
+ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
+ }
+
+ timestamp_add_now(TS_AFTER_INITRAM);
+ post_code(0x3c);
+
+ rcba_config();
+ post_code(0x3d);
+
+ quick_ram_check();
+ post_code(0x3e);
+
+ MCHBAR16(SSKPD) = 0xCAFE;
+ cbmem_was_initted = !cbmem_initialize();
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+
+ *(u32 *)CBMEM_BOOT_MODE = 0;
+ *(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+ if ((boot_mode == 2) && cbmem_was_initted) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+ if (resume_backup_memory) {
+ *(u32 *)CBMEM_BOOT_MODE = boot_mode;
+ *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+ }
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ } else if (boot_mode == 2) {
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0x6, 0xcf9);
+ hlt();
+ } else {
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ }
+#endif
+ post_code(0x3f);
+#if CONFIG_CHROMEOS
+ init_chromeos(boot_mode);
+#endif
+ timestamp_add_now(TS_END_ROMSTAGE);
+}
diff --git a/src/mainboard/lenovo/x230/smi.h b/src/mainboard/lenovo/x230/smi.h
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c
new file mode 100644
index 0000000..ca92091
--- /dev/null
+++ b/src/mainboard/lenovo/x230/smihandler.c
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include "smi.h"
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
+ (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch (event) {
+ case 0x14:
+ /* brightness up */
+ mainboard_smi_brightness_up();
+ break;
+ case 0x15:
+ /* brightness down */
+ mainboard_smi_brightness_down();
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << 12))
+ mainboard_smi_handle_ec_sci();
+}
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ u8 tmp;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
+ data);
+
+ if (!pmbase)
+ return 0;
+
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route H8SCI to SCI */
+ outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x02;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route H8SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_FINALIZE:
+ printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/lenovo/x230/thermal.h b/src/mainboard/lenovo/x230/thermal.h
new file mode 100644
index 0000000..9657fe0
--- /dev/null
+++ b/src/mainboard/lenovo/x230/thermal.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_THERMAL_H
+#define BUTTERFLY_THERMAL_H
+
+/* Active Thermal and fans are controlled by the EC. */
+
+ /* Temperature which OS will shutdown at */
+ #define CRITICAL_TEMPERATURE 100
+
+ /* Temperature which OS will throttle CPU */
+ #define PASSIVE_TEMPERATURE 90
+
+#endif
diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl
index a6804ad..7d3d4db 100644
--- a/src/northbridge/intel/sandybridge/acpi/igd.asl
+++ b/src/northbridge/intel/sandybridge/acpi/igd.asl
@@ -23,6 +23,23 @@ Device (GFX0)
{
Name (_ADR, 0x00020000)
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ BAR0, 64
+ }
+
+ OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x48254),
+ BCLV, 16,
+ Offset (0xc8250),
+ CR1, 32,
+ CR2, 32
+ }
+
/* Display Output Switching */
Method (_DOS, 1)
{
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index e19d2c5..a13a971 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -34,8 +34,8 @@
#endif
/* convert a pointer to flash area into the offset inside the flash */
-static inline u32 to_flash_offset(void *p) {
- return ((u32)p + CONFIG_ROM_SIZE);
+static inline u32 to_flash_offset(struct spi_flash *flash, void *p) {
+ return ((u32)p + flash->size);
}
static struct mrc_data_container *next_mrc_block(
@@ -192,7 +192,12 @@ static void update_mrc_cache(void *unused)
// 1. use spi_flash_probe() to find the flash, then
spi_init();
- struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ struct spi_flash *flash = 0;
+
+ if (!spi_is_multichip ())
+ flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!flash)
+ flash = spi_flash_hwseq(0, 0, 1000000, SPI_MODE_3);
if (!flash) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
@@ -212,7 +217,7 @@ static void update_mrc_cache(void *unused)
"Need to erase the MRC cache region of %d bytes at %p\n",
cache_size, cache_base);
- flash->erase(flash, to_flash_offset(cache_base), cache_size);
+ flash->erase(flash, to_flash_offset(flash, cache_base), cache_size);
/* we will start at the beginning again */
cache = cache_base;
@@ -220,7 +225,7 @@ static void update_mrc_cache(void *unused)
// 4. write mrc data with flash->write()
printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n",
cache);
- flash->write(flash, to_flash_offset(cache),
+ flash->write(flash, to_flash_offset(flash, cache),
current->mrc_data_size + sizeof(*current), current);
}
@@ -232,6 +237,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = {
struct mrc_data_container *find_current_mrc_cache(void)
{
+ return NULL;
struct mrc_data_container *cache_base;
u32 cache_size;
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 333a6b5..3dab218 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -219,7 +219,7 @@ static void post_system_agent_init(struct pei_data *pei_data)
void sdram_initialize(struct pei_data *pei_data)
{
struct sys_info sysinfo;
- unsigned long entry;
+ int (*entry) (struct pei_data *pei_data) __attribute__ ((regparm(1)));
report_platform_info();
@@ -252,13 +252,11 @@ void sdram_initialize(struct pei_data *pei_data)
/* Locate and call UEFI System Agent binary. */
/* TODO make MRC blob (0xab?) defined in cbfs_core.h. */
- entry = (unsigned long)cbfs_get_file_content(
+ entry = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab);
if (entry) {
int rv;
- asm volatile (
- "call *%%ecx\n\t"
- :"=a" (rv) : "c" (entry), "a" (pei_data));
+ rv = entry (pei_data);
if (rv) {
switch (rv) {
case -1:
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 90de855..6382481 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -58,6 +58,14 @@ void intel_pch_finalize_smm(void);
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
+int spi_is_multichip(void);
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+#endif
+#endif
+
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
void pch_enable(device_t dev);
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index ec5d7de..f7778e0 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
+ * Copyright (C) 2011 Stefan Tauner
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,11 +30,20 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci.h>
+#include <spi_flash.h>
#include <spi-generic.h>
+#include "pch.h"
#define min(a, b) ((a)<(b)?(a):(b))
+#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
+#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
+#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
+#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
+
+
#ifdef __SMM__
#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
@@ -115,7 +126,11 @@ typedef struct ich9_spi_regs {
typedef struct ich_spi_controller {
int locked;
+ int revision;
+ uint32_t flmap0;
+ uint32_t hsfs;
+ ich9_spi_regs *ich9_spi;
uint8_t *opmenu;
int menubytes;
uint16_t *preop;
@@ -356,6 +371,7 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
+ cntlr.revision = ich_version;
switch (ich_version) {
case 7:
{
@@ -381,7 +397,11 @@ void spi_init(void)
const uint16_t ich9_spibar_offset = 0x3800;
ich9_spi_regs *ich9_spi =
(ich9_spi_regs *)(rcrb + ich9_spibar_offset);
- ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ uint16_t hsfs;
+ cntlr.ich9_spi = ich9_spi;
+ hsfs = readw_(&ich9_spi->hsfs);
+ ichspi_lock = hsfs & HSFS_FLOCKDN;
+ cntlr.hsfs = hsfs;
cntlr.opmenu = ich9_spi->opmenu;
cntlr.menubytes = sizeof(ich9_spi->opmenu);
cntlr.optype = &ich9_spi->optype;
@@ -392,6 +412,12 @@ void spi_init(void)
cntlr.control = (uint16_t *)ich9_spi->ssfc;
cntlr.bbar = &ich9_spi->bbar;
cntlr.preop = &ich9_spi->preop;
+
+ if (cntlr.hsfs & HSFS_FDV)
+ {
+ writel_ (4, &ich9_spi->fdoc);
+ cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ }
break;
}
default:
@@ -591,6 +617,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+int spi_is_multichip (void)
+{
+ if (cntlr.revision != 9)
+ return 0;
+ if (!(cntlr.hsfs & HSFS_FDV))
+ return 0;
+ return !!((cntlr.flmap0 >> 8) & 3);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bitsout, void *din, unsigned int bitsin)
{
@@ -743,3 +778,309 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return 0;
}
+
+/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
+static void ich_hwseq_set_addr(uint32_t addr)
+{
+ uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
+ writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
+}
+
+/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
+ Resets all error flags in HSFS.
+ Returns 0 if the cycle completes successfully without errors within
+ timeout us, 1 on errors. */
+static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
+ unsigned int len)
+{
+ uint16_t hsfs;
+ uint32_t addr;
+
+ timeout /= 8; /* scale timeout duration to counter */
+ while ((((hsfs = readw_(cntlr.ich9_spi->hsfs)) &
+ (HSFS_FDONE | HSFS_FCERR)) == 0) &&
+ --timeout) {
+ udelay(8);
+ }
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ if (!timeout) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+
+ if (hsfs & HSFS_FCERR) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+ return 0;
+}
+
+
+static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 start, end, erase_size;
+ int ret;
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ start = offset;
+ end = start + len;
+
+ while (offset < end) {
+ ich_hwseq_set_addr(offset);
+
+ offset += erase_size;
+
+ /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+ if (ich_hwseq_wait_for_cycle_complete(timeout, len))
+ {
+ printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
+ ret = -1;
+ goto out;
+ }
+ }
+
+ printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static void ich_read_data(uint8_t *data, int len)
+{
+ int i;
+ uint32_t temp32 = 0;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = readl_(cntlr.data + i);
+
+ data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
+ }
+}
+
+static int ich_hwseq_read(struct spi_flash *flash,
+ u32 addr, size_t len, void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR, "Attempt to read %x-%x which is out of chip\n",
+ addr, addr+len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ block_len = min(len, cntlr.databytes);
+ ich_hwseq_set_addr(addr);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* set read operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ return 1;
+ ich_read_data(buf, block_len);
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ return 0;
+}
+
+/* Fill len bytes from the data array into the fdata/spid registers.
+ *
+ * Note that using len > flash->pgm->spi.max_data_write will trash the registers
+ * following the data registers.
+ */
+static void ich_fill_data(const uint8_t *data, int len)
+{
+ uint32_t temp32 = 0;
+ int i;
+
+ if (len <= 0)
+ return;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = 0;
+
+ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
+
+ if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+ }
+ i--;
+ if ((i % 4) != 3) /* Write remaining data to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+}
+
+static int ich_hwseq_write(struct spi_flash *flash,
+ u32 addr, size_t len, const void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+ uint32_t start = addr;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR, "Attempt to write %x-%x which is out of chip\n",
+ addr, addr+len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ ich_hwseq_set_addr(addr);
+ block_len = min(len, cntlr.databytes);
+ ich_fill_data(buf, block_len);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ {
+ printk (BIOS_ERR, "SF: write failure at %x\n",
+ addr);
+ return -1;
+ }
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ printk(BIOS_DEBUG, "SF: Successfully written %zu bytes @ %#x\n", addr - start, start);
+ return 0;
+}
+
+
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ int ret;
+
+ if (cntlr.revision != 9) {
+ printk(BIOS_WARNING, "SF: Unsupported revision %x\n",
+ cntlr.revision);
+ return NULL;
+ }
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printk(BIOS_WARNING, "SF: Failed to set up slave\n");
+ free (flash);
+ return NULL;
+ }
+
+ spi->rw = SPI_READ_FLAG;
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret);
+ free (flash);
+ return NULL;
+ }
+
+ flash->spi = spi;
+ flash->name = "Opaque HW-sequencing";
+
+ flash->write = ich_hwseq_write;
+ flash->erase = ich_hwseq_erase;
+ flash->read = ich_hwseq_read;
+ switch ((cntlr.hsfs >> 3) & 3)
+ {
+ case 0:
+ flash->sector_size = 256;
+ break;
+ case 1:
+ flash->sector_size = 4096;
+ break;
+ case 2:
+ flash->sector_size = 8192;
+ break;
+ case 3:
+ flash->sector_size = 65536;
+ break;
+ }
+
+ uint32_t flcomp;
+
+ writel_ (0x1000, &cntlr.ich9_spi->fdoc);
+ flcomp = readl_(&cntlr.ich9_spi->fdod);
+
+ flash->size = 1 << (19 + (flcomp & 7));
+
+ if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
+ flash->size += 1 << (19 + ((flcomp >> 3) & 7));
+ printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
+
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
+ printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
+ flash->name, flash->sector_size, flash->size);
+
+ spi_release_bus(spi);
+
+ return flash;
+}
1
0
Patch set updated for coreboot: 2df3862 sandy/ivy SPI: Support hardware sequencing and use with multiple chips
by Vladimir Serbinenko 04 Jan '14
by Vladimir Serbinenko 04 Jan '14
04 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4613
-gerrit
commit 2df3862e5364819b49b671a52a05e8184b1a6bb2
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 4 21:00:38 2014 +0100
sandy/ivy SPI: Support hardware sequencing and use with multiple chips
When 2 chips are present to get to seconf one you have to use hardware
sequencing. Also use it ass fallback if chip is unknown.
Based on code in flashrom by Stefan Tauner and Carl-Daniel Hailfinger
distributed under compatible license.
Tested on Lenovo X230 which has EN25QH64 (8M) + N25Q032..3E (4M)
Change-Id: I56f3cf0406b5f09fa327ed052c8e8b1df1d8a11f
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/northbridge/intel/sandybridge/mrccache.c | 7 +-
src/southbridge/intel/bd82x6x/pch.h | 8 +
src/southbridge/intel/bd82x6x/spi.c | 347 ++++++++++++++++++++++++++-
src/southbridge/intel/ibexpeak/pch.h | 8 +
src/southbridge/intel/ibexpeak/spi.c | 347 ++++++++++++++++++++++++++-
5 files changed, 714 insertions(+), 3 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index e19d2c5..4079b1f 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -192,7 +192,12 @@ static void update_mrc_cache(void *unused)
// 1. use spi_flash_probe() to find the flash, then
spi_init();
- struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ struct spi_flash *flash = 0;
+
+ if (!spi_is_multichip ())
+ flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!flash)
+ flash = spi_flash_hwseq(0, 0, 1000000, SPI_MODE_3);
if (!flash) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 90de855..6382481 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -58,6 +58,14 @@ void intel_pch_finalize_smm(void);
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
+int spi_is_multichip(void);
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+#endif
+#endif
+
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
void pch_enable(device_t dev);
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index ec5d7de..959c29c 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
+ * Copyright (C) 2011 Stefan Tauner
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,11 +30,20 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci.h>
+#include <spi_flash.h>
#include <spi-generic.h>
+#include "pch.h"
#define min(a, b) ((a)<(b)?(a):(b))
+#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
+#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
+#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
+#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
+
+
#ifdef __SMM__
#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
@@ -115,7 +126,11 @@ typedef struct ich9_spi_regs {
typedef struct ich_spi_controller {
int locked;
+ int revision;
+ uint32_t flmap0;
+ uint32_t hsfs;
+ ich9_spi_regs *ich9_spi;
uint8_t *opmenu;
int menubytes;
uint16_t *preop;
@@ -356,6 +371,7 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
+ cntlr.revision = ich_version;
switch (ich_version) {
case 7:
{
@@ -381,7 +397,11 @@ void spi_init(void)
const uint16_t ich9_spibar_offset = 0x3800;
ich9_spi_regs *ich9_spi =
(ich9_spi_regs *)(rcrb + ich9_spibar_offset);
- ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ uint16_t hsfs;
+ cntlr.ich9_spi = ich9_spi;
+ hsfs = readw_(&ich9_spi->hsfs);
+ ichspi_lock = hsfs & HSFS_FLOCKDN;
+ cntlr.hsfs = hsfs;
cntlr.opmenu = ich9_spi->opmenu;
cntlr.menubytes = sizeof(ich9_spi->opmenu);
cntlr.optype = &ich9_spi->optype;
@@ -392,6 +412,12 @@ void spi_init(void)
cntlr.control = (uint16_t *)ich9_spi->ssfc;
cntlr.bbar = &ich9_spi->bbar;
cntlr.preop = &ich9_spi->preop;
+
+ if (cntlr.hsfs & HSFS_FDV)
+ {
+ writel_ (4, &ich9_spi->fdoc);
+ cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ }
break;
}
default:
@@ -591,6 +617,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+int spi_is_multichip (void)
+{
+ if (cntlr.revision != 9)
+ return 0;
+ if (!(cntlr.hsfs & HSFS_FDV))
+ return 0;
+ return !!((cntlr.flmap0 >> 8) & 3);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bitsout, void *din, unsigned int bitsin)
{
@@ -743,3 +778,313 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return 0;
}
+
+/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
+static void ich_hwseq_set_addr(uint32_t addr)
+{
+ uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
+ writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
+}
+
+/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
+ Resets all error flags in HSFS.
+ Returns 0 if the cycle completes successfully without errors within
+ timeout us, 1 on errors. */
+static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
+ unsigned int len)
+{
+ uint16_t hsfs;
+ uint32_t addr;
+
+ timeout /= 8; /* scale timeout duration to counter */
+ while ((((hsfs = readw_(cntlr.ich9_spi->hsfs)) &
+ (HSFS_FDONE | HSFS_FCERR)) == 0) &&
+ --timeout) {
+ udelay(8);
+ }
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ if (!timeout) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+
+ if (hsfs & HSFS_FCERR) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+ return 0;
+}
+
+
+static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 start, end, erase_size;
+ int ret;
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ start = offset;
+ end = start + len;
+
+ while (offset < end) {
+ ich_hwseq_set_addr(offset);
+
+ offset += erase_size;
+
+ /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+ if (ich_hwseq_wait_for_cycle_complete(timeout, len))
+ {
+ printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
+ ret = -1;
+ goto out;
+ }
+ }
+
+ printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static void ich_read_data(uint8_t *data, int len)
+{
+ int i;
+ uint32_t temp32 = 0;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = readl_(cntlr.data + i);
+
+ data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
+ }
+}
+
+static int ich_hwseq_read(struct spi_flash *flash,
+ u32 addr, size_t len, void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to read %x-%x which is out of chip\n",
+ (unsigned) addr,
+ (unsigned) addr+(unsigned) len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ block_len = min(len, cntlr.databytes);
+ ich_hwseq_set_addr(addr);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* set read operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ return 1;
+ ich_read_data(buf, block_len);
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ return 0;
+}
+
+/* Fill len bytes from the data array into the fdata/spid registers.
+ *
+ * Note that using len > flash->pgm->spi.max_data_write will trash the registers
+ * following the data registers.
+ */
+static void ich_fill_data(const uint8_t *data, int len)
+{
+ uint32_t temp32 = 0;
+ int i;
+
+ if (len <= 0)
+ return;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = 0;
+
+ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
+
+ if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+ }
+ i--;
+ if ((i % 4) != 3) /* Write remaining data to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+}
+
+static int ich_hwseq_write(struct spi_flash *flash,
+ u32 addr, size_t len, const void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+ uint32_t start = addr;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to write 0x%x-0x%x which is out of chip\n",
+ (unsigned)addr, (unsigned) (addr+len));
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ ich_hwseq_set_addr(addr);
+ block_len = min(len, cntlr.databytes);
+ ich_fill_data(buf, block_len);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ {
+ printk (BIOS_ERR, "SF: write failure at %x\n",
+ addr);
+ return -1;
+ }
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
+ (unsigned) (addr - start), start);
+ return 0;
+}
+
+
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ int ret;
+
+ if (cntlr.revision != 9) {
+ printk(BIOS_WARNING, "SF: Unsupported revision %x\n",
+ cntlr.revision);
+ return NULL;
+ }
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printk(BIOS_WARNING, "SF: Failed to set up slave\n");
+ free (flash);
+ return NULL;
+ }
+
+ spi->rw = SPI_READ_FLAG;
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret);
+ free (flash);
+ return NULL;
+ }
+
+ flash->spi = spi;
+ flash->name = "Opaque HW-sequencing";
+
+ flash->write = ich_hwseq_write;
+ flash->erase = ich_hwseq_erase;
+ flash->read = ich_hwseq_read;
+ switch ((cntlr.hsfs >> 3) & 3)
+ {
+ case 0:
+ flash->sector_size = 256;
+ break;
+ case 1:
+ flash->sector_size = 4096;
+ break;
+ case 2:
+ flash->sector_size = 8192;
+ break;
+ case 3:
+ flash->sector_size = 65536;
+ break;
+ }
+
+ uint32_t flcomp;
+
+ writel_ (0x1000, &cntlr.ich9_spi->fdoc);
+ flcomp = readl_(&cntlr.ich9_spi->fdod);
+
+ flash->size = 1 << (19 + (flcomp & 7));
+
+ if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
+ flash->size += 1 << (19 + ((flcomp >> 3) & 7));
+ printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
+
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
+ printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
+ flash->name, flash->sector_size, flash->size);
+
+ spi_release_bus(spi);
+
+ return flash;
+}
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 356dd8a..2728b54 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -59,6 +59,14 @@ void intel_pch_finalize_smm(void);
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
+int spi_is_multichip(void);
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+#endif
+#endif
+
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
void pch_enable(device_t dev);
diff --git a/src/southbridge/intel/ibexpeak/spi.c b/src/southbridge/intel/ibexpeak/spi.c
index e263b7f..6ff8fce 100644
--- a/src/southbridge/intel/ibexpeak/spi.c
+++ b/src/southbridge/intel/ibexpeak/spi.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
+ * Copyright (C) 2011 Stefan Tauner
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,11 +30,20 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci.h>
+#include <spi_flash.h>
#include <spi-generic.h>
+#include "pch.h"
#define min(a, b) ((a)<(b)?(a):(b))
+#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
+#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
+#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
+#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
+
+
#ifdef __SMM__
#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
@@ -115,7 +126,11 @@ typedef struct ich9_spi_regs {
typedef struct ich_spi_controller {
int locked;
+ int revision;
+ uint32_t flmap0;
+ uint32_t hsfs;
+ ich9_spi_regs *ich9_spi;
uint8_t *opmenu;
int menubytes;
uint16_t *preop;
@@ -357,6 +372,7 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
+ cntlr.revision = ich_version;
switch (ich_version) {
case 7:
{
@@ -382,7 +398,11 @@ void spi_init(void)
const uint16_t ich9_spibar_offset = 0x3800;
ich9_spi_regs *ich9_spi =
(ich9_spi_regs *)(rcrb + ich9_spibar_offset);
- ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ uint16_t hsfs;
+ cntlr.ich9_spi = ich9_spi;
+ hsfs = readw_(&ich9_spi->hsfs);
+ ichspi_lock = hsfs & HSFS_FLOCKDN;
+ cntlr.hsfs = hsfs;
cntlr.opmenu = ich9_spi->opmenu;
cntlr.menubytes = sizeof(ich9_spi->opmenu);
cntlr.optype = &ich9_spi->optype;
@@ -393,6 +413,12 @@ void spi_init(void)
cntlr.control = (uint16_t *)ich9_spi->ssfc;
cntlr.bbar = &ich9_spi->bbar;
cntlr.preop = &ich9_spi->preop;
+
+ if (cntlr.hsfs & HSFS_FDV)
+ {
+ writel_ (4, &ich9_spi->fdoc);
+ cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ }
break;
}
default:
@@ -592,6 +618,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+int spi_is_multichip (void)
+{
+ if (cntlr.revision != 9)
+ return 0;
+ if (!(cntlr.hsfs & HSFS_FDV))
+ return 0;
+ return !!((cntlr.flmap0 >> 8) & 3);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bitsout, void *din, unsigned int bitsin)
{
@@ -744,3 +779,313 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return 0;
}
+
+/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
+static void ich_hwseq_set_addr(uint32_t addr)
+{
+ uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
+ writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
+}
+
+/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
+ Resets all error flags in HSFS.
+ Returns 0 if the cycle completes successfully without errors within
+ timeout us, 1 on errors. */
+static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
+ unsigned int len)
+{
+ uint16_t hsfs;
+ uint32_t addr;
+
+ timeout /= 8; /* scale timeout duration to counter */
+ while ((((hsfs = readw_(cntlr.ich9_spi->hsfs)) &
+ (HSFS_FDONE | HSFS_FCERR)) == 0) &&
+ --timeout) {
+ udelay(8);
+ }
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ if (!timeout) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+
+ if (hsfs & HSFS_FCERR) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+ return 0;
+}
+
+
+static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 start, end, erase_size;
+ int ret;
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ start = offset;
+ end = start + len;
+
+ while (offset < end) {
+ ich_hwseq_set_addr(offset);
+
+ offset += erase_size;
+
+ /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+ if (ich_hwseq_wait_for_cycle_complete(timeout, len))
+ {
+ printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
+ ret = -1;
+ goto out;
+ }
+ }
+
+ printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static void ich_read_data(uint8_t *data, int len)
+{
+ int i;
+ uint32_t temp32 = 0;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = readl_(cntlr.data + i);
+
+ data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
+ }
+}
+
+static int ich_hwseq_read(struct spi_flash *flash,
+ u32 addr, size_t len, void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to read %x-%x which is out of chip\n",
+ (unsigned) addr,
+ (unsigned) addr+(unsigned) len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ block_len = min(len, cntlr.databytes);
+ ich_hwseq_set_addr(addr);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* set read operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ return 1;
+ ich_read_data(buf, block_len);
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ return 0;
+}
+
+/* Fill len bytes from the data array into the fdata/spid registers.
+ *
+ * Note that using len > flash->pgm->spi.max_data_write will trash the registers
+ * following the data registers.
+ */
+static void ich_fill_data(const uint8_t *data, int len)
+{
+ uint32_t temp32 = 0;
+ int i;
+
+ if (len <= 0)
+ return;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = 0;
+
+ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
+
+ if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+ }
+ i--;
+ if ((i % 4) != 3) /* Write remaining data to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+}
+
+static int ich_hwseq_write(struct spi_flash *flash,
+ u32 addr, size_t len, const void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+ uint32_t start = addr;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to write 0x%x-0x%x which is out of chip\n",
+ (unsigned)addr, (unsigned) (addr+len));
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ ich_hwseq_set_addr(addr);
+ block_len = min(len, cntlr.databytes);
+ ich_fill_data(buf, block_len);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ {
+ printk (BIOS_ERR, "SF: write failure at %x\n",
+ addr);
+ return -1;
+ }
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
+ (unsigned) (addr - start), start);
+ return 0;
+}
+
+
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ int ret;
+
+ if (cntlr.revision != 9) {
+ printk(BIOS_WARNING, "SF: Unsupported revision %x\n",
+ cntlr.revision);
+ return NULL;
+ }
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printk(BIOS_WARNING, "SF: Failed to set up slave\n");
+ free (flash);
+ return NULL;
+ }
+
+ spi->rw = SPI_READ_FLAG;
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret);
+ free (flash);
+ return NULL;
+ }
+
+ flash->spi = spi;
+ flash->name = "Opaque HW-sequencing";
+
+ flash->write = ich_hwseq_write;
+ flash->erase = ich_hwseq_erase;
+ flash->read = ich_hwseq_read;
+ switch ((cntlr.hsfs >> 3) & 3)
+ {
+ case 0:
+ flash->sector_size = 256;
+ break;
+ case 1:
+ flash->sector_size = 4096;
+ break;
+ case 2:
+ flash->sector_size = 8192;
+ break;
+ case 3:
+ flash->sector_size = 65536;
+ break;
+ }
+
+ uint32_t flcomp;
+
+ writel_ (0x1000, &cntlr.ich9_spi->fdoc);
+ flcomp = readl_(&cntlr.ich9_spi->fdod);
+
+ flash->size = 1 << (19 + (flcomp & 7));
+
+ if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
+ flash->size += 1 << (19 + ((flcomp >> 3) & 7));
+ printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
+
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
+ printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
+ flash->name, flash->sector_size, flash->size);
+
+ spi_release_bus(spi);
+
+ return flash;
+}
1
0
Patch set updated for coreboot: 9bfdd5d sandy/ivy SPI: Support hardware sequencing and use with multiple chips
by Vladimir Serbinenko 04 Jan '14
by Vladimir Serbinenko 04 Jan '14
04 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4613
-gerrit
commit 9bfdd5ddf3229fb65232cedef80c1aeba2084c81
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 4 21:00:38 2014 +0100
sandy/ivy SPI: Support hardware sequencing and use with multiple chips
When 2 chips are present to get to seconf one you have to use hardware
sequencing. Also use it ass fallback if chip is unknown.
Based on code in flashrom by Stefan Tauner and Carl-Daniel Hailfinger
distributed under compatible license.
Tested on Lenovo X230 which has EN25QH64 (8M) + N25Q032..3E (4M)
Change-Id: I56f3cf0406b5f09fa327ed052c8e8b1df1d8a11f
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/northbridge/intel/sandybridge/mrccache.c | 7 +-
src/southbridge/intel/bd82x6x/pch.h | 8 +
src/southbridge/intel/bd82x6x/spi.c | 347 ++++++++++++++++++++++++++-
3 files changed, 360 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index e19d2c5..4079b1f 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -192,7 +192,12 @@ static void update_mrc_cache(void *unused)
// 1. use spi_flash_probe() to find the flash, then
spi_init();
- struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ struct spi_flash *flash = 0;
+
+ if (!spi_is_multichip ())
+ flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!flash)
+ flash = spi_flash_hwseq(0, 0, 1000000, SPI_MODE_3);
if (!flash) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 90de855..6382481 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -58,6 +58,14 @@ void intel_pch_finalize_smm(void);
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
+int spi_is_multichip(void);
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+#endif
+#endif
+
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
void pch_enable(device_t dev);
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index ec5d7de..959c29c 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
+ * Copyright (C) 2011 Stefan Tauner
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,11 +30,20 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci.h>
+#include <spi_flash.h>
#include <spi-generic.h>
+#include "pch.h"
#define min(a, b) ((a)<(b)?(a):(b))
+#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
+#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
+#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
+#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
+
+
#ifdef __SMM__
#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
@@ -115,7 +126,11 @@ typedef struct ich9_spi_regs {
typedef struct ich_spi_controller {
int locked;
+ int revision;
+ uint32_t flmap0;
+ uint32_t hsfs;
+ ich9_spi_regs *ich9_spi;
uint8_t *opmenu;
int menubytes;
uint16_t *preop;
@@ -356,6 +371,7 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
+ cntlr.revision = ich_version;
switch (ich_version) {
case 7:
{
@@ -381,7 +397,11 @@ void spi_init(void)
const uint16_t ich9_spibar_offset = 0x3800;
ich9_spi_regs *ich9_spi =
(ich9_spi_regs *)(rcrb + ich9_spibar_offset);
- ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ uint16_t hsfs;
+ cntlr.ich9_spi = ich9_spi;
+ hsfs = readw_(&ich9_spi->hsfs);
+ ichspi_lock = hsfs & HSFS_FLOCKDN;
+ cntlr.hsfs = hsfs;
cntlr.opmenu = ich9_spi->opmenu;
cntlr.menubytes = sizeof(ich9_spi->opmenu);
cntlr.optype = &ich9_spi->optype;
@@ -392,6 +412,12 @@ void spi_init(void)
cntlr.control = (uint16_t *)ich9_spi->ssfc;
cntlr.bbar = &ich9_spi->bbar;
cntlr.preop = &ich9_spi->preop;
+
+ if (cntlr.hsfs & HSFS_FDV)
+ {
+ writel_ (4, &ich9_spi->fdoc);
+ cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ }
break;
}
default:
@@ -591,6 +617,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+int spi_is_multichip (void)
+{
+ if (cntlr.revision != 9)
+ return 0;
+ if (!(cntlr.hsfs & HSFS_FDV))
+ return 0;
+ return !!((cntlr.flmap0 >> 8) & 3);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bitsout, void *din, unsigned int bitsin)
{
@@ -743,3 +778,313 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return 0;
}
+
+/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
+static void ich_hwseq_set_addr(uint32_t addr)
+{
+ uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
+ writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
+}
+
+/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
+ Resets all error flags in HSFS.
+ Returns 0 if the cycle completes successfully without errors within
+ timeout us, 1 on errors. */
+static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
+ unsigned int len)
+{
+ uint16_t hsfs;
+ uint32_t addr;
+
+ timeout /= 8; /* scale timeout duration to counter */
+ while ((((hsfs = readw_(cntlr.ich9_spi->hsfs)) &
+ (HSFS_FDONE | HSFS_FCERR)) == 0) &&
+ --timeout) {
+ udelay(8);
+ }
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ if (!timeout) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+
+ if (hsfs & HSFS_FCERR) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+ return 0;
+}
+
+
+static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 start, end, erase_size;
+ int ret;
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ start = offset;
+ end = start + len;
+
+ while (offset < end) {
+ ich_hwseq_set_addr(offset);
+
+ offset += erase_size;
+
+ /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+ if (ich_hwseq_wait_for_cycle_complete(timeout, len))
+ {
+ printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
+ ret = -1;
+ goto out;
+ }
+ }
+
+ printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static void ich_read_data(uint8_t *data, int len)
+{
+ int i;
+ uint32_t temp32 = 0;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = readl_(cntlr.data + i);
+
+ data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
+ }
+}
+
+static int ich_hwseq_read(struct spi_flash *flash,
+ u32 addr, size_t len, void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to read %x-%x which is out of chip\n",
+ (unsigned) addr,
+ (unsigned) addr+(unsigned) len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ block_len = min(len, cntlr.databytes);
+ ich_hwseq_set_addr(addr);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* set read operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ return 1;
+ ich_read_data(buf, block_len);
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ return 0;
+}
+
+/* Fill len bytes from the data array into the fdata/spid registers.
+ *
+ * Note that using len > flash->pgm->spi.max_data_write will trash the registers
+ * following the data registers.
+ */
+static void ich_fill_data(const uint8_t *data, int len)
+{
+ uint32_t temp32 = 0;
+ int i;
+
+ if (len <= 0)
+ return;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = 0;
+
+ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
+
+ if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+ }
+ i--;
+ if ((i % 4) != 3) /* Write remaining data to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+}
+
+static int ich_hwseq_write(struct spi_flash *flash,
+ u32 addr, size_t len, const void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+ uint32_t start = addr;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to write 0x%x-0x%x which is out of chip\n",
+ (unsigned)addr, (unsigned) (addr+len));
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ ich_hwseq_set_addr(addr);
+ block_len = min(len, cntlr.databytes);
+ ich_fill_data(buf, block_len);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ {
+ printk (BIOS_ERR, "SF: write failure at %x\n",
+ addr);
+ return -1;
+ }
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
+ (unsigned) (addr - start), start);
+ return 0;
+}
+
+
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ int ret;
+
+ if (cntlr.revision != 9) {
+ printk(BIOS_WARNING, "SF: Unsupported revision %x\n",
+ cntlr.revision);
+ return NULL;
+ }
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printk(BIOS_WARNING, "SF: Failed to set up slave\n");
+ free (flash);
+ return NULL;
+ }
+
+ spi->rw = SPI_READ_FLAG;
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret);
+ free (flash);
+ return NULL;
+ }
+
+ flash->spi = spi;
+ flash->name = "Opaque HW-sequencing";
+
+ flash->write = ich_hwseq_write;
+ flash->erase = ich_hwseq_erase;
+ flash->read = ich_hwseq_read;
+ switch ((cntlr.hsfs >> 3) & 3)
+ {
+ case 0:
+ flash->sector_size = 256;
+ break;
+ case 1:
+ flash->sector_size = 4096;
+ break;
+ case 2:
+ flash->sector_size = 8192;
+ break;
+ case 3:
+ flash->sector_size = 65536;
+ break;
+ }
+
+ uint32_t flcomp;
+
+ writel_ (0x1000, &cntlr.ich9_spi->fdoc);
+ flcomp = readl_(&cntlr.ich9_spi->fdod);
+
+ flash->size = 1 << (19 + (flcomp & 7));
+
+ if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
+ flash->size += 1 << (19 + ((flcomp >> 3) & 7));
+ printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
+
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
+ printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
+ flash->name, flash->sector_size, flash->size);
+
+ spi_release_bus(spi);
+
+ return flash;
+}
1
0
Patch set updated for coreboot: 53a1a4f sandy/ivy SPI: Support hardware sequencing and use with multiple chips
by Vladimir Serbinenko 04 Jan '14
by Vladimir Serbinenko 04 Jan '14
04 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4613
-gerrit
commit 53a1a4faa1a091524d8e73a2663322e312ba94de
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 4 21:00:38 2014 +0100
sandy/ivy SPI: Support hardware sequencing and use with multiple chips
When 2 chips are present to get to seconf one you have to use hardware
sequencing. Also use it ass fallback if chip is unknown.
Based on code in flashrom by Stefan Tauner and Carl-Daniel Hailfinger
distributed under compatible license.
Tested on Lenovo X230 which has EN25QH64 (8M) + N25Q032..3E (4M)
Change-Id: I56f3cf0406b5f09fa327ed052c8e8b1df1d8a11f
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/northbridge/intel/sandybridge/mrccache.c | 7 +-
src/southbridge/intel/bd82x6x/pch.h | 8 +
src/southbridge/intel/bd82x6x/spi.c | 346 ++++++++++++++++++++++++++-
3 files changed, 359 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index e19d2c5..4079b1f 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -192,7 +192,12 @@ static void update_mrc_cache(void *unused)
// 1. use spi_flash_probe() to find the flash, then
spi_init();
- struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ struct spi_flash *flash = 0;
+
+ if (!spi_is_multichip ())
+ flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!flash)
+ flash = spi_flash_hwseq(0, 0, 1000000, SPI_MODE_3);
if (!flash) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 90de855..6382481 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -58,6 +58,14 @@ void intel_pch_finalize_smm(void);
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
+int spi_is_multichip(void);
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+#endif
+#endif
+
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
void pch_enable(device_t dev);
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index ec5d7de..dde7792 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
+ * Copyright (C) 2011 Stefan Tauner
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,11 +30,20 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci.h>
+#include <spi_flash.h>
#include <spi-generic.h>
+#include "pch.h"
#define min(a, b) ((a)<(b)?(a):(b))
+#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
+#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
+#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
+#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
+
+
#ifdef __SMM__
#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
@@ -115,7 +126,11 @@ typedef struct ich9_spi_regs {
typedef struct ich_spi_controller {
int locked;
+ int revision;
+ uint32_t flmap0;
+ uint32_t hsfs;
+ ich9_spi_regs *ich9_spi;
uint8_t *opmenu;
int menubytes;
uint16_t *preop;
@@ -356,6 +371,7 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
+ cntlr.revision = ich_version;
switch (ich_version) {
case 7:
{
@@ -381,7 +397,11 @@ void spi_init(void)
const uint16_t ich9_spibar_offset = 0x3800;
ich9_spi_regs *ich9_spi =
(ich9_spi_regs *)(rcrb + ich9_spibar_offset);
- ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ uint16_t hsfs;
+ cntlr.ich9_spi = ich9_spi;
+ hsfs = readw_(&ich9_spi->hsfs);
+ ichspi_lock = hsfs & HSFS_FLOCKDN;
+ cntlr.hsfs = hsfs;
cntlr.opmenu = ich9_spi->opmenu;
cntlr.menubytes = sizeof(ich9_spi->opmenu);
cntlr.optype = &ich9_spi->optype;
@@ -392,6 +412,12 @@ void spi_init(void)
cntlr.control = (uint16_t *)ich9_spi->ssfc;
cntlr.bbar = &ich9_spi->bbar;
cntlr.preop = &ich9_spi->preop;
+
+ if (cntlr.hsfs & HSFS_FDV)
+ {
+ writel_ (4, &ich9_spi->fdoc);
+ cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ }
break;
}
default:
@@ -591,6 +617,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+int spi_is_multichip (void)
+{
+ if (cntlr.revision != 9)
+ return 0;
+ if (!(cntlr.hsfs & HSFS_FDV))
+ return 0;
+ return !!((cntlr.flmap0 >> 8) & 3);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bitsout, void *din, unsigned int bitsin)
{
@@ -743,3 +778,312 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return 0;
}
+
+/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
+static void ich_hwseq_set_addr(uint32_t addr)
+{
+ uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
+ writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
+}
+
+/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
+ Resets all error flags in HSFS.
+ Returns 0 if the cycle completes successfully without errors within
+ timeout us, 1 on errors. */
+static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
+ unsigned int len)
+{
+ uint16_t hsfs;
+ uint32_t addr;
+
+ timeout /= 8; /* scale timeout duration to counter */
+ while ((((hsfs = readw_(cntlr.ich9_spi->hsfs)) &
+ (HSFS_FDONE | HSFS_FCERR)) == 0) &&
+ --timeout) {
+ udelay(8);
+ }
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ if (!timeout) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+
+ if (hsfs & HSFS_FCERR) {
+ uint16_t hsfc;
+ addr = readl_(cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
+ "0x%08x (= 0x%08x + %d) HSFC=%x!\n",
+ addr, addr + len - 1, addr, len - 1,
+ hsfc);
+ return 1;
+ }
+ return 0;
+}
+
+
+static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 start, end, erase_size;
+ int ret;
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ start = offset;
+ end = start + len;
+
+ while (offset < end) {
+ ich_hwseq_set_addr(offset);
+
+ offset += erase_size;
+
+ /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+ if (ich_hwseq_wait_for_cycle_complete(timeout, len))
+ {
+ printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
+ ret = -1;
+ goto out;
+ }
+ }
+
+ printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static void ich_read_data(uint8_t *data, int len)
+{
+ int i;
+ uint32_t temp32 = 0;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = readl_(cntlr.data + i);
+
+ data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
+ }
+}
+
+static int ich_hwseq_read(struct spi_flash *flash,
+ u32 addr, size_t len, void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR,
+ "Attempt to read %x-%x which is out of chip\n",
+ (unsigned) addr,
+ (unsigned) addr+(unsigned) len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ block_len = min(len, cntlr.databytes);
+ ich_hwseq_set_addr(addr);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* set read operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ return 1;
+ ich_read_data(buf, block_len);
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ return 0;
+}
+
+/* Fill len bytes from the data array into the fdata/spid registers.
+ *
+ * Note that using len > flash->pgm->spi.max_data_write will trash the registers
+ * following the data registers.
+ */
+static void ich_fill_data(const uint8_t *data, int len)
+{
+ uint32_t temp32 = 0;
+ int i;
+
+ if (len <= 0)
+ return;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ temp32 = 0;
+
+ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
+
+ if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+ }
+ i--;
+ if ((i % 4) != 3) /* Write remaining data to regs. */
+ writel_(temp32, cntlr.data + (i - (i % 4)));
+}
+
+static int ich_hwseq_write(struct spi_flash *flash,
+ u32 addr, size_t len, const void *buf)
+{
+ uint16_t hsfc;
+ uint16_t timeout = 100 * 60;
+ uint8_t block_len;
+ uint32_t start = addr;
+
+ if (addr + len > flash->size) {
+ printk (BIOS_ERR, "Attempt to write %x-%x which is out of chip\n",
+ addr, addr+len);
+ return -1;
+ }
+
+ /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+ writew_(readw_(cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
+
+ while (len > 0) {
+ ich_hwseq_set_addr(addr);
+ block_len = min(len, cntlr.databytes);
+ ich_fill_data(buf, block_len);
+ hsfc = readw_(cntlr.ich9_spi->hsfc);
+ hsfc &= ~HSFC_FCYCLE; /* clear operation */
+ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
+ hsfc &= ~HSFC_FDBC; /* clear byte count */
+ /* set byte count */
+ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
+ hsfc |= HSFC_FGO; /* start */
+ writew_(hsfc, &cntlr.ich9_spi->hsfc);
+
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
+ {
+ printk (BIOS_ERR, "SF: write failure at %x\n",
+ addr);
+ return -1;
+ }
+ addr += block_len;
+ buf += block_len;
+ len -= block_len;
+ }
+ printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
+ (unsigned) (addr - start), start);
+ return 0;
+}
+
+
+struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ int ret;
+
+ if (cntlr.revision != 9) {
+ printk(BIOS_WARNING, "SF: Unsupported revision %x\n",
+ cntlr.revision);
+ return NULL;
+ }
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printk(BIOS_WARNING, "SF: Failed to set up slave\n");
+ free (flash);
+ return NULL;
+ }
+
+ spi->rw = SPI_READ_FLAG;
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret);
+ free (flash);
+ return NULL;
+ }
+
+ flash->spi = spi;
+ flash->name = "Opaque HW-sequencing";
+
+ flash->write = ich_hwseq_write;
+ flash->erase = ich_hwseq_erase;
+ flash->read = ich_hwseq_read;
+ switch ((cntlr.hsfs >> 3) & 3)
+ {
+ case 0:
+ flash->sector_size = 256;
+ break;
+ case 1:
+ flash->sector_size = 4096;
+ break;
+ case 2:
+ flash->sector_size = 8192;
+ break;
+ case 3:
+ flash->sector_size = 65536;
+ break;
+ }
+
+ uint32_t flcomp;
+
+ writel_ (0x1000, &cntlr.ich9_spi->fdoc);
+ flcomp = readl_(&cntlr.ich9_spi->fdod);
+
+ flash->size = 1 << (19 + (flcomp & 7));
+
+ if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
+ flash->size += 1 << (19 + ((flcomp >> 3) & 7));
+ printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
+
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
+ printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
+ flash->name, flash->sector_size, flash->size);
+
+ spi_release_bus(spi);
+
+ return flash;
+}
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