coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: ae068a2 cpu/intel: Add configuration for socket LGA1155
by Alexandru Gagniuc 06 Jan '14

06 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4623 -gerrit commit ae068a2762961f820fc4f71eabf34c2ef5615dd7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Jan 4 22:17:21 2014 -0600 cpu/intel: Add configuration for socket LGA1155 This is not a functional change. It just allows mainboards to explicitly select LGA1155. Change-Id: If4cf88fffcb3e37e24679fb70ced7c54f68b1837 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/socket_LGA1155/Kconfig | 27 +++++++++++++++++++++++++++ src/cpu/intel/socket_LGA1155/Makefile.inc | 8 ++++++++ src/cpu/intel/socket_LGA1155/socket_LGA1155.c | 5 +++++ 5 files changed, 42 insertions(+) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 6f4f561..51c824a 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -32,6 +32,7 @@ source src/cpu/intel/socket_mPGA603/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig +source src/cpu/intel/socket_LGA1155/Kconfig source src/cpu/intel/socket_LGA771/Kconfig source src/cpu/intel/socket_LGA775/Kconfig source src/cpu/intel/socket_rPGA989/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 964369d..1fbbedb 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -25,6 +25,7 @@ subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155 #socket_mPGA604_533Mhz #socket_mPGA604_800Mhz diff --git a/src/cpu/intel/socket_LGA1155/Kconfig b/src/cpu/intel/socket_LGA1155/Kconfig new file mode 100644 index 0000000..536f6ec --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/Kconfig @@ -0,0 +1,27 @@ +config CPU_INTEL_SOCKET_LGA1155 + bool + +if CPU_INTEL_SOCKET_LGA1155 + +# Northbridge config automatically selects the appropriate processor model, +# since the CPU and NB come on the same die. However, we select them here +# explicitly for consistency with other socket configs and to document the +# intention. + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select MMX + select SSE + select CACHE_AS_RAM + # 2nd Gen Core processors + select CPU_INTEL_MODEL_206AX + select NORTHBRIDGE_INTEL_SANDYBRIDGE + # 3rd Gen Core processors + select CPU_INTEL_MODEL_306AX + select NORTHBRIDGE_INTEL_IVYBRIDGE + +config CACHE_MRC_BIN + bool + default n + +endif # CPU_INTEL_SOCKET_LGA1155 diff --git a/src/cpu/intel/socket_LGA1155/Makefile.inc b/src/cpu/intel/socket_LGA1155/Makefile.inc new file mode 100644 index 0000000..4ff24c9 --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/Makefile.inc @@ -0,0 +1,8 @@ +ramstage-y += socket_LGA1155.c +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo diff --git a/src/cpu/intel/socket_LGA1155/socket_LGA1155.c b/src/cpu/intel/socket_LGA1155/socket_LGA1155.c new file mode 100644 index 0000000..63c925d --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/socket_LGA1155.c @@ -0,0 +1,5 @@ +#include <device/device.h> + +struct chip_operations cpu_intel_socket_LGA1155_ops = { + CHIP_NAME("Socket LGA1155 CPU") +};

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Patch set updated for coreboot: 0f9d696 sandy/ivy/nehalem: Make DRAM gate GPIO configurable
by Vladimir Serbinenko 05 Jan '14

05 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4622 -gerrit commit 0f9d696cbe6643a2d270833b31c03e8f2a963482 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 5 11:37:32 2014 +0100 sandy/ivy/nehalem: Make DRAM gate GPIO configurable DRAM gate GPIO is different on different mobos move it to hidden config with 60 (current value) as default. Set it to 10 for Lenovo X201. Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Kconfig | 4 ++++ src/southbridge/intel/bd82x6x/Kconfig | 4 ++++ src/southbridge/intel/bd82x6x/smihandler.c | 32 +++++++++++++++++++---------- src/southbridge/intel/ibexpeak/Kconfig | 4 ++++ src/southbridge/intel/ibexpeak/smihandler.c | 32 +++++++++++++++++++---------- 5 files changed, 54 insertions(+), 22 deletions(-) diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index a2d66b3..dbc80c5 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -43,6 +43,10 @@ config IRQ_SLOT_COUNT int default 18 +config CONFIG_DRAM_GATE_GPIO + int + default 10 + config MAX_CPUS int default 4 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index c2720ef..6a96c5e 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -45,6 +45,10 @@ config EHCI_DEBUG_OFFSET hex default 0xa0 +config DRAM_GATE_GPIO + int + default 60 + config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/bd82x6x/bootblock.c" diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 99f6b51..dc8bf8b 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -305,24 +305,34 @@ static void southbridge_gate_memory_reset(void) if (!gpiobase) return; +#if CONFIG_DRAM_GATE_GPIO >= 32 +#define SUFFIX(x) x ## 2 +#define OFFSET (CONFIG_DRAM_GATE_GPIO - 32) +#else +#define SUFFIX(x) x +#define OFFSET (CONFIG_DRAM_GATE_GPIO) +#endif + /* Make sure it is set as GPIO */ - reg32 = inl(gpiobase + GPIO_USE_SEL2); - if (!(reg32 & (1 << 28))) { - reg32 |= (1 << 28); - outl(reg32, gpiobase + GPIO_USE_SEL2); + reg32 = inl(gpiobase + SUFFIX(GPIO_USE_SEL)); + if (!(reg32 & (1 << OFFSET))) { + reg32 |= (1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GPIO_USE_SEL)); } /* Make sure it is set as output */ - reg32 = inl(gpiobase + GP_IO_SEL2); - if (reg32 & (1 << 28)) { - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_IO_SEL2); + reg32 = inl(gpiobase + SUFFIX(GP_IO_SEL)); + if (reg32 & (1 << OFFSET)) { + reg32 &= ~(1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GP_IO_SEL)); } /* Drive the output low */ - reg32 = inl(gpiobase + GP_LVL2); - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_LVL2); + reg32 = inl(gpiobase + SUFFIX(GP_LVL)); + reg32 &= ~(1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GP_LVL)); +#undef OFFSET +#undef SUFFIX } static void xhci_sleep(u8 slp_typ) diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 07e714b..7e1c4e0 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -43,6 +43,10 @@ config EHCI_DEBUG_OFFSET hex default 0xa0 +config DRAM_GATE_GPIO + int + default 60 + config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/bd82x6x/bootblock.c" diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 5ee8ef9..088c5c2 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -305,24 +305,34 @@ static void southbridge_gate_memory_reset(void) if (!gpiobase) return; +#if CONFIG_DRAM_GATE_GPIO >= 32 +#define SUFFIX(x) x ## 2 +#define OFFSET (CONFIG_DRAM_GATE_GPIO - 32) +#else +#define SUFFIX(x) x +#define OFFSET (CONFIG_DRAM_GATE_GPIO) +#endif + /* Make sure it is set as GPIO */ - reg32 = inl(gpiobase + GPIO_USE_SEL2); - if (!(reg32 & (1 << 28))) { - reg32 |= (1 << 28); - outl(reg32, gpiobase + GPIO_USE_SEL2); + reg32 = inl(gpiobase + SUFFIX(GPIO_USE_SEL)); + if (!(reg32 & (1 << OFFSET))) { + reg32 |= (1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GPIO_USE_SEL)); } /* Make sure it is set as output */ - reg32 = inl(gpiobase + GP_IO_SEL2); - if (reg32 & (1 << 28)) { - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_IO_SEL2); + reg32 = inl(gpiobase + SUFFIX(GP_IO_SEL)); + if (reg32 & (1 << OFFSET)) { + reg32 &= ~(1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GP_IO_SEL)); } /* Drive the output low */ - reg32 = inl(gpiobase + GP_LVL2); - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_LVL2); + reg32 = inl(gpiobase + SUFFIX(GP_LVL)); + reg32 &= ~(1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GP_LVL)); +#undef OFFSET +#undef SUFFIX } static void xhci_sleep(u8 slp_typ)

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Patch set updated for coreboot: ac77c06 ROMSIZE: Add option for 12M chips.
by Vladimir Serbinenko 05 Jan '14

05 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4615 -gerrit commit ac77c06034b30905289f10d8ed19628a45ede2ec Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 5 06:40:36 2014 +0100 ROMSIZE: Add option for 12M chips. On X230 2 real chips (8 + 4) are merged into one virtual 12M chip. Change-Id: I04e676e4a0a5b074d8a45dbfa8a595629fd1b66d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/romstage.c | 4 ++-- src/cpu/x86/Kconfig | 2 +- src/cpu/x86/mtrr/mtrr.c | 4 ++-- src/mainboard/Kconfig | 23 +++++++++++++++++++++++ src/mainboard/amd/dinar/agesawrapper.c | 4 ++-- src/mainboard/amd/inagua/romstage.c | 4 ++-- src/mainboard/amd/olivehill/agesawrapper.c | 4 ++-- src/mainboard/amd/parmer/agesawrapper.c | 4 ++-- src/mainboard/amd/persimmon/romstage.c | 4 ++-- src/mainboard/amd/south_station/romstage.c | 4 ++-- src/mainboard/amd/thatcher/agesawrapper.c | 4 ++-- src/mainboard/amd/torpedo/agesawrapper.c | 4 ++-- src/mainboard/amd/union_station/romstage.c | 4 ++-- src/mainboard/asrock/e350m1/romstage.c | 4 ++-- src/mainboard/asrock/imb-a180/agesawrapper.c | 4 ++-- src/mainboard/asus/f2a85-m/agesawrapper.c | 4 ++-- src/mainboard/gizmosphere/gizmo/romstage.c | 8 ++++---- src/mainboard/lippert/frontrunner-af/romstage.c | 4 ++-- src/mainboard/lippert/toucan-af/romstage.c | 4 ++-- src/mainboard/supermicro/h8qgi/agesawrapper.c | 4 ++-- src/mainboard/supermicro/h8scm/agesawrapper.c | 4 ++-- src/mainboard/tyan/s8226/agesawrapper.c | 4 ++-- 22 files changed, 66 insertions(+), 43 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 35b51c5..ea63ef8 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -124,9 +124,9 @@ static void *setup_romstage_stack_after_car(void) /* Cache the ROM as WP just below 4GiB. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~(CONFIG_ALIGNED_ROM_SIZE - 1) | MTRRphysMaskValid); slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + slot = stack_push(slot, ~(CONFIG_ALIGNED_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); num_mtrrs++; /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index c64a8e4..f509786 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -65,7 +65,7 @@ config TSC_SYNC_MFENCE config XIP_ROM_SIZE hex - default ROM_SIZE if ROMCC + default ALIGNED_ROM_SIZE if ROMCC default 0x10000 config CPU_ADDR_BITS diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d168978..955cec7 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -190,8 +190,8 @@ static struct memranges *get_physical_address_space(void) * when CONFIG_CACHE_ROM is enabled. The ROM is assumed * to be located at 4GiB - rom size. */ resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CONFIG_ROM_SIZE, + RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ALIGNED_ROM_SIZE)); + memranges_insert(addr_space, rom_base, CONFIG_ALIGNED_ROM_SIZE, MTRR_TYPE_WRPROT); #endif diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index fc38994..9ae80c1 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -225,6 +225,8 @@ config BOARD_ROMSIZE_KB_4096 bool config BOARD_ROMSIZE_KB_8192 bool +config BOARD_ROMSIZE_KB_12288 + bool config BOARD_ROMSIZE_KB_16384 bool @@ -239,6 +241,7 @@ choice default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 + default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 help Select the size of the ROM chip you intend to flash coreboot on. @@ -286,6 +289,11 @@ config COREBOOT_ROMSIZE_KB_8192 help Choose this option if you have a 8192 KB (8 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_12288 + bool "12288 KB (12 MB)" + help + Choose this option if you have a 12288 KB (12 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_16384 bool "16384 KB (16 MB)" help @@ -304,6 +312,7 @@ config COREBOOT_ROMSIZE_KB default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 default 8192 if COREBOOT_ROMSIZE_KB_8192 + default 12288 if COREBOOT_ROMSIZE_KB_12288 default 16384 if COREBOOT_ROMSIZE_KB_16384 # Map the config names to a hex value (bytes). @@ -317,6 +326,20 @@ config ROM_SIZE default 0x200000 if COREBOOT_ROMSIZE_KB_2048 default 0x400000 if COREBOOT_ROMSIZE_KB_4096 default 0x800000 if COREBOOT_ROMSIZE_KB_8192 + default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 + default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 + +config ALIGNED_ROM_SIZE + hex + default 0x10000 if COREBOOT_ROMSIZE_KB_64 + default 0x20000 if COREBOOT_ROMSIZE_KB_128 + default 0x40000 if COREBOOT_ROMSIZE_KB_256 + default 0x80000 if COREBOOT_ROMSIZE_KB_512 + default 0x100000 if COREBOOT_ROMSIZE_KB_1024 + default 0x200000 if COREBOOT_ROMSIZE_KB_2048 + default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x800000 if COREBOOT_ROMSIZE_KB_8192 + default 0x1000000 if COREBOOT_ROMSIZE_KB_12288 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 config ENABLE_POWER_BUTTON diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index 179822b..41be617 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -271,9 +271,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + MsrReg = (0x0100000000 - CONFIG_ALIGNED_ROM_SIZE) | 5; LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 2e46516..1395591 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -45,8 +45,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* all cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800); /* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index ecd85ee..ade7feb 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -166,9 +166,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index fcbdded..2366025 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -166,9 +166,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 58829b4..0de5a00 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -58,8 +58,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index af12026..c3ac439 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -46,8 +46,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 6331197..8bcc9dc 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -166,9 +166,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c index 8d06811..98c84bb 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.c +++ b/src/mainboard/amd/torpedo/agesawrapper.c @@ -279,9 +279,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */ diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index e4cd21b..af37dbb 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -45,8 +45,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index b76e6a8..ef8036b 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -49,8 +49,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr(0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr(0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr(0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr(0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 8300e34..10c4431 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -166,9 +166,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index 529878b..4e54a22 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -166,9 +166,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 05699cc..3449005 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -60,12 +60,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - msr.lo = ((0x0100000000ull - CONFIG_ROM_SIZE) | 5) & 0xFFFFFFFF; - msr.hi = ((0x0100000000ull - CONFIG_ROM_SIZE) | 5) >> 32; + msr.lo = ((0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5) & 0xFFFFFFFF; + msr.hi = ((0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5) >> 32; wrmsr (MSR_MTRR_VARIABLE_BASE6, msr); - msr.lo = ((0x1000000000ull - CONFIG_ROM_SIZE) | 0x800) & 0xFFFFFFFF; - msr.hi = ((0x1000000000ull - CONFIG_ROM_SIZE) | 0x800) >> 32; + msr.lo = ((0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800) & 0xFFFFFFFF; + msr.hi = ((0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800) >> 32; wrmsr (MSR_MTRR_VARIABLE_MASK6, msr); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 093a047..248124c 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -58,8 +58,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 88b8100..e9eb9eb 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -58,8 +58,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + __writemsr (0x20c, (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ALIGNED_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 3199575..527bbc1 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -192,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID) LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + MsrReg = (0x0100000000 - CONFIG_ALIGNED_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index 49abe25..cf7a15e 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -192,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID) LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + MsrReg = (0x0100000000 - CONFIG_ALIGNED_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 7fba1b7..b7e0791 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -202,9 +202,9 @@ agesawrapper_amdinitmmio ( LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + MsrReg = (0x0100000000ull - CONFIG_ALIGNED_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ALIGNED_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS;

1 0

Patch set updated for coreboot: 2be53f3 sandybridge/igd: Add brightness register descriptions
by Vladimir Serbinenko 05 Jan '14

05 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4618 -gerrit commit 2be53f362139f8f3abd45070038c6cc4395de848 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 5 06:52:11 2014 +0100 sandybridge/igd: Add brightness register descriptions Needed for brightness control for Lenovo X230 Change-Id: Ib6d127d2e050671dd402c31af06ff4726f65156c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/acpi/igd.asl | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl index a6804ad..02eff2e 100644 --- a/src/northbridge/intel/sandybridge/acpi/igd.asl +++ b/src/northbridge/intel/sandybridge/acpi/igd.asl @@ -23,6 +23,23 @@ Device (GFX0) { Name (_ADR, 0x00020000) + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64 + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (0x48254), + BCLV, 16, + Offset (0xc8250), + CR1, 32, + CR2, 32 + } + /* Display Output Switching */ Method (_DOS, 1) {

1 0

Patch set updated for coreboot: 93899e3 sandybridge/igd: Add brightness register descriptions
by Vladimir Serbinenko 05 Jan '14

05 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4618 -gerrit commit 93899e34a99904fe49796f38faa2bc0974468b21 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 5 06:52:11 2014 +0100 sandybridge/igd: Add brightness register descriptions Needed for brightness control for Lenovo X230 Change-Id: Ib6d127d2e050671dd402c31af06ff4726f65156c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/acpi/igd.asl | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl index a6804ad..54fa4d6 100644 --- a/src/northbridge/intel/sandybridge/acpi/igd.asl +++ b/src/northbridge/intel/sandybridge/acpi/igd.asl @@ -23,6 +23,23 @@ Device (GFX0) { Name (_ADR, 0x00020000) + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64 + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (0x48254), + BCLV, 16, + Offset (0xc8250), + CR1, 32, + CR2, 32 + } + /* Display Output Switching */ Method (_DOS, 1) {

1 0

New patch to review for coreboot: 784ed5b Make DRAM GPIO configurable
by Vladimir Serbinenko 05 Jan '14

05 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4622 -gerrit commit 784ed5b04635c542c0ed74799d371fcde8679c95 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 5 11:37:32 2014 +0100 Make DRAM GPIO configurable DRAM gate GPIO is different on different mobos move it to hidden config with 60 (current value) as default. Set it to 10 for Lenovo X201. Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Kconfig | 4 ++++ src/southbridge/intel/bd82x6x/Kconfig | 4 ++++ src/southbridge/intel/bd82x6x/smihandler.c | 32 +++++++++++++++++++---------- src/southbridge/intel/ibexpeak/Kconfig | 4 ++++ src/southbridge/intel/ibexpeak/smihandler.c | 32 +++++++++++++++++++---------- 5 files changed, 54 insertions(+), 22 deletions(-) diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index a2d66b3..dbc80c5 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -43,6 +43,10 @@ config IRQ_SLOT_COUNT int default 18 +config CONFIG_DRAM_GATE_GPIO + int + default 10 + config MAX_CPUS int default 4 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index c2720ef..6a96c5e 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -45,6 +45,10 @@ config EHCI_DEBUG_OFFSET hex default 0xa0 +config DRAM_GATE_GPIO + int + default 60 + config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/bd82x6x/bootblock.c" diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 99f6b51..dc8bf8b 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -305,24 +305,34 @@ static void southbridge_gate_memory_reset(void) if (!gpiobase) return; +#if CONFIG_DRAM_GATE_GPIO >= 32 +#define SUFFIX(x) x ## 2 +#define OFFSET (CONFIG_DRAM_GATE_GPIO - 32) +#else +#define SUFFIX(x) x +#define OFFSET (CONFIG_DRAM_GATE_GPIO) +#endif + /* Make sure it is set as GPIO */ - reg32 = inl(gpiobase + GPIO_USE_SEL2); - if (!(reg32 & (1 << 28))) { - reg32 |= (1 << 28); - outl(reg32, gpiobase + GPIO_USE_SEL2); + reg32 = inl(gpiobase + SUFFIX(GPIO_USE_SEL)); + if (!(reg32 & (1 << OFFSET))) { + reg32 |= (1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GPIO_USE_SEL)); } /* Make sure it is set as output */ - reg32 = inl(gpiobase + GP_IO_SEL2); - if (reg32 & (1 << 28)) { - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_IO_SEL2); + reg32 = inl(gpiobase + SUFFIX(GP_IO_SEL)); + if (reg32 & (1 << OFFSET)) { + reg32 &= ~(1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GP_IO_SEL)); } /* Drive the output low */ - reg32 = inl(gpiobase + GP_LVL2); - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_LVL2); + reg32 = inl(gpiobase + SUFFIX(GP_LVL)); + reg32 &= ~(1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GP_LVL)); +#undef OFFSET +#undef SUFFIX } static void xhci_sleep(u8 slp_typ) diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 07e714b..7e1c4e0 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -43,6 +43,10 @@ config EHCI_DEBUG_OFFSET hex default 0xa0 +config DRAM_GATE_GPIO + int + default 60 + config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/bd82x6x/bootblock.c" diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 5ee8ef9..088c5c2 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -305,24 +305,34 @@ static void southbridge_gate_memory_reset(void) if (!gpiobase) return; +#if CONFIG_DRAM_GATE_GPIO >= 32 +#define SUFFIX(x) x ## 2 +#define OFFSET (CONFIG_DRAM_GATE_GPIO - 32) +#else +#define SUFFIX(x) x +#define OFFSET (CONFIG_DRAM_GATE_GPIO) +#endif + /* Make sure it is set as GPIO */ - reg32 = inl(gpiobase + GPIO_USE_SEL2); - if (!(reg32 & (1 << 28))) { - reg32 |= (1 << 28); - outl(reg32, gpiobase + GPIO_USE_SEL2); + reg32 = inl(gpiobase + SUFFIX(GPIO_USE_SEL)); + if (!(reg32 & (1 << OFFSET))) { + reg32 |= (1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GPIO_USE_SEL)); } /* Make sure it is set as output */ - reg32 = inl(gpiobase + GP_IO_SEL2); - if (reg32 & (1 << 28)) { - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_IO_SEL2); + reg32 = inl(gpiobase + SUFFIX(GP_IO_SEL)); + if (reg32 & (1 << OFFSET)) { + reg32 &= ~(1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GP_IO_SEL)); } /* Drive the output low */ - reg32 = inl(gpiobase + GP_LVL2); - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_LVL2); + reg32 = inl(gpiobase + SUFFIX(GP_LVL)); + reg32 &= ~(1 << OFFSET); + outl(reg32, gpiobase + SUFFIX(GP_LVL)); +#undef OFFSET +#undef SUFFIX } static void xhci_sleep(u8 slp_typ)

1 0

Patch set updated for coreboot: 0690708 sandy/ivy SPI: Support hardware sequencing and use with multiple chips
by Vladimir Serbinenko 05 Jan '14

05 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4613 -gerrit commit 0690708a2f1acf0bb3f6fdf212d01f824bfc4995 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 4 21:00:38 2014 +0100 sandy/ivy SPI: Support hardware sequencing and use with multiple chips When 2 chips are present to get to the second one you have to use hardware sequencing. Also use it as the fallback if chip is unknown. Based on code in flashrom by Stefan Tauner and Carl-Daniel Hailfinger distributed under compatible license. Tested on Lenovo X230 which has EN25QH64 (8M) + N25Q032..3E (4M) Change-Id: I56f3cf0406b5f09fa327ed052c8e8b1df1d8a11f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/mrccache.c | 7 +- src/southbridge/intel/bd82x6x/pch.h | 8 + src/southbridge/intel/bd82x6x/spi.c | 354 ++++++++++++++++++++++++++- src/southbridge/intel/ibexpeak/pch.h | 8 + src/southbridge/intel/ibexpeak/spi.c | 354 ++++++++++++++++++++++++++- 5 files changed, 728 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index e19d2c5..4079b1f 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -192,7 +192,12 @@ static void update_mrc_cache(void *unused) // 1. use spi_flash_probe() to find the flash, then spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + struct spi_flash *flash = 0; + + if (!spi_is_multichip ()) + flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!flash) + flash = spi_flash_hwseq(0, 0, 1000000, SPI_MODE_3); if (!flash) { printk(BIOS_DEBUG, "Could not find SPI device\n"); return; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 90de855..6382481 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -58,6 +58,14 @@ void intel_pch_finalize_smm(void); #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) +int spi_is_multichip(void); +struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); +#endif +#endif + +#if !defined(__ASSEMBLER__) +#if !defined(__PRE_RAM__) #if !defined(__SMM__) #include "chip.h" void pch_enable(device_t dev); diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index ec5d7de..4110d98 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -1,5 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * See file CREDITS for list of people who contributed to this * project. @@ -28,11 +30,20 @@ #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> +#include <device/pci.h> +#include <spi_flash.h> #include <spi-generic.h> +#include "pch.h" #define min(a, b) ((a)<(b)?(a):(b)) +#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ +#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) +#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ +#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) + + #ifdef __SMM__ #include <arch/pci_mmio_cfg.h> #define pci_read_config_byte(dev, reg, targ)\ @@ -115,7 +126,11 @@ typedef struct ich9_spi_regs { typedef struct ich_spi_controller { int locked; + int revision; + uint32_t flmap0; + uint32_t hsfs; + ich9_spi_regs *ich9_spi; uint8_t *opmenu; int menubytes; uint16_t *preop; @@ -356,6 +371,7 @@ void spi_init(void) pci_read_config_dword(dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); + cntlr.revision = ich_version; switch (ich_version) { case 7: { @@ -381,7 +397,11 @@ void spi_init(void) const uint16_t ich9_spibar_offset = 0x3800; ich9_spi_regs *ich9_spi = (ich9_spi_regs *)(rcrb + ich9_spibar_offset); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + uint16_t hsfs; + cntlr.ich9_spi = ich9_spi; + hsfs = readw_(&ich9_spi->hsfs); + ichspi_lock = hsfs & HSFS_FLOCKDN; + cntlr.hsfs = hsfs; cntlr.opmenu = ich9_spi->opmenu; cntlr.menubytes = sizeof(ich9_spi->opmenu); cntlr.optype = &ich9_spi->optype; @@ -392,6 +412,12 @@ void spi_init(void) cntlr.control = (uint16_t *)ich9_spi->ssfc; cntlr.bbar = &ich9_spi->bbar; cntlr.preop = &ich9_spi->preop; + + if (cntlr.hsfs & HSFS_FDV) + { + writel_ (4, &ich9_spi->fdoc); + cntlr.flmap0 = readl_(&ich9_spi->fdod); + } break; } default: @@ -591,6 +617,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) return -1; } +int spi_is_multichip (void) +{ + if (cntlr.revision != 9) + return 0; + if (!(cntlr.hsfs & HSFS_FDV)) + return 0; + return !!((cntlr.flmap0 >> 8) & 3); +} + int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, void *din, unsigned int bitsin) { @@ -743,3 +778,320 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return 0; } + +/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; + writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + timeout /= 8; /* scale timeout duration to counter */ + while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + udelay(8); + } + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + if (!timeout) { + uint16_t hsfc; + addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&cntlr.ich9_spi->hsfc); + printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " + "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", + addr, addr + len - 1, addr, len - 1, + hsfc, hsfs); + return 1; + } + + if (hsfs & HSFS_FCERR) { + uint16_t hsfc; + addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&cntlr.ich9_spi->hsfc); + printk(BIOS_ERR, "Transaction error between offset 0x%08x and " + "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", + addr, addr + len - 1, addr, len - 1, + hsfc, hsfs); + return 1; + } + return 0; +} + + +static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + u32 start, end, erase_size; + int ret; + uint16_t hsfc; + uint16_t timeout = 1000 * 60; + + erase_size = flash->sector_size; + if (offset % erase_size || len % erase_size) { + printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); + return -1; + } + + flash->spi->rw = SPI_WRITE_FLAG; + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); + return ret; + } + + start = offset; + end = start + len; + + while (offset < end) { + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + ich_hwseq_set_addr(offset); + + offset += erase_size; + + hsfc = readw_(&cntlr.ich9_spi->hsfc); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + writew_(hsfc, &cntlr.ich9_spi->hsfc); + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + { + printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); + ret = -1; + goto out; + } + } + + printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); + +out: + spi_release_bus(flash->spi); + return ret; +} + +static void ich_read_data(uint8_t *data, int len) +{ + int i; + uint32_t temp32 = 0; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = readl_(cntlr.data + i); + + data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; + } +} + +static int ich_hwseq_read(struct spi_flash *flash, + u32 addr, size_t len, void *buf) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr + len > flash->size) { + printk (BIOS_ERR, + "Attempt to read %x-%x which is out of chip\n", + (unsigned) addr, + (unsigned) addr+(unsigned) len); + return -1; + } + + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + while (len > 0) { + block_len = min(len, cntlr.databytes); + if (block_len > (~addr & 0xff)) + block_len = (~addr & 0xff) + 1; + ich_hwseq_set_addr(addr); + hsfc = readw_(&cntlr.ich9_spi->hsfc); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + writew_(hsfc, &cntlr.ich9_spi->hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +/* Fill len bytes from the data array into the fdata/spid registers. + * + * Note that using len > flash->pgm->spi.max_data_write will trash the registers + * following the data registers. + */ +static void ich_fill_data(const uint8_t *data, int len) +{ + uint32_t temp32 = 0; + int i; + + if (len <= 0) + return; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = 0; + + temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + + if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ + writel_(temp32, cntlr.data + (i - (i % 4))); + } + i--; + if ((i % 4) != 3) /* Write remaining data to regs. */ + writel_(temp32, cntlr.data + (i - (i % 4))); +} + +static int ich_hwseq_write(struct spi_flash *flash, + u32 addr, size_t len, const void *buf) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + uint32_t start = addr; + + if (addr + len > flash->size) { + printk (BIOS_ERR, + "Attempt to write 0x%x-0x%x which is out of chip\n", + (unsigned)addr, (unsigned) (addr+len)); + return -1; + } + + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + while (len > 0) { + block_len = min(len, cntlr.databytes); + if (block_len > (~addr & 0xff)) + block_len = (~addr & 0xff) + 1; + + ich_hwseq_set_addr(addr); + + ich_fill_data(buf, block_len); + hsfc = readw_(&cntlr.ich9_spi->hsfc); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + writew_(hsfc, &cntlr.ich9_spi->hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + { + printk (BIOS_ERR, "SF: write failure at %x\n", + addr); + return -1; + } + addr += block_len; + buf += block_len; + len -= block_len; + } + printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", + (unsigned) (addr - start), start); + return 0; +} + + +struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + struct spi_flash *flash = NULL; + int ret; + + if (cntlr.revision != 9) { + printk(BIOS_WARNING, "SF: Unsupported revision %x\n", + cntlr.revision); + return NULL; + } + + flash = malloc(sizeof(*flash)); + if (!flash) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + printk(BIOS_WARNING, "SF: Failed to set up slave\n"); + free (flash); + return NULL; + } + + spi->rw = SPI_READ_FLAG; + ret = spi_claim_bus(spi); + if (ret) { + printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret); + free (flash); + return NULL; + } + + flash->spi = spi; + flash->name = "Opaque HW-sequencing"; + + flash->write = ich_hwseq_write; + flash->erase = ich_hwseq_erase; + flash->read = ich_hwseq_read; + ich_hwseq_set_addr (0); + switch ((cntlr.hsfs >> 3) & 3) + { + case 0: + flash->sector_size = 256; + break; + case 1: + flash->sector_size = 4096; + break; + case 2: + flash->sector_size = 8192; + break; + case 3: + flash->sector_size = 65536; + break; + } + + uint32_t flcomp; + + writel_ (0x1000, &cntlr.ich9_spi->fdoc); + flcomp = readl_(&cntlr.ich9_spi->fdod); + + flash->size = 1 << (19 + (flcomp & 7)); + + if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3)) + flash->size += 1 << (19 + ((flcomp >> 3) & 7)); + printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); + +#if CONFIG_SMM_TSEG && defined(__SMM__) + /* Ensure flash handlers are valid for TSEG */ + tseg_relocate((void **)&flash->read); + tseg_relocate((void **)&flash->write); + tseg_relocate((void **)&flash->erase); + tseg_relocate((void **)&flash->name); +#endif + + printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n", + flash->name, flash->sector_size, flash->size); + + spi_release_bus(spi); + + return flash; +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 356dd8a..2728b54 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -59,6 +59,14 @@ void intel_pch_finalize_smm(void); #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) +int spi_is_multichip(void); +struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); +#endif +#endif + +#if !defined(__ASSEMBLER__) +#if !defined(__PRE_RAM__) #if !defined(__SMM__) #include "chip.h" void pch_enable(device_t dev); diff --git a/src/southbridge/intel/ibexpeak/spi.c b/src/southbridge/intel/ibexpeak/spi.c index e263b7f..9d064c3 100644 --- a/src/southbridge/intel/ibexpeak/spi.c +++ b/src/southbridge/intel/ibexpeak/spi.c @@ -1,5 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * See file CREDITS for list of people who contributed to this * project. @@ -28,11 +30,20 @@ #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> +#include <device/pci.h> +#include <spi_flash.h> #include <spi-generic.h> +#include "pch.h" #define min(a, b) ((a)<(b)?(a):(b)) +#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ +#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) +#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ +#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) + + #ifdef __SMM__ #include <arch/pci_mmio_cfg.h> #define pci_read_config_byte(dev, reg, targ)\ @@ -115,7 +126,11 @@ typedef struct ich9_spi_regs { typedef struct ich_spi_controller { int locked; + int revision; + uint32_t flmap0; + uint32_t hsfs; + ich9_spi_regs *ich9_spi; uint8_t *opmenu; int menubytes; uint16_t *preop; @@ -357,6 +372,7 @@ void spi_init(void) pci_read_config_dword(dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); + cntlr.revision = ich_version; switch (ich_version) { case 7: { @@ -382,7 +398,11 @@ void spi_init(void) const uint16_t ich9_spibar_offset = 0x3800; ich9_spi_regs *ich9_spi = (ich9_spi_regs *)(rcrb + ich9_spibar_offset); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + uint16_t hsfs; + cntlr.ich9_spi = ich9_spi; + hsfs = readw_(&ich9_spi->hsfs); + ichspi_lock = hsfs & HSFS_FLOCKDN; + cntlr.hsfs = hsfs; cntlr.opmenu = ich9_spi->opmenu; cntlr.menubytes = sizeof(ich9_spi->opmenu); cntlr.optype = &ich9_spi->optype; @@ -393,6 +413,12 @@ void spi_init(void) cntlr.control = (uint16_t *)ich9_spi->ssfc; cntlr.bbar = &ich9_spi->bbar; cntlr.preop = &ich9_spi->preop; + + if (cntlr.hsfs & HSFS_FDV) + { + writel_ (4, &ich9_spi->fdoc); + cntlr.flmap0 = readl_(&ich9_spi->fdod); + } break; } default: @@ -592,6 +618,15 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) return -1; } +int spi_is_multichip (void) +{ + if (cntlr.revision != 9) + return 0; + if (!(cntlr.hsfs & HSFS_FDV)) + return 0; + return !!((cntlr.flmap0 >> 8) & 3); +} + int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, void *din, unsigned int bitsin) { @@ -744,3 +779,320 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return 0; } + +/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; + writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + timeout /= 8; /* scale timeout duration to counter */ + while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + udelay(8); + } + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + if (!timeout) { + uint16_t hsfc; + addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&cntlr.ich9_spi->hsfc); + printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " + "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", + addr, addr + len - 1, addr, len - 1, + hsfc, hsfs); + return 1; + } + + if (hsfs & HSFS_FCERR) { + uint16_t hsfc; + addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&cntlr.ich9_spi->hsfc); + printk(BIOS_ERR, "Transaction error between offset 0x%08x and " + "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", + addr, addr + len - 1, addr, len - 1, + hsfc, hsfs); + return 1; + } + return 0; +} + + +static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + u32 start, end, erase_size; + int ret; + uint16_t hsfc; + uint16_t timeout = 1000 * 60; + + erase_size = flash->sector_size; + if (offset % erase_size || len % erase_size) { + printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); + return -1; + } + + flash->spi->rw = SPI_WRITE_FLAG; + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); + return ret; + } + + start = offset; + end = start + len; + + while (offset < end) { + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + ich_hwseq_set_addr(offset); + + offset += erase_size; + + hsfc = readw_(&cntlr.ich9_spi->hsfc); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + writew_(hsfc, &cntlr.ich9_spi->hsfc); + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + { + printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); + ret = -1; + goto out; + } + } + + printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); + +out: + spi_release_bus(flash->spi); + return ret; +} + +static void ich_read_data(uint8_t *data, int len) +{ + int i; + uint32_t temp32 = 0; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = readl_(cntlr.data + i); + + data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; + } +} + +static int ich_hwseq_read(struct spi_flash *flash, + u32 addr, size_t len, void *buf) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr + len > flash->size) { + printk (BIOS_ERR, + "Attempt to read %x-%x which is out of chip\n", + (unsigned) addr, + (unsigned) addr+(unsigned) len); + return -1; + } + + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + while (len > 0) { + block_len = min(len, cntlr.databytes); + if (block_len > (~addr & 0xff)) + block_len = (~addr & 0xff) + 1; + ich_hwseq_set_addr(addr); + hsfc = readw_(&cntlr.ich9_spi->hsfc); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + writew_(hsfc, &cntlr.ich9_spi->hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +/* Fill len bytes from the data array into the fdata/spid registers. + * + * Note that using len > flash->pgm->spi.max_data_write will trash the registers + * following the data registers. + */ +static void ich_fill_data(const uint8_t *data, int len) +{ + uint32_t temp32 = 0; + int i; + + if (len <= 0) + return; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = 0; + + temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + + if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ + writel_(temp32, cntlr.data + (i - (i % 4))); + } + i--; + if ((i % 4) != 3) /* Write remaining data to regs. */ + writel_(temp32, cntlr.data + (i - (i % 4))); +} + +static int ich_hwseq_write(struct spi_flash *flash, + u32 addr, size_t len, const void *buf) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + uint32_t start = addr; + + if (addr + len > flash->size) { + printk (BIOS_ERR, + "Attempt to write 0x%x-0x%x which is out of chip\n", + (unsigned)addr, (unsigned) (addr+len)); + return -1; + } + + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + + while (len > 0) { + block_len = min(len, cntlr.databytes); + if (block_len > (~addr & 0xff)) + block_len = (~addr & 0xff) + 1; + + ich_hwseq_set_addr(addr); + + ich_fill_data(buf, block_len); + hsfc = readw_(&cntlr.ich9_spi->hsfc); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + writew_(hsfc, &cntlr.ich9_spi->hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + { + printk (BIOS_ERR, "SF: write failure at %x\n", + addr); + return -1; + } + addr += block_len; + buf += block_len; + len -= block_len; + } + printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", + (unsigned) (addr - start), start); + return 0; +} + + +struct spi_flash *spi_flash_hwseq(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + struct spi_flash *flash = NULL; + int ret; + + if (cntlr.revision != 9) { + printk(BIOS_WARNING, "SF: Unsupported revision %x\n", + cntlr.revision); + return NULL; + } + + flash = malloc(sizeof(*flash)); + if (!flash) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + printk(BIOS_WARNING, "SF: Failed to set up slave\n"); + free (flash); + return NULL; + } + + spi->rw = SPI_READ_FLAG; + ret = spi_claim_bus(spi); + if (ret) { + printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret); + free (flash); + return NULL; + } + + flash->spi = spi; + flash->name = "Opaque HW-sequencing"; + + flash->write = ich_hwseq_write; + flash->erase = ich_hwseq_erase; + flash->read = ich_hwseq_read; + ich_hwseq_set_addr (0); + switch ((cntlr.hsfs >> 3) & 3) + { + case 0: + flash->sector_size = 256; + break; + case 1: + flash->sector_size = 4096; + break; + case 2: + flash->sector_size = 8192; + break; + case 3: + flash->sector_size = 65536; + break; + } + + uint32_t flcomp; + + writel_ (0x1000, &cntlr.ich9_spi->fdoc); + flcomp = readl_(&cntlr.ich9_spi->fdod); + + flash->size = 1 << (19 + (flcomp & 7)); + + if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3)) + flash->size += 1 << (19 + ((flcomp >> 3) & 7)); + printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); + +#if CONFIG_SMM_TSEG && defined(__SMM__) + /* Ensure flash handlers are valid for TSEG */ + tseg_relocate((void **)&flash->read); + tseg_relocate((void **)&flash->write); + tseg_relocate((void **)&flash->erase); + tseg_relocate((void **)&flash->name); +#endif + + printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n", + flash->name, flash->sector_size, flash->size); + + spi_release_bus(spi); + + return flash; +}

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New patch to review for coreboot: 2406da8 CBMEM: Fix allocation for static CBMEM
by Kyösti Mälkki 05 Jan '14

05 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4621 -gerrit commit 2406da8b16f0cf5adbfb007e0c01258b4b0613d5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 4 09:42:02 2014 +0200 CBMEM: Fix allocation for static CBMEM CBMEM console buffer size is adjustable in menuconfig, but this would not correctly adjust the overall allocation made for CBMEM. HIGH_MEMORY_SIZE is aligned to 64kB and definitions are moved down in the header file as HIGH_MEMORY_SIZE is not used with DYNAMIC_CBMEM. Try to continue boot even if CBMEM cannot be created. This error would only occur during development of new ports anyways and more log output is better. Change-Id: I4ee2df601b12ab6532ffcae8897775ecaa2fc05f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 1 + src/include/cbmem.h | 30 ++++++++++++++++++------------ src/lib/cbmem.c | 9 +++------ 3 files changed, 22 insertions(+), 18 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 0152018..c2d9a2e 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -15,6 +15,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ +#include <stdlib.h> #include <console/console.h> #include <cbmem.h> #include <arch/acpi.h> diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 746f40c..5f1ac3c 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -21,13 +21,6 @@ #ifndef _CBMEM_H_ #define _CBMEM_H_ -/* Reserve 128k for ACPI and other tables */ -#if CONFIG_CONSOLE_CBMEM -#define HIGH_MEMORY_DEF_SIZE ( 256 * 1024 ) -#else -#define HIGH_MEMORY_DEF_SIZE ( 128 * 1024 ) -#endif - #if CONFIG_HAVE_ACPI_RESUME #if CONFIG_RELOCATABLE_RAMSTAGE #define HIGH_MEMORY_SAVE 0 @@ -35,16 +28,11 @@ #define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) #endif -#define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + CONFIG_HIGH_SCRATCH_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) - /* Delegation of resume backup memory so we don't have to * (slowly) handle backing up OS memory in romstage.c */ #define CBMEM_BOOT_MODE 0x610 #define CBMEM_RESUME_BACKUP 0x614 - -#else /* CONFIG_HAVE_ACPI_RESUME */ -#define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE #endif /* CONFIG_HAVE_ACPI_RESUME */ #define CBMEM_ID_FREESPACE 0x46524545 @@ -130,6 +118,24 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry); #else /* !CONFIG_DYNAMIC_CBMEM */ +/* Allocation with static CBMEM is resolved at build time. We start + * with 128kB and conditionally add some of the most greedy CBMEM + * table entries. + */ +#define _CBMEM_SZ_MINIMAL ( 128 * 1024 ) + +#if CONFIG_HAVE_ACPI_RESUME +#define _CBMEM_SZ_RESUME (HIGH_MEMORY_SAVE + CONFIG_HIGH_SCRATCH_MEMORY_SIZE) +#else +#define _CBMEM_SZ_RESUME 0 +#endif + +#define _CBMEM_SZ_TOTAL \ + (_CBMEM_SZ_MINIMAL + _CBMEM_SZ_RESUME + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE) + +#define HIGH_MEMORY_SIZE ALIGN_UP(_CBMEM_SZ_TOTAL, 0x10000) + + #ifndef __PRE_RAM__ void set_top_of_ram(uint64_t ramtop); void backup_top_of_ram(uint64_t ramtop); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 6b0cbc8..5d6f41d 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -104,13 +104,10 @@ static void cbmem_init(void) cbmem_locate_table(&baseaddr, &size); cbmem_trace_location(baseaddr, size, __FUNCTION__); - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - - if (size < (64 * 1024)) { - printk(BIOS_DEBUG, "Increase CBMEM size!\n"); - for (;;) ; - } + if (!(baseaddr && size)) + return; + cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); cbmem_toc[0] = (struct cbmem_entry) {

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New patch to review for coreboot: 84a3765 CBMEM: Drop cbmem_base_check()
by Kyösti Mälkki 05 Jan '14

05 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4620 -gerrit commit 84a37651e08063d543dcc8ec72224a9eb14058df Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jan 5 08:49:29 2014 +0200 CBMEM: Drop cbmem_base_check() This function was for logging only, but we have both base and size already logged elsewhere. Change-Id: Ie6ac71fc859b8fd42fcf851c316a5f888f828dc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/tables.c | 4 ---- src/arch/x86/boot/tables.c | 4 ---- src/include/cbmem.h | 1 - src/lib/cbmem.c | 11 ----------- 4 files changed, 20 deletions(-) diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c index 3f5338c..7e7cbe4 100644 --- a/src/arch/armv7/tables.c +++ b/src/arch/armv7/tables.c @@ -50,10 +50,6 @@ struct lb_memory *write_tables(void) { unsigned long table_pointer, new_table_pointer; -#if !CONFIG_DYNAMIC_CBMEM - cbmem_base_check(); -#endif - post_code(0x9d); table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index eea9bf1..40bf087 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -50,10 +50,6 @@ struct lb_memory *write_tables(void) */ unsigned long high_table_pointer; -#if !CONFIG_DYNAMIC_CBMEM - cbmem_base_check(); -#endif - rom_table_start = 0xf0000; rom_table_end = 0xf0000; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index f9d268a..746f40c 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -134,7 +134,6 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry); void set_top_of_ram(uint64_t ramtop); void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); -int cbmem_base_check(void); #endif int cbmem_reinit(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index e6d3913..6b0cbc8 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -256,17 +256,6 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { init_cbmem_post_device, NULL), }; -int cbmem_base_check(void) -{ - if (!cbmem_base) { - printk(BIOS_ERR, "ERROR: CBMEM Base is not set.\n"); - // Are there any boards without? - // Stepan thinks we should die() here! - } - printk(BIOS_DEBUG, "CBMEM Base is %llx.\n", cbmem_base); - return !!cbmem_base; -} - void cbmem_add_lb_mem(struct lb_memory *mem) { lb_add_memory_range(mem, LB_MEM_TABLE, cbmem_base, cbmem_size);

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New patch to review for coreboot: 3eb16ab CBMEM ACPI: Move resume handler
by Kyösti Mälkki 05 Jan '14

05 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4619 -gerrit commit 3eb16abf89b9426669200620fa5b188051415c7d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 3 15:15:22 2014 +0200 CBMEM ACPI: Move resume handler Handler is ACPI/x86 specific so move details out of cbmem code. With static CBMEM initialisation, ramstage will need to test for S3 wakeup condition so publish also acpi_is_wakeup(). Change-Id: If591535448cdd24a54262b534c1a828fc13da759 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/tables.c | 4 ++++ src/arch/x86/boot/acpi.c | 8 +++++++- src/arch/x86/boot/cbmem.c | 15 +++++++++++++++ src/arch/x86/include/arch/acpi.h | 2 ++ src/include/cbmem.h | 2 ++ src/lib/cbmem.c | 6 +----- src/lib/dynamic_cbmem.c | 15 +-------------- 7 files changed, 32 insertions(+), 20 deletions(-) diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c index cf4e4e0..3f5338c 100644 --- a/src/arch/armv7/tables.c +++ b/src/arch/armv7/tables.c @@ -42,6 +42,10 @@ void cbmem_arch_init(void) { } +void cbmem_fail_resume(void) +{ +} + struct lb_memory *write_tables(void) { unsigned long table_pointer, new_table_pointer; diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 96cb270..0e09ec5 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -645,12 +645,18 @@ void acpi_resume(void *wake_vec) /* This is to be filled by SB code - startup value what was found. */ u8 acpi_slp_type = 0; -static int acpi_is_wakeup(void) +int acpi_is_wakeup(void) { /* Both resume from S2 and resume from S3 restart at CPU reset */ return (acpi_slp_type == 3 || acpi_slp_type == 2); } +void acpi_fail_wakeup(void) +{ + if (acpi_slp_type == 3 || acpi_slp_type == 2) + acpi_slp_type = 0; +} + static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp) { if (strncmp((char *)rsdp, RSDP_SIG, sizeof(RSDP_SIG) - 1) != 0) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index bdc695c..0152018 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <cbmem.h> +#include <arch/acpi.h> #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) @@ -64,3 +65,17 @@ void *cbmem_top(void) } #endif /* DYNAMIC_CBMEM */ + +#if !defined(__PRE_RAM__) + +/* ACPI resume needs to be cleared in the fail-to-recover case, but that + * condition is only handled during ramstage. */ +void cbmem_fail_resume(void) +{ +#if CONFIG_HAVE_ACPI_RESUME + /* Something went wrong, our high memory area got wiped */ + acpi_fail_wakeup(); +#endif +} + +#endif /* !__PRE_RAM__ */ diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 306f7da..d73c046 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -558,6 +558,8 @@ void acpi_save_gnvs(u32 gnvs_address); /* 0 = S0, 1 = S1 ...*/ extern u8 acpi_slp_type; +int acpi_is_wakeup(void); +void acpi_fail_wakeup(void); void acpi_resume(void *wake_vec); void __attribute__((weak)) mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 0c32111..f9d268a 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -166,8 +166,10 @@ void cbmem_add_lb_mem(struct lb_memory *mem); void cbmem_list(void); void cbmem_arch_init(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); +void cbmem_fail_resume(void); #else static inline void cbmem_arch_init(void) {} +static inline void cbmem_fail_resume(void) {} #endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 6449b55..e6d3913 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -228,12 +228,8 @@ int cbmem_initialize(void) /* We expect the romstage to always initialize it. */ if (!cbmem_reinit()) { -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) - /* Something went wrong, our high memory area got wiped */ - if (acpi_slp_type == 3 || acpi_slp_type == 2) - acpi_slp_type = 0; -#endif cbmem_init(); + cbmem_fail_resume(); rv = 1; } #ifndef __PRE_RAM__ diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index b934aed..0ab8f81 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -32,19 +32,6 @@ #define UINT_MAX 4294967295U #endif -/* ACPI resume needs to be cleared in the fail-to-recover case, but that - * condition is only handled during ramstage. */ -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) -static inline void cbmem_handle_acpi_resume(void) -{ - /* Something went wrong, our high memory area got wiped */ - if (acpi_slp_type == 3 || acpi_slp_type == 2) - acpi_slp_type = 0; -} -#else -static inline void cbmem_handle_acpi_resume(void) {} -#endif - /* * The dynamic cbmem code uses a root region. The root region boundary * addresses are determined by cbmem_top() and ROOT_MIN_SIZE. Just below @@ -191,7 +178,7 @@ void cbmem_initialize_empty(void) static inline int cbmem_fail_recovery(void) { cbmem_initialize_empty(); - cbmem_handle_acpi_resume(); + cbmem_fail_resume(); /* Migrate cache-as-ram variables. */ car_migrate_variables(); return 1;

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coreboot-gerrit January 2014