coreboot-gerrit July 2013

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New patch to review for coreboot: b51b382 emulation/qemu-q35: Use MMCONF_SUPPORT_DEFAULT
by Kyösti Mälkki 04 Jul '13

04 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3599 -gerrit commit b51b3820484f4839168ae964f52e20070f712111 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jul 3 08:06:32 2013 +0300 emulation/qemu-q35: Use MMCONF_SUPPORT_DEFAULT Change all PCI configuration accesses to MMIO in qemu-q35 emulation To enable MMIO style access, add (move) explicit PCI IO config write in the bootblock. As there is no northbridge/x/x/bootblock.c file, a mainboard/x/x/bootblock.c file is added for this purpose. Change-Id: I979efb3d9b2f359a9ccbd1b4f6c05f83bab43007 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/emulation/qemu-q35/Kconfig | 9 ++++++++ src/mainboard/emulation/qemu-q35/bootblock.c | 33 ++++++++++++++++++++++++++++ src/mainboard/emulation/qemu-q35/mainboard.c | 6 +---- 3 files changed, 43 insertions(+), 5 deletions(-) diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 7f33699..9d78bb8 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801IX select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select CACHE_AS_RAM # select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE @@ -24,10 +25,18 @@ config MAINBOARD_PART_NUMBER string default "QEMU x86 q35/ich9" +config BOOTBLOCK_MAINBOARD_INIT + string + default "mainboard/emulation/qemu-q35/bootblock.c" + #config IRQ_SLOT_COUNT # int # default 6 +config MMCONF_BASE_ADDRESS + hex + default 0xb0000000 + config DCACHE_RAM_BASE hex default 0xd0000 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c new file mode 100644 index 0000000..939a4e6 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -0,0 +1,33 @@ +#include <arch/io.h> + +/* Just define these here, there is no gm35.h file to include. */ +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); +} + +static void bootblock_mainboard_init(void) +{ + bootblock_northbridge_init(); + bootblock_southbridge_init(); +} diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 3740064..78c92a9 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -27,7 +27,6 @@ #include <console/console.h> #define Q35_PAM0 0x90 -#define Q35_PCIEXBAR_ADDR 0xb0000000 static const unsigned char qemu_q35_irqs[] = { 10, 10, 11, 11, @@ -59,9 +58,6 @@ static void qemu_nb_init(device_t dev) /* setup IRQ routing southbridge devices */ for (i = 25; i < 32; i++) pci_assign_irqs(0, i, qemu_q35_irqs); - - /* setup mmconfig */ - pci_write_config32(dev, 0x60, Q35_PCIEXBAR_ADDR | 1); } static void qemu_nb_read_resources(struct device *dev) @@ -69,7 +65,7 @@ static void qemu_nb_read_resources(struct device *dev) pci_dev_read_resources(dev); /* reserve mmconfig */ - fixed_mem_resource(dev, 2, Q35_PCIEXBAR_ADDR >> 10, 0x10000000 >> 10, + fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10, IORESOURCE_RESERVE); }

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New patch to review for coreboot: 67c421e Move select MMCONF_SUPPORT under northbridge (fix)
by Kyösti Mälkki 04 Jul '13

04 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3598 -gerrit commit 67c421e854fede03f3eccef3292ad21f46c93427 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 2 11:37:35 2013 +0300 Move select MMCONF_SUPPORT under northbridge (fix) I missed the board with gm45 when I moved MMCONF_SUPPORT lines. Also, the intel/i3100 does not have MMCONF_SUPPORT implemented even though it was previously selected for intel/eagleheights board. Change-Id: I9c7f6b0a150b4d54288a1e015277b9d98467fca4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/roda/rk9/Kconfig | 1 - src/northbridge/intel/gm45/Kconfig | 1 + src/northbridge/intel/i3100/Kconfig | 1 - 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index 4bf9088..59ae455 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_GM45 select SOUTHBRIDGE_INTEL_I82801IX select SUPERIO_SMSC_LPC47N227 - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_4096 select RTL8168_ROM_DISABLE select DRIVERS_GENERIC_IOAPIC diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 34b2544..16a0bf1 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -25,6 +25,7 @@ if NORTHBRIDGE_INTEL_GM45 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP + select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select IOMMU diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 2bb1a25..079004b 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,6 +1,5 @@ config NORTHBRIDGE_INTEL_I3100 bool - select MMCONF_SUPPORT if NORTHBRIDGE_INTEL_I3100 config DIMM_MAP_LOGICAL

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Patch merged into coreboot/master: 032c23d intel/i945: Use MMCONF_SUPPORT_DEFAULT
by gerrit＠coreboot.org 04 Jul '13

04 Jul '13

the following patch was just integrated into master: commit 032c23db08e6f0c6a2937092edafa26339aa4921 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 1 11:21:53 2013 +0300 intel/i945: Use MMCONF_SUPPORT_DEFAULT Change all PCI configuration accesses to MMIO on all boards with i945 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3584 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Nico Huber <nico.huber(a)secunet.com> See http://review.coreboot.org/3584 for details. -gerrit

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Patch merged into coreboot/master: fbdb085 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
by gerrit＠coreboot.org 04 Jul '13

04 Jul '13

the following patch was just integrated into master: commit fbdb085549b6c500e12dc2fb21143a197b4be042 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 1 11:21:53 2013 +0300 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT Change all PCI configuration accesses to MMIO on all boards with SandyBridge and IvyBridge. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3576 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber(a)secunet.com> See http://review.coreboot.org/3576 for details. -gerrit

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Patch merged into coreboot/master: 15c4ab7 Move select MMCONF_SUPPORT under northbridge
by gerrit＠coreboot.org 03 Jul '13

03 Jul '13

the following patch was just integrated into master: commit 15c4ab7adf594e0707cdedded8fe6797b17da56a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 2 11:37:35 2013 +0300 Move select MMCONF_SUPPORT under northbridge Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as that feature originates from northbridge and cannot be disabled for a single mainboard. Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3589 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3589 for details. -gerrit

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Patch merged into coreboot/master: 00bf647 Add support for DMP Vortex86EX PCI southbridge.
by gerrit＠coreboot.org 03 Jul '13

03 Jul '13

the following patch was just integrated into master: commit 00bf647bf6a980e8b9c3d8d91d79859c9b3de0a1 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Jun 26 21:24:59 2013 +0800 Add support for DMP Vortex86EX PCI southbridge. Change-Id: Iad11cb1b22e9d1e2953b12221541b1478cad9665 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-on: http://review.coreboot.org/3547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3547 for details. -gerrit

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Patch merged into coreboot/master: dd94fa9 winbond/w83627dhg: Fix logical device power down in ACPI
by gerrit＠coreboot.org 03 Jul '13

03 Jul '13

the following patch was just integrated into master: commit dd94fa93b403a73cc7d7b282eb6cefeb27512d13 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Jul 1 16:29:16 2013 +0200 winbond/w83627dhg: Fix logical device power down in ACPI The W83627DHG has some power managements bits to power down individual logical devices. These are called `* Power Down`. Counterintuitively and in contrast to `Immediate Power Down` (bit to power down the whole chip), these bits are set when the respective logical device is powered. Unfortunately, our ACPI code set them wrong which led to disabled devices after a S3 suspend/resume. Adding an option how to set the PM bits and setting them to zero for the W83627DHG, corrects it. Tested with kontron/ktqm77. Change-Id: I8a472d480d4277721bd17c9f7c2ce44fa84e8ae2 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3590 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3590 for details. -gerrit

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Patch merged into filo/master: 955261a Update help text for flash lock
by gerrit＠coreboot.org 03 Jul '13

03 Jul '13

the following patch was just integrated into master: commit 955261a040d1ee1e9b2b0ae3286a3415c29d07c6 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Jul 3 15:39:47 2013 +0200 Update help text for flash lock Update the help text for the FLASHROM_LOCKDOWN option to reflect the current state of supported platforms. Change-Id: I9f8b13887b188d973a07b46b9948de5f5ad4435e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3596 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3596 for details. -gerrit

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Patch merged into filo/master: 0797d1a Refactor flash locking for supported Intel chipsets
by gerrit＠coreboot.org 03 Jul '13

03 Jul '13

the following patch was just integrated into master: commit 0797d1ae1957d83f471e4051a17b5db4e75d56ad Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Jul 3 15:10:58 2013 +0200 Refactor flash locking for supported Intel chipsets This should make things more readable when support for more chipsets comes. Change-Id: I6df6673fa1961ab20796210577950e7be6c12316 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3595 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3595 for details. -gerrit

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New patch to review for filo: c439e0d Add support for flash lock on Cougar / Panther Point
by Nico Huber 03 Jul '13

03 Jul '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3597 -gerrit commit c439e0d2502218ba7ae66837fc8c6ffd7fe6cdfe Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Jul 3 15:12:50 2013 +0200 Add support for flash lock on Cougar / Panther Point Add PCI IDs for Cougar Point and Panther Point PCHs and lock their SPI interface like we do it in coreboot's resume path. We write a valid opcode menu but set all flash regions to read only. The regions are strapped from the flash descriptor. Change-Id: Ie5735cff02564822139f45666c1f28b080a9c6d3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- Config.in | 1 + drivers/intel.c | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 101 insertions(+), 1 deletion(-) diff --git a/Config.in b/Config.in index 08ac0ec..cc48bd3 100644 --- a/Config.in +++ b/Config.in @@ -196,6 +196,7 @@ config FLASHROM_LOCKDOWN o Intel ICH7 (FWH) o Intel ICH9 (FWH + SPI) + o Intel Cougar Point / Panther Point PCH (FWH + SPI) o AMD SB600 (SPI by locking the flash chip itself) endmenu diff --git a/drivers/intel.c b/drivers/intel.c index d2153b7..90811de 100644 --- a/drivers/intel.c +++ b/drivers/intel.c @@ -45,10 +45,53 @@ #define ICH9_SPI_HSFS 0x3804 #define ICH9_SPI_HSFS_FLOCKDN (1 << 15); +#define ICH9_SPI_FLASH_REGIONS 5 +#define ICH9_SPI_FREG0 0x3854 +#define ICH9_SPI_FPR0 0x3874 #define ICH9_SPI_PREOP 0x3894 #define ICH9_SPI_OPTYPE 0x3896 #define ICH9_SPI_OPMENU 0x3898 +/* + * SPI Opcode Menu setup for SPIBAR lockdown + * should support most common flash chips. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ + static void lockdown_flash_ich7(void) { u8 reg8; @@ -80,6 +123,24 @@ static void lockdown_flash_ich9_empty_ops(void) RCBA16(ICH9_SPI_HSFS) |= ICH9_SPI_HSFS_FLOCKDN; } +static void lockdown_flash_ich9_lock_regions(void) +{ + /* Lock SPI interface with the opcodes coreboot uses */ + RCBA16(ICH9_SPI_PREOP) = SPI_OPPREFIX; + RCBA16(ICH9_SPI_OPTYPE) = SPI_OPTYPE; + RCBA32(ICH9_SPI_OPMENU + 0) = SPI_OPMENU_LOWER; + RCBA32(ICH9_SPI_OPMENU + 4) = SPI_OPMENU_UPPER; + + /* Copy flash regions from FREG0-4 to FPR0-4 + and enable write protection bit31 */ + int i; + for (i = 0; i < (4 * ICH9_SPI_FLASH_REGIONS); i += 4) + RCBA32(ICH9_SPI_FPR0 + i) = + RCBA32(ICH9_SPI_FREG0 + i) | (1 << 31); + + RCBA16(ICH9_SPI_HSFS) |= ICH9_SPI_HSFS_FLOCKDN; +} + int intel_lockdown_flash(void) { const u32 reg32 = pci_read_config32(PCI_DEV(0,0x1f, 0), 0); @@ -106,8 +167,46 @@ int intel_lockdown_flash(void) of setting up any write protection. */ lockdown_flash_ich9_empty_ops(); break; + + /* Cougar Point */ + case 0x1c448086: + case 0x1c468086: + case 0x1c478086: + case 0x1c498086: + case 0x1c4a8086: + case 0x1c4b8086: + case 0x1c4c8086: + case 0x1c4d8086: + case 0x1c4e8086: + case 0x1c4f8086: + case 0x1c508086: + case 0x1c528086: + case 0x1c548086: + case 0x1c568086: + case 0x1c5c8086: + /* Panther Point */ + case 0x1e448086: + case 0x1e468086: + case 0x1e478086: + case 0x1e488086: + case 0x1e498086: + case 0x1e4a8086: + case 0x1e538086: + case 0x1e558086: + case 0x1e568086: + case 0x1e578086: + case 0x1e588086: + case 0x1e598086: + case 0x1e5d8086: + case 0x1e5e8086: + case 0x1e5f8086: + lockdown_flash_ich7(); + /* Since Cougar Point, coreboot uses flash regions, + lock them and set up static SPI opcodes. */ + lockdown_flash_ich9_lock_regions(); + break; default: - debug("Not an ICH7 or ICH9 southbridge\n"); + debug("Not a supported ICH or PCH southbridge\n"); return -1; }

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coreboot-gerrit July 2013