coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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1030 discussions

Patch set updated for coreboot: fe62690 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`
by Nico Huber 02 Jul '13

02 Jul '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3220 -gerrit commit fe62690f03e50c809b06d2a0e67f39757531da64 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed May 8 17:08:55 2013 +0200 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c` Use the same indentation, comment placement and spelling of words. Run `indent -linux …`. Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/gm45/delay.c | 5 ++--- src/northbridge/intel/i945/udelay.c | 5 ++--- src/northbridge/intel/sandybridge/udelay.c | 4 ++-- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index a861e25..0b5ecd9 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -24,7 +24,7 @@ #include "delay.h" /** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */ static void _udelay(const u32 us, const u32 numerator, const int total) { @@ -62,8 +62,7 @@ static void _udelay(const u32 us, const u32 numerator, const int total) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f; - /* CPU clock is always a quarter. */ - d = ((fsb * divisor) / numerator) / 4; + d = ((fsb * divisor) / numerator) / 4; /* CPU clock is always a quarter. */ multiply_to_tsc(&tscd, us, d); diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 3d5d6c6..60ca9fb 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -24,7 +24,7 @@ #include <cpu/intel/speedstep.h> /** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */ void udelay(u32 us) @@ -63,7 +63,7 @@ void udelay(u32 us) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f; - d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ multiply_to_tsc(&tscd, us, d); @@ -79,5 +79,4 @@ void udelay(u32 us) tsc = rdtsc(); } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); - } diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 449b0b9..608726c 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -23,7 +23,7 @@ #include <cpu/x86/msr.h> /** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz + * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz */ void udelay(u32 us) @@ -37,7 +37,7 @@ void udelay(u32 us) msr = rdmsr(0xce); divisor = (msr.lo >> 8) & 0xff; - d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ multiply_to_tsc(&tscd, us, d); tsc1 = rdtsc();

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Patch set updated for coreboot: 887b699 ARM ARCH64: extend buildgcc and xcompile to set the tools up
by Ronald G. Minnich 02 Jul '13

02 Jul '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3591 -gerrit commit 887b69987d0a68652bd042003dedc96af21bb42f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jul 2 19:20:21 2013 +0200 ARM ARCH64: extend buildgcc and xcompile to set the tools up With this change, the recommended aarch64 toolchain is fetched, installed, and util/xcompile/xcompile will properly put the definitions in .xcompile For now, we need to get the pre-built compilers per a conversation we've had with a CPU company. The patch list is evidently huge and still in the process of being taken in. The current 'good' toolchain is the linaro one. They recommended in the strongest terms that just getting the binaries was the way to go for now. Obviously, at some point, this decision will be revisited. Change-Id: I904acd604ac0982178fa5c2f27f22fee7cf1cac0 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- util/crossgcc/buildgcc | 14 ++++++++++++++ util/xcompile/xcompile | 7 ++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 4458ea4..8efccd8 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -227,10 +227,24 @@ case "$TARGETARCH" in i386-mingw32) ;; i386*) TARGETARCH=i386-elf;; arm*) TARGETARCH=armv7a-eabi;; + aarch64) TARGETARCH=aarch64;; *) printf "Invalid architecture\n\n"; myhelp; exit 1;; esac echo "Target arch is now $TARGETARCH" + +# we're not building from source yet. +if [ $TARGETARCH = "aarch64" ]; then + mkdir -p xgcc/bin + cd xgcc/bin + wget -O - http://releases.linaro.org/12.10/components/toolchain/gcc-linaro/aarch64/rc… | tar xjf - + for i in gcc-linaro-aarch64-linux-gnu-4.7+bzr115029-20121015+bzr2506_linux/aarch64-linux-gnu/bin/*; do + file=`basename $i` + ln -s $i aarch64-elf-$file + done + exit +fi + GDB_PACKAGE="GDB" PYTHON_PACKAGE="PYTHON" EXPAT_PACKAGE="EXPAT" diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index ff12217..08058c6 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -135,7 +135,7 @@ touch "$TMPFILE" trap clean_up EXIT # Architecture definition -SUPPORTED_ARCHITECTURE="x86 armv7" +SUPPORTED_ARCHITECTURE="x86 armv7 aarch64" # ARM Architecture TARCH_armv7="armv7" @@ -143,6 +143,11 @@ TBFDARCH_armv7="littlearm" TCLIST_armv7="armv7a" TWIDTH_armv7="32" +TARCH_aarch64="aarch64" +TBFDARCH_aarch64="littleaarch64" +TCLIST_aarch64="aarch64" +TWIDTH_aarch64="64" + # X86 Architecture TARCH_x86="i386" TBFDARCH_x86="i386"

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Patch set updated for coreboot: 6aaf65b Makefile: fix config.h leaking to the next build when using CONFIG_UPDATE_IMAGE.
by Denis Carikli 02 Jul '13

02 Jul '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3585 -gerrit commit 6aaf65b28434bf40aaf5c1258bc16cbff6ab1c99 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Mon Jul 1 08:39:51 2013 +0200 Makefile: fix config.h leaking to the next build when using CONFIG_UPDATE_IMAGE. When we build a first image with the fallback/ prefix, with the CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT option, and without CONFIG_UPDATE_IMAGE, the image builds fine, and build/coreboot.rom is generated. Then if when we run "make menuconfig" and select CONFIG_UPDATE_IMAGE along with different options( here we will unselect the CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT ), we then have a build failure like that: build/generated/coreboot_ram.o: In function `gma_func0_init': [...]/src/northbridge/intel/i945/gma.c:62: undefined reference to `i915lightup' build/generated/coreboot_ram.o: In function `lb_framebuffer': [...]/src/lib/coreboot_table.c:176: undefined reference to `vbe_mode_info_valid' [...]/src/lib/coreboot_table.c:182: undefined reference to `fill_lb_framebuffer' collect2: error: ld returned 1 exit status despite of having #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT and #endif surrounding the usage of i915lightup in [...]/src/northbridge/intel/i945/gma.c It is due to the fact that build/config.h has #define CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT 1 in it, despite of having selected CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT only in the first build(the one with the /fallback prefix). Change-Id: I345c2359876918eba1019f25d86d1392f4ee85e1 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index dec32e5..fbe68fa 100644 --- a/Makefile +++ b/Makefile @@ -82,7 +82,10 @@ HOSTCXXFLAGS := -g DOXYGEN := doxygen DOXYGEN_OUTPUT_DIR := doxygen -all: real-all +all: clean-config real-all + +clean-config: + rm -f $(obj)/config.h # This include must come _before_ the pattern rules below! # Order _does_ matter for pattern rules.

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Patch set updated for coreboot: 5b51373 Add a new and safer bootblock implementation.
by Denis Carikli 02 Jul '13

02 Jul '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3549 -gerrit commit 5b51373d79139461b992f4ebcca9efcd381023b0 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 21 23:32:19 2013 +0200 Add a new and safer bootblock implementation. The drawback is that it requires cooperation from something that is run after coreboot (like the OS or the payload). To understand how to use it, refer to the Kconfig help of that option. Thanks a lot to kmalkki on #coreboot Freenode IRC channel for pointers on how to simplify the implementation. Change-Id: I1109c49c7c84461bb056b36ee5d07391c2392176 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 13 +++++++++++++ src/drivers/pc80/mc146818rtc_early.c | 37 ++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 69cdc8a..3bb6547 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -54,12 +54,25 @@ config X86_BOOTBLOCK_SIMPLE config X86_BOOTBLOCK_NORMAL bool "Switch to normal if CMOS says so" +config X86_BOOTBLOCK_FAILBOOT + bool "Switch to Fallback if it fails to boot" + help + Switch to Fallback after failing to boot. + Coreboot will reset boot_option to Fallback + as early as possible, If the user has + a Fallback and a Normal image in cbfs, + and wants to boot on the Normal image, + he must reset the boot_option to Normal + after successfully booting (like trough the OS + boot scripts that would run something like: + "nvramtool -w boot_option=Normal". endchoice config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if X86_BOOTBLOCK_SIMPLE default "bootblock_normal.c" if X86_BOOTBLOCK_NORMAL + default "bootblock_normal.c" if X86_BOOTBLOCK_FAILBOOT config UPDATE_IMAGE bool "Update existing coreboot.rom image" diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 0652f27..2b2fc77 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -42,13 +42,49 @@ static int cmos_chksum_valid(void) } +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline int last_boot_normal(void) +{ + unsigned char byte; + byte = cmos_read(RTC_BOOT_BYTE); + return (byte & (1 << 0)); +} +#else static inline int last_boot_normal(void) { unsigned char byte; byte = cmos_read(RTC_BOOT_BYTE); return (byte & (1 << 1)); } +#endif +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline int do_normal_boot(void) +{ + unsigned char old_byte, write_byte; + + if (cmos_error() || !cmos_chksum_valid()) { + /* There are no impossible values, no checksums so just + * trust whatever value we have in the the cmos, + * but clear the fallback bit. + */ + write_byte = cmos_read(RTC_BOOT_BYTE); + write_byte &= 0x0c; + cmos_write(write_byte, RTC_BOOT_BYTE); + } + + /* The RTC_BOOT_BYTE is now o.k. see where to go. */ + write_byte = old_byte = cmos_read(RTC_BOOT_BYTE); + + /* Reset boot_option to Fallback */ + write_byte &= ~(1<<0); + + /* Save the boot byte */ + cmos_write(write_byte, RTC_BOOT_BYTE); + + return (old_byte & (1<<0)); +} +#else static inline int do_normal_boot(void) { unsigned char byte; @@ -91,6 +127,7 @@ static inline int do_normal_boot(void) return (byte & (1<<1)); } +#endif unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) {

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New patch to review for coreboot: cfa24d9 ARM ARCH64: try to get xcompile built
by Ronald G. Minnich 02 Jul '13

02 Jul '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3591 -gerrit commit cfa24d9b7f5e52ef0dbb8d12e225a264268b3393 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jul 2 19:20:21 2013 +0200 ARM ARCH64: try to get xcompile built DRAFT: does not work. The toolchain gets installed, but I can't figure out how to get xcompile to include the binaries. Maybe some smart guy out there will tell me what I'm missing. For now, we need to get with the pre-built compilers per a conversation we've had with a CPU company. Change-Id: I904acd604ac0982178fa5c2f27f22fee7cf1cac0 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- util/crossgcc/buildgcc | 14 ++++++++++++++ util/xcompile/xcompile | 7 ++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 4458ea4..548366a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -227,10 +227,24 @@ case "$TARGETARCH" in i386-mingw32) ;; i386*) TARGETARCH=i386-elf;; arm*) TARGETARCH=armv7a-eabi;; + aarch64) TARGETARCH=aarch64;; *) printf "Invalid architecture\n\n"; myhelp; exit 1;; esac echo "Target arch is now $TARGETARCH" + +# we're not building from source yet. +if [ $TARGETARCH = "aarch64" ]; then + mkdir -p xgcc/bin + cd xgcc/bin + wget -O - http://releases.linaro.org/12.10/components/toolchain/gcc-linaro/aarch64/rc… | tar xjf - + for i in gcc-linaro-aarch64-linux-gnu-4.7+bzr115029-20121015+bzr2506_linux/aarch64-linux-gnu/bin/*; do + file=`basename $i` + ln -s $i aarch64-elf-$file + done + exit +fi + GDB_PACKAGE="GDB" PYTHON_PACKAGE="PYTHON" EXPAT_PACKAGE="EXPAT" diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index ff12217..308bd02 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -135,7 +135,7 @@ touch "$TMPFILE" trap clean_up EXIT # Architecture definition -SUPPORTED_ARCHITECTURE="x86 armv7" +SUPPORTED_ARCHITECTURE="x86 armv7 aarch64" # ARM Architecture TARCH_armv7="armv7" @@ -143,6 +143,11 @@ TBFDARCH_armv7="littlearm" TCLIST_armv7="armv7a" TWIDTH_armv7="32" +TARCH_aarch64="aarch64" +TBFDARCH_aarch64="aarch64" +TCLIST_aarch64="aarch64" +TWIDTH_aarch64="64" + # X86 Architecture TARCH_x86="i386" TBFDARCH_x86="i386"

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New patch to review for coreboot: 42747cf winbond/w83627dhg: Fix logical device power down in ACPI
by Nico Huber 02 Jul '13

02 Jul '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3590 -gerrit commit 42747cff716b336afc431029e21e1ee366418568 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Jul 1 16:29:16 2013 +0200 winbond/w83627dhg: Fix logical device power down in ACPI The W83627DHG has some power managements bits to power down individual logical devices. These are called `* Power Down`. Counterintuitively and in contrast to `Immediate Power Down` (bit to power down the whole chip), these bits are set when the respective logical device is powered. Unfortunately, our ACPI code set them wrong which led to disabled devices after a S3 suspend/resume. Adding an option how to set the PM bits and setting them to zero for the W83627DHG, corrects it. Tested with kontron/ktqm77. Change-Id: I8a472d480d4277721bd17c9f7c2ce44fa84e8ae2 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/superio/acpi/pnp.asl | 12 ++++++------ src/superio/acpi/pnp_generic.asl | 8 +++++--- src/superio/acpi/pnp_uart.asl | 10 ++++++---- src/superio/winbond/w83627dhg/acpi/superio.asl | 6 ++++++ 4 files changed, 23 insertions(+), 13 deletions(-) diff --git a/src/superio/acpi/pnp.asl b/src/superio/acpi/pnp.asl index ba3882a..0637c04 100644 --- a/src/superio/acpi/pnp.asl +++ b/src/superio/acpi/pnp.asl @@ -90,25 +90,25 @@ * PM_LDN The logical device number to access the PM_REG * bit */ -#define PNP_GENERIC_PSC(PM_REG, PM_LDN) \ +#define PNP_GENERIC_PSC(PM_REG, PM_VAL, PM_LDN) \ Store(^^_PSC (), Local0)\ If (Local0) { Return (Local0) }\ ENTER_CONFIG_MODE (PM_LDN)\ Store (PM_REG, Local0)\ EXIT_CONFIG_MODE ()\ - If (Local0) { Return (1) }\ + If (LEqual(Local0, PM_VAL)) { Return (1) }\ Else { Return (0) }\ /* Disable power saving mode */ -#define PNP_GENERIC_PS0(PM_REG, PM_LDN) \ +#define PNP_GENERIC_PS0(PM_REG, PM_VAL, PM_LDN) \ ENTER_CONFIG_MODE (PM_LDN)\ - Store (Zero, PM_REG)\ + Store (Not(PM_VAL), PM_REG)\ EXIT_CONFIG_MODE () /* Enable power saving mode */ -#define PNP_GENERIC_PS1(PM_REG, PM_LDN) \ +#define PNP_GENERIC_PS1(PM_REG, PM_VAL, PM_LDN) \ ENTER_CONFIG_MODE (PM_LDN)\ - Store (One, PM_REG)\ + Store (PM_VAL, PM_REG)\ EXIT_CONFIG_MODE () diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index f7a9b13..74fd028 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -31,6 +31,8 @@ * name (DDN) of this device (e.g. "COM1", optional) * SUPERIO_PNP_PM_REG Identifier of a 1-bit register to power down * the logical device (optional) + * SUPERIO_PNP_PM_VAL The value for SUPERIO_PNP_PM_REG to power the logical + * device down (required if SUPERIO_PNP_PM_REG is defined) * SUPERIO_PNP_PM_LDN The logical device number to access the PM_REG * bit (required if SUPERIO_PNP_PM_REG is defined) * SUPERIO_PNP_IO0 The alignment and length of the first PnP i/o @@ -73,15 +75,15 @@ Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) { #ifdef SUPERIO_PNP_PM_REG Method (_PSC) { - PNP_GENERIC_PSC(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_LDN) + PNP_GENERIC_PSC(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN) } Method (_PS0) { - PNP_GENERIC_PS0(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_LDN) + PNP_GENERIC_PS0(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN) } Method (_PS1) { - PNP_GENERIC_PS1(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_LDN) + PNP_GENERIC_PS1(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN) } #else Method (_PSC) { diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl index c826106..8ddecbf 100644 --- a/src/superio/acpi/pnp_uart.asl +++ b/src/superio/acpi/pnp_uart.asl @@ -32,7 +32,9 @@ * name (DDN) of this uart (e.g. "COM1", optional) * SUPERIO_UART_PM_REG Identifier of a 1-bit register to power down * the UART (optional) - * SUPERIO_UART_PM_LDN The logical device number to access the PM_REG + * SUPERIO_UART_PM_VAL The value for SUPERIO_UART_PM_REG to power the logical + * device down (required if SUPERIO_UART_PM_REG is defined) + * SUPERIO_UART_PM_LDN The logical device number to access the PM_REG * bit (required if SUPERIO_UART_PM_REG is defined) */ @@ -65,15 +67,15 @@ Device (SUPERIO_ID(SER, SUPERIO_UART_LDN)) { #ifdef SUPERIO_UART_PM_REG Method (_PSC) { - PNP_GENERIC_PSC(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_LDN) + PNP_GENERIC_PSC(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_VAL, SUPERIO_UART_PM_LDN) } Method (_PS0) { - PNP_GENERIC_PS0(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_LDN) + PNP_GENERIC_PS0(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_VAL, SUPERIO_UART_PM_LDN) } Method (_PS1) { - PNP_GENERIC_PS1(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_LDN) + PNP_GENERIC_PS1(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_VAL, SUPERIO_UART_PM_LDN) } #else Method (_PSC) { diff --git a/src/superio/winbond/w83627dhg/acpi/superio.asl b/src/superio/winbond/w83627dhg/acpi/superio.asl index 417d6fe..7616363 100644 --- a/src/superio/winbond/w83627dhg/acpi/superio.asl +++ b/src/superio/winbond/w83627dhg/acpi/superio.asl @@ -147,9 +147,11 @@ Device(SUPERIO_DEV) { #undef SUPERIO_UART_LDN #undef SUPERIO_UART_DDN #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL #undef SUPERIO_UART_PM_LDN #define SUPERIO_UART_LDN 2 #define SUPERIO_UART_PM_REG UAPW + #define SUPERIO_UART_PM_VAL 0 #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE #include <superio/acpi/pnp_uart.asl> #endif @@ -158,9 +160,11 @@ Device(SUPERIO_DEV) { #undef SUPERIO_UART_LDN #undef SUPERIO_UART_DDN #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL #undef SUPERIO_UART_PM_LDN #define SUPERIO_UART_LDN 3 #define SUPERIO_UART_PM_REG UBPW + #define SUPERIO_UART_PM_VAL 0 #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE #include <superio/acpi/pnp_uart.asl> #endif @@ -180,6 +184,7 @@ Device(SUPERIO_DEV) { #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN #undef SUPERIO_PNP_IO0 #undef SUPERIO_PNP_IO1 @@ -188,6 +193,7 @@ Device(SUPERIO_DEV) { #undef SUPERIO_PNP_DMA #define SUPERIO_PNP_LDN 11 #define SUPERIO_PNP_PM_REG HWPW + #define SUPERIO_PNP_PM_VAL 0 #define SUPERIO_PNP_PM_LDN PNP_NO_LDN_CHANGE #define SUPERIO_PNP_IO0 0x08, 0x08 #define SUPERIO_PNP_IRQ0 1

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Patch merged into coreboot/master: 59158b2 Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900
by gerrit＠coreboot.org 02 Jul '13

02 Jul '13

the following patch was just integrated into master: commit 59158b2fb0eda826feaa7ae99d5fe2a284c569d3 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon Jul 1 14:19:48 2013 -0600 Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900 The MAX_PIRQ_LINKS is defined in src/Kconfig with a default value of 4. The src/northbridge/via/vx900/Kconfig also defines MAX_PIRQ_LINKS with a default of 8 and it ends up giving us a value of 8 for non-VIA platforms. Change-Id: Iee1938d38a93ab7c35c8cb6fe9656a92cf3fa21e Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3586 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3586 for details. -gerrit

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Patch set updated for coreboot: c06a0cd Move select MMCONF_SUPPORT under northbridge
by Kyösti Mälkki 02 Jul '13

02 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3589 -gerrit commit c06a0cd59db5380b30097ca8b35118cf5e226a88 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 2 11:37:35 2013 +0300 Move select MMCONF_SUPPORT under northbridge Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as that feature originates from northbridge and cannot be disabled for a single mainboard. Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/asus/dsbf/Kconfig | 1 - src/mainboard/google/snow/Kconfig | 1 - src/mainboard/intel/baskingridge/Kconfig | 1 - src/mainboard/intel/eagleheights/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/mainboard/iwave/iWRainbowG6/Kconfig | 1 - src/mainboard/supermicro/x7db8/Kconfig | 1 - src/mainboard/via/vt8454c/Kconfig | 1 - src/northbridge/intel/haswell/Kconfig | 1 + src/northbridge/intel/i3100/Kconfig | 1 + src/northbridge/intel/i5000/Kconfig | 1 + src/northbridge/intel/sch/Kconfig | 1 + 12 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig index 3927853..5d67014 100644 --- a/src/mainboard/asus/dsbf/Kconfig +++ b/src/mainboard/asus/dsbf/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I3100 select NORTHBRIDGE_INTEL_I5000 select SUPERIO_WINBOND_W83627HF - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_512 select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index aa4c3c4..4072b0f 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES -# select MMCONF_SUPPORT select EXYNOS_DISPLAYPORT select CHROMEOS select DRIVER_TI_TPS65090 diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 9608ea2..163ccc9 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select CHROMEOS select EXTERNAL_MRC_BLOB diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index 0b765f9..e74705b 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select MMCONF_SUPPORT select UDELAY_TSC select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 4065110..3e41b2c 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select CHROMEOS select EXTERNAL_MRC_BLOB diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index e908fcf..75d4bb9 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_SCH select HAVE_PIRQ_TABLE # select HAVE_MP_TABLE - select MMCONF_SUPPORT select USE_PRINTK_IN_CAR select UDELAY_LAPIC select HAVE_ACPI_TABLES diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig index 47fb4b9..03f8ceb 100644 --- a/src/mainboard/supermicro/x7db8/Kconfig +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I3100 select NORTHBRIDGE_INTEL_I5000 select SUPERIO_WINBOND_W83627HF - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_512 select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig index 1f5e95a..14eebe6 100644 --- a/src/mainboard/via/vt8454c/Kconfig +++ b/src/mainboard/via/vt8454c/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE -# select MMCONF_SUPPORT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index f689780..72ea080 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_MRC_BIN select CPU_INTEL_HASWELL select REQUIRES_BLOB + select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 079004b..2bb1a25 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I3100 bool + select MMCONF_SUPPORT if NORTHBRIDGE_INTEL_I3100 config DIMM_MAP_LOGICAL diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig index a5ca7f0..b9c3547 100644 --- a/src/northbridge/intel/i5000/Kconfig +++ b/src/northbridge/intel/i5000/Kconfig @@ -19,6 +19,7 @@ config NORTHBRIDGE_INTEL_I5000 bool + select MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP config NORTHBRIDGE_INTEL_I5000_RAM_CHECK diff --git a/src/northbridge/intel/sch/Kconfig b/src/northbridge/intel/sch/Kconfig index cc96cba..f87afdf 100644 --- a/src/northbridge/intel/sch/Kconfig +++ b/src/northbridge/intel/sch/Kconfig @@ -19,6 +19,7 @@ config NORTHBRIDGE_INTEL_SCH bool + select MMCONF_SUPPORT if NORTHBRIDGE_INTEL_SCH

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New patch to review for coreboot: 6bcf095 Move select MMCONF_SUPPORT under northbridge
by Kyösti Mälkki 02 Jul '13

02 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3589 -gerrit commit 6bcf09515521171c51d0ce1e7d5fe34898dc52bc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 2 11:37:35 2013 +0300 Move select MMCONF_SUPPORT under northbridge Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as that feature originates from northbridge and cannot be disabled for a single mainboard. Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/asus/dsbf/Kconfig | 1 - src/mainboard/google/snow/Kconfig | 1 - src/mainboard/intel/baskingridge/Kconfig | 1 - src/mainboard/intel/eagleheights/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/mainboard/iwave/iWRainbowG6/Kconfig | 1 - src/mainboard/supermicro/x7db8/Kconfig | 1 - src/mainboard/via/vt8454c/Kconfig | 1 - src/northbridge/intel/haswell/Kconfig | 1 + src/northbridge/intel/i3100/Kconfig | 1 + src/northbridge/intel/sch/Kconfig | 1 + 11 files changed, 3 insertions(+), 8 deletions(-) diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig index 3927853..5d67014 100644 --- a/src/mainboard/asus/dsbf/Kconfig +++ b/src/mainboard/asus/dsbf/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I3100 select NORTHBRIDGE_INTEL_I5000 select SUPERIO_WINBOND_W83627HF - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_512 select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index aa4c3c4..4072b0f 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES -# select MMCONF_SUPPORT select EXYNOS_DISPLAYPORT select CHROMEOS select DRIVER_TI_TPS65090 diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 9608ea2..163ccc9 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select CHROMEOS select EXTERNAL_MRC_BLOB diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index 0b765f9..e74705b 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select MMCONF_SUPPORT select UDELAY_TSC select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 4065110..3e41b2c 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select CHROMEOS select EXTERNAL_MRC_BLOB diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index e908fcf..75d4bb9 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_SCH select HAVE_PIRQ_TABLE # select HAVE_MP_TABLE - select MMCONF_SUPPORT select USE_PRINTK_IN_CAR select UDELAY_LAPIC select HAVE_ACPI_TABLES diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig index 47fb4b9..03f8ceb 100644 --- a/src/mainboard/supermicro/x7db8/Kconfig +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I3100 select NORTHBRIDGE_INTEL_I5000 select SUPERIO_WINBOND_W83627HF - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_512 select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig index 1f5e95a..14eebe6 100644 --- a/src/mainboard/via/vt8454c/Kconfig +++ b/src/mainboard/via/vt8454c/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE -# select MMCONF_SUPPORT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index f689780..72ea080 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_MRC_BIN select CPU_INTEL_HASWELL select REQUIRES_BLOB + select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 079004b..2bb1a25 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I3100 bool + select MMCONF_SUPPORT if NORTHBRIDGE_INTEL_I3100 config DIMM_MAP_LOGICAL diff --git a/src/northbridge/intel/sch/Kconfig b/src/northbridge/intel/sch/Kconfig index cc96cba..f87afdf 100644 --- a/src/northbridge/intel/sch/Kconfig +++ b/src/northbridge/intel/sch/Kconfig @@ -19,6 +19,7 @@ config NORTHBRIDGE_INTEL_SCH bool + select MMCONF_SUPPORT if NORTHBRIDGE_INTEL_SCH

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New patch to review for coreboot: e337722 Lenovo ThinkPad T60: Clean up `romstage.c`
by Paul Menzel 02 Jul '13

02 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3588 -gerrit commit e3377225a8737cc011ec68a4d26f0e8d55e756a9 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Apr 29 23:16:27 2013 +0200 Lenovo ThinkPad T60: Clean up `romstage.c` 1. Correctly spell the word »set up«. 2. Start output with capital letter and add full stop at the end. 3. Indent the code automatically using GNU indent [1] with the `-sc` switch adding stars in front of comment blocks as the good indent manual documents. $ indent -linux -sc src/mainboard/lenovo/t60/romstage.c Leave the numbers left aligned as it is more beneficial to be able to run indent without adapting the result afterward. See the equivalent commit c2f17773 for the Lenovo ThinkPad X60 [1]. Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Apr 29 23:05:44 2013 +0200 Lenovo ThinkPad X60: Clean up `romstage.c` [1] http://review.coreboot.org/3185 Change-Id: I507dc8c824860e4606b90e8ab11fa1bb85d8c001 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/t60/romstage.c | 58 ++++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 5bb7ac1..0ef8d09 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -44,22 +44,22 @@ void setup_ich7_gpios(void) printk(BIOS_DEBUG, " GPIOS..."); /* T60 GPIO: - 6: LEGACYIO# - 7: BDC_PRESENCE# - 8: H8_WAKE# - 10: MDI_DETECT - 12: H8SCI# - 14: CPUSB# - 15: CPPE# - 25: MDC_KILL# - 27: EXC_PWR_CTRL - 28: EXC_AUX_CTRL - 35: CLKREQ_SATA# - 36: PLANARID0 - 37: PLANARID1 - 38: PLANARID2 - 39: PLANARID3 - */ + * 6: LEGACYIO# + * 7: BDC_PRESENCE# + * 8: H8_WAKE# + * 10: MDI_DETECT + * 12: H8SCI# + * 14: CPUSB# + * 15: CPPE# + * 25: MDC_KILL# + * 27: EXC_PWR_CTRL + * 28: EXC_AUX_CTRL + * 35: CLKREQ_SATA# + * 36: PLANARID0 + * 37: PLANARID1 + * 38: PLANARID2 + * 39: PLANARID3 + */ outl(0x1f48f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0xe0e0ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ outl(0xfbfefb7d, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ @@ -101,7 +101,7 @@ static void early_superio_config(void) pnp_write_config(dev, 0x29, 0xa0); - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + while (!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) udelay(1000); /* Enable COM1 */ @@ -140,7 +140,7 @@ static void rcba_config(void) /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD; - RCBA32(0x3418) |= (1 << 0); // Required. + RCBA32(0x3418) |= (1 << 0); // Required. /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ RCBA32(0x1e84) = 0x00020001; @@ -253,16 +253,18 @@ void main(unsigned long bist) early_superio_config(); } - /* Setup the console */ + /* Set up the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + printk(BIOS_DEBUG, + "Soft reset detected, rebooting properly.\n"); outb(0x6, 0xcf9); - while (1) asm("hlt"); + while (1) + asm("hlt"); } /* Perform some early chipset initialization required @@ -323,7 +325,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); @@ -350,18 +352,20 @@ void main(unsigned long bist) * day. */ if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, + HIGH_MEMORY_SAVE); /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, + SKPAD_ACPI_S3_MAGIC); } #endif #if CONFIG_COLLECT_TIMESTAMPS timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); - timestamp_add(TS_AFTER_INITRAM, after_dram_time ); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif

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coreboot-gerrit July 2013