coreboot-gerrit July 2013

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New patch to review for coreboot: 7d39656 lenovo/x60/romstage.c: Collect timestamps in romstage
by Paul Menzel 02 Jul '13

02 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3587 -gerrit commit 7d396566be210dfd5f86c8d9038ae0fdacefa02f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jul 2 09:54:17 2013 +0200 lenovo/x60/romstage.c: Collect timestamps in romstage Collect early timestamps in Lenovo X60’s romstage like the Lenovo T60 does. Selecting the option `COLLECT_TIMESTAMPS` in Kconfig and then doing `cbmem --timestamps` should output the timestamps. Thanks to Nico Huber’s work setting this up for the ICH7 and implementing it for the T60, all what was needed to do, was to do the equivalent changes for the X60 as for the T60 in commit 44c392f8 [1]. lenovo/t60: Collect timestamps in romstage [1] http://review.coreboot.org/3499 Change-Id: I7bd30f03a1b85c38e89c19cdf88b2d20b24abed8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/romstage.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 222b999..4d0eac7 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -30,6 +30,7 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <cbmem.h> +#include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -218,6 +219,20 @@ void main(unsigned long bist) int cbmem_was_initted; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; +#if CONFIG_COLLECT_TIMESTAMPS + tsc_t start_romstage_time; + tsc_t before_dram_time; + tsc_t after_dram_time; + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; +#endif + +#if CONFIG_COLLECT_TIMESTAMPS + start_romstage_time = rdtsc(); +#endif + if (bist == 0) enable_lapic(); @@ -281,7 +296,13 @@ void main(unsigned long bist) dump_spd_registers(); #endif +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = rdtsc(); +#endif sdram_initialize(boot_mode, spd_addrmap); +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = rdtsc(); +#endif /* Perform some initialization that must run before stage2 */ early_ich7_init(); @@ -340,6 +361,14 @@ void main(unsigned long bist) } #endif +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit();

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Patch set updated for coreboot: a26548d Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900
by Dave Frodin 01 Jul '13

01 Jul '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3586 -gerrit commit a26548d3e2e6fc83309da8421c2a5b0397529071 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon Jul 1 14:19:48 2013 -0600 Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900 The MAX_PIRQ_LINKS is defined in src/Kconfig with a default value of 4. The src/northbridge/via/vx900/Kconfig also defines MAX_PIRQ_LINKS with a default of 8 and it ends up giving us a value of 8 for non-VIA platforms. Change-Id: Iee1938d38a93ab7c35c8cb6fe9656a92cf3fa21e Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/northbridge/via/vx900/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index a76b59b..910523f 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -28,6 +28,8 @@ config NORTHBRIDGE_VIA_VX900 select MMCONF_SUPPORT_DEFAULT select GFXUMA +if NORTHBRIDGE_VIA_VX900 + config MAX_PIRQ_LINKS int default 8 @@ -39,3 +41,5 @@ config MMCONF_BASE_ADDRESS config VGA_BIOS_ID string default "1106,7122" + +endif

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Patch merged into coreboot/master: dda4095 w83627hf: Add comments about parallel port modes in superio.asl
by gerrit＠coreboot.org 01 Jul '13

01 Jul '13

the following patch was just integrated into master: commit dda4095101f8e04924d32dbabfd038b32a93961c Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Tue Jun 18 01:26:50 2013 +0200 w83627hf: Add comments about parallel port modes in superio.asl Add comments in PAR0._PRS explaining which dependent resource descriptor puts the parallel port into EPP or SPP mode. Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3495 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber(a)secunet.com> See http://review.coreboot.org/3495 for details. -gerrit

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Patch merged into coreboot/master: e978fc2 cbmem: Fix makefile
by gerrit＠coreboot.org 01 Jul '13

01 Jul '13

the following patch was just integrated into master: commit e978fc265d22d54146ba167b63ed0e3a6d4875a5 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sun Jun 30 01:05:30 2013 +0200 cbmem: Fix makefile The .dependencies rule did not use the CPPFLAGS variable which led to funny behavior: a spurious termination message the first time (after checkout/make distclean) one executes make. Afterwards the (wrongly) empty .dependencies file hides the problem and the binary is created anyway. $ make cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory compilation terminated. cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem $ make make: Nothing to be done for `all'. $ make clean rm -f cbmem *.o *~ $ make cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem $ make distclean rm -f cbmem *.o *~ rm -f .dependencies $ make cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory compilation terminated. cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem I fixed that by adding the CPPFLAGS variable to the .dependencies recipe, just like Stefan Reinauer did in Chromium (Ia9d2e10a3ef122f30d681d16c2291eb108ead835), hence the split sign-off for this tiny change. :) Change-Id: Icd11b146ad762cbdf9774630b950f70e1253a072 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: http://review.coreboot.org/3548 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber(a)secunet.com> See http://review.coreboot.org/3548 for details. -gerrit

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Patch set updated for coreboot: 9b99c91 w83627hf: Add comments about parallel port modes in superio.asl
by Nico Huber 01 Jul '13

01 Jul '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3495 -gerrit commit 9b99c91f165e08b9411a8b6fa665a815171bf4b8 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Tue Jun 18 01:26:50 2013 +0200 w83627hf: Add comments about parallel port modes in superio.asl Add comments in PAR0._PRS explaining which dependent resource descriptor puts the parallel port into EPP or SPP mode. Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/superio/winbond/w83627hf/acpi/superio.asl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 69017fe..ff95dfc 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -529,6 +529,7 @@ Device(SIO) { Name (_PRS, ResourceTemplate () { + /* Traditional configurations (SPP mode) */ StartDependentFn (0,1) { IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) @@ -544,6 +545,7 @@ Device(SIO) { IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Traditional configurations (EPP mode) */ StartDependentFn (0,0) { IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) @@ -554,11 +556,13 @@ Device(SIO) { IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Any configurable address (EPP mode) */ StartDependentFn (2,0) { IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Any configurable address (No EPP mode) */ StartDependentFn (2,1) { IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08)

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New patch to review for coreboot: 48cd4ee Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900
by Dave Frodin 01 Jul '13

01 Jul '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3586 -gerrit commit 48cd4eea777fd93c694974c1665a02e34b345a0c Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon Jul 1 14:19:48 2013 -0600 Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900 The MAX_PIRQ_LINKS is defined in src/Kconfig with a default value of 4. The src/northbridge/via/vx900/Kconfig also defines MAX_PIRQ_LINKS with a default of 8 and it ends up giving us a value of 8 for non-VIA platforms. Change-Id: Iee1938d38a93ab7c35c8cb6fe9656a92cf3fa21e Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/northbridge/via/vx900/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index a76b59b..b623a3f 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -30,6 +30,7 @@ config NORTHBRIDGE_VIA_VX900 config MAX_PIRQ_LINKS int + depends on NORTHBRIDGE_VIA_VX900 default 8 config MMCONF_BASE_ADDRESS

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Patch set updated for coreboot: b28eb30 CBFS: Use memmove instead of memcpy when loading a file from CBFS.
by Ronald G. Minnich 01 Jul '13

01 Jul '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3577 -gerrit commit b28eb30bb29fd7ddfaf5709bd84008fa5c24b170 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 04:28:23 2013 -0700 CBFS: Use memmove instead of memcpy when loading a file from CBFS. It might be the case that a file is being loaded from a portion of CBFS which has already been loaded into a limitted bit of memory somewhere, and we want to load that file in place, effectively, so that it's original location in CBFS overlaps with its new location. That's only guaranteed to work if you use memmove instead of memcpy. One significant downside of this change is that there aren't yet architecture optimized (aka not horribly performing) implementations of memmove available for either x86 or ARM. It's not clear whether the performance difference would be significant enough to notice in practice since the things in CBFS are probably not that big. It might still be a good idea to hold off on this change until optimized versions are available to avoid any potential performance hit. This also means that memmove needs to be built into the bootblock. Change-Id: Id550138c875907749fff05f330fcd2fb5f9ed924 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/lib/Makefile.inc | 1 + src/lib/cbfs_core.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d44f4a7..50092b6 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -26,6 +26,7 @@ ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) bootblock-y += memcpy.c endif bootblock-y += memcmp.c +bootblock-y += memmove.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) romstage-y += memset.c diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 852b37f..39c1ff6 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -195,7 +195,7 @@ int cbfs_decompress(int algo, void *src, void *dst, int len) { switch (algo) { case CBFS_COMPRESS_NONE: - memcpy(dst, src, len); + memmove(dst, src, len); return 0; #ifdef CBFS_CORE_WITH_LZMA case CBFS_COMPRESS_LZMA:

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Patch merged into coreboot/master: 595ab4f beaglebone: Enable the clocks and pins for the configured UART.
by gerrit＠coreboot.org 01 Jul '13

01 Jul '13

the following patch was just integrated into master: commit 595ab4f955c98ee486cde7adc1af4eb56cebe569 Author: Gabe Black <gabeblack(a)chromium.org> Date: Sat Jun 29 23:20:14 2013 -0700 beaglebone: Enable the clocks and pins for the configured UART. Set up the pinmux to enable the pins and the clocks for whichever UART is currently configured. Change-Id: Iac13f16d9d84320555b99734ea83eafd0a2803fe Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3573 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3573 for details. -gerrit

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New patch to review for coreboot: c887f03 Makefile: fix config.h leaking to the next build when using CONFIG_UPDATE_IMAGE.
by Denis Carikli 01 Jul '13

01 Jul '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3585 -gerrit commit c887f033a5f3b2f7f3fc0a1cab212487651a2791 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Mon Jul 1 08:39:51 2013 +0200 Makefile: fix config.h leaking to the next build when using CONFIG_UPDATE_IMAGE. When we build a first image with the fallback/ prefix, with the CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT option, and without CONFIG_UPDATE_IMAGE, the image builds fine, and build/coreboot.rom is generated. Then if when we run "make menuconfig" and select CONFIG_UPDATE_IMAGE along with different options( here we will unselect the CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT ), we then have a build failure like that: build/generated/coreboot_ram.o: In function `gma_func0_init': [...]/src/northbridge/intel/i945/gma.c:62: undefined reference to `i915lightup' build/generated/coreboot_ram.o: In function `lb_framebuffer': [...]/src/lib/coreboot_table.c:176: undefined reference to `vbe_mode_info_valid' [...]/src/lib/coreboot_table.c:182: undefined reference to `fill_lb_framebuffer' collect2: error: ld returned 1 exit status despite of having #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT and #endif surrounding the usage of i915lightup in [...]/src/northbridge/intel/i945/gma.c It is due to the fact that build/config.h has #define CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT 0 in it, despite of having selected CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT only in the first build(the one with the /fallback prefix). Change-Id: I345c2359876918eba1019f25d86d1392f4ee85e1 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index dec32e5..fbe68fa 100644 --- a/Makefile +++ b/Makefile @@ -82,7 +82,10 @@ HOSTCXXFLAGS := -g DOXYGEN := doxygen DOXYGEN_OUTPUT_DIR := doxygen -all: real-all +all: clean-config real-all + +clean-config: + rm -f $(obj)/config.h # This include must come _before_ the pattern rules below! # Order _does_ matter for pattern rules.

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Patch merged into coreboot/master: 94f631c am335x: Fix the address of the pinmux registers.
by gerrit＠coreboot.org 01 Jul '13

01 Jul '13

the following patch was just integrated into master: commit 94f631cdc9805d61071c29d25a0af9ddea174c22 Author: Gabe Black <gabeblack(a)chromium.org> Date: Sat Jun 29 22:55:15 2013 -0700 am335x: Fix the address of the pinmux registers. The pinmux register data structure describes a subset of the control module registers, but the address which pointed to the base of the pinmux registers was actually being set to the beginning of all the control module registers, not just those having to do with the pinmux. With this address fixed, the UART now works on the beaglebone black. Change-Id: I7c99b6f37d7da359af074127cd0c1a86fda2d9a0 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3574 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3574 for details. -gerrit

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coreboot-gerrit July 2013