coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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New patch to review for filo: c02744c Update help text for flash lock
by Nico Huber 03 Jul '13

03 Jul '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3596 -gerrit commit c02744c1810713747bed3665f83341d289b50645 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Jul 3 15:39:47 2013 +0200 Update help text for flash lock Update the help text for the FLASHROM_LOCKDOWN option to reflect the current state of supported platforms. Change-Id: I9f8b13887b188d973a07b46b9948de5f5ad4435e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- Config.in | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Config.in b/Config.in index cd9fdda..08ac0ec 100644 --- a/Config.in +++ b/Config.in @@ -191,7 +191,12 @@ config FLASHROM_LOCKDOWN Enable system flash memory write protections and lock them down prior starting the kernel. Flash memory lockdown can be disabled per boot entry with the new command 'flashrom_unlock'. - NOTE: Only supported on selected Intel hardware, ICH7 so far. + + NOTE: Only supported on selected hardware: + + o Intel ICH7 (FWH) + o Intel ICH9 (FWH + SPI) + o AMD SB600 (SPI by locking the flash chip itself) endmenu

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New patch to review for filo: 747369c Refactor flash locking for supported Intel chipsets
by Nico Huber 03 Jul '13

03 Jul '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3595 -gerrit commit 747369c2646d851e83220e22f64dda37b4f695d4 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Jul 3 15:10:58 2013 +0200 Refactor flash locking for supported Intel chipsets This should make things more readable when support for more chipsets comes. Change-Id: I6df6673fa1961ab20796210577950e7be6c12316 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- drivers/intel.c | 72 ++++++++++++++++++++++++++++++--------------------------- 1 file changed, 38 insertions(+), 34 deletions(-) diff --git a/drivers/intel.c b/drivers/intel.c index 62d23b5..d2153b7 100644 --- a/drivers/intel.c +++ b/drivers/intel.c @@ -49,25 +49,50 @@ #define ICH9_SPI_OPTYPE 0x3896 #define ICH9_SPI_OPMENU 0x3898 -typedef enum { - ICH7, ICH9, -} ich_t; - -int intel_lockdown_flash(void) +static void lockdown_flash_ich7(void) { u8 reg8; u32 reg32; - ich_t ich; - reg32 = pci_read_config32(PCI_DEV(0,0x1f, 0), 0); + debug("Locking BIOS to read-only... "); + reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xdc); /* BIOS_CNTL */ + debug(" BIOS Lockdown Enable: %s; BIOS Write-Enable: %s\n", + (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); + + reg8 &= ~(1 << 0); /* clear BIOSWE */ + pci_write_config8(PCI_DEV(0,0x1f,0), 0xdc, reg8); + + reg8 |= (1 << 1); /* set BLE */ + pci_write_config8(PCI_DEV(0,0x1f,0), 0xdc, reg8); + + reg32 = RCBA32(0x3410); /* GCS - General Control and Status */ + reg32 |= 1; /* BILD - BIOS Interface Lockdown */ + RCBA32(0x3410) = reg32; /* Set BUC.TS and GCS.BBS to RO */ +} + +static void lockdown_flash_ich9_empty_ops(void) +{ + /* Lock SPI interface with empty opcode registers */ + RCBA16(ICH9_SPI_PREOP) = 0x0000; + RCBA16(ICH9_SPI_OPTYPE) = 0x0000; + RCBA32(ICH9_SPI_OPMENU + 0) = 0x00000000; + RCBA32(ICH9_SPI_OPMENU + 4) = 0x00000000; + RCBA16(ICH9_SPI_HSFS) |= ICH9_SPI_HSFS_FLOCKDN; +} + +int intel_lockdown_flash(void) +{ + const u32 reg32 = pci_read_config32(PCI_DEV(0,0x1f, 0), 0); switch (reg32) { + /* ICH7 */ case 0x27b08086: case 0x27b88086: case 0x27b98086: case 0x27bd8086: - ich = ICH7; + lockdown_flash_ich7(); break; + /* ICH9 */ case 0x29128086: case 0x29148086: @@ -75,38 +100,17 @@ int intel_lockdown_flash(void) case 0x29178086: case 0x29188086: case 0x29198086: - ich = ICH9; + lockdown_flash_ich7(); + /* Coreboot doesn't use flash regions for ICH9 based + boards, so we just lock empty SPI opcodes instead + of setting up any write protection. */ + lockdown_flash_ich9_empty_ops(); break; default: debug("Not an ICH7 or ICH9 southbridge\n"); return -1; } - /* Now try this: */ - debug("Locking BIOS to read-only... "); - reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xdc); /* BIOS_CNTL */ - debug(" BIOS Lockdown Enable: %s; BIOS Write-Enable: %s\n", - (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); - - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(PCI_DEV(0,0x1f,0), 0xdc, reg8); - - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(PCI_DEV(0,0x1f,0), 0xdc, reg8); - - reg32 = RCBA32(0x3410); /* GCS - General Control and Status */ - reg32 |= 1; /* BILD - BIOS Interface Lockdown */ - RCBA32(0x3410) = reg32; /* Set BUC.TS and GCS.BBS to RO */ - - /* Lock SPI interface with empty opcode registers on ICH9. */ - if (ICH9 == ich) { - RCBA16(ICH9_SPI_PREOP) = 0x0000; - RCBA16(ICH9_SPI_OPTYPE) = 0x0000; - RCBA32(ICH9_SPI_OPMENU + 0) = 0x00000000; - RCBA32(ICH9_SPI_OPMENU + 4) = 0x00000000; - RCBA16(ICH9_SPI_HSFS) |= ICH9_SPI_HSFS_FLOCKDN; - } - debug("BIOS hard locked until next full reset.\n"); return 0;

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New patch to review for coreboot: 2b73722 sandybridge: Add option to lock SPI regions on resume
by Nico Huber 03 Jul '13

03 Jul '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3594 -gerrit commit 2b73722bf3071c2d01d099e5a7cc488b5bf17ece Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Jul 1 16:02:36 2013 +0200 sandybridge: Add option to lock SPI regions on resume Add an option to mark all SPI regions write protected on each S3 resume. We were used to lock the SPI interface in the payload which isn't run on the resume path. So we have to do it here. For the write protection to be effective, all write opcodes in the opmenu have to be marked correctly (as write operations) and the whole SPI interface has to be locked. Both is already done. Change-Id: I5c268ae8850642f5e82f18c28c71cf1ae248dbff Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/southbridge/intel/bd82x6x/Kconfig | 10 ++++++++++ src/southbridge/intel/bd82x6x/finalize.c | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 0be875e..e6a4fc8 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -148,4 +148,14 @@ config LOCK_MANAGEMENT_ENGINE If unsure, say N. +config LOCK_SPI_ON_RESUME + bool "Lock all flash ROM sections on S3 resume" + default n + help + If the flash ROM shall be protected against write accesses from the + operating system (OS), the locking procedure has to be repeated after + each resume from S3. Select this if you never want to update the flash + ROM from within your OS. Notice: Even with this option, the write lock + has still to be enabled on the normal boot path (e.g. by the payload). + endif diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index bcc2f3d..331e26c 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -26,6 +26,14 @@ void intel_pch_finalize_smm(void) { +#if CONFIG_LOCK_SPI_ON_RESUME + /* Copy flash regions from FREG0-4 to PR0-4 + and enable write protection bit31 */ + int i; + for (i = 0; i < 20; i += 4) + RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | (1 << 31); +#endif + /* Set SPI opcode menu */ RCBA16(0x3894) = SPI_OPPREFIX; RCBA16(0x3896) = SPI_OPTYPE;

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Patch merged into coreboot/master: 1c81128 pnp: Add some default functions to enter/exit config state
by gerrit＠coreboot.org 03 Jul '13

03 Jul '13

the following patch was just integrated into master: commit 1c81128dcd3a723f75d554b0a8d87101d7dd3663 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jun 15 20:33:44 2013 +0200 pnp: Add some default functions to enter/exit config state Implement some common default functions to enter and exit the configuration state. Also provide default pnp_mode_ops for common enter()/exit() function pairs. The following cocci ensures their use: @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; @ enter_match_8787 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } @ depends on enter_match_8787 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_8787, }; @ enter_match_55 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x55, dev->path.pnp.port); } @ depends on enter_match_55 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_55, }; @ depends on enter_match_8787 || enter_match_55 @ identifier mode_match.enter; @@ -enter(...) {...} @ exit_match_aa @ identifier mode_match.exit, dev; @@ exit(...) { outb(0xaa, dev->path.pnp.port); } @ depends on exit_match_aa @ identifier mode_match.exit, mode_match.ops; @@ struct pnp_mode_ops ops = { - .exit_conf_mode = exit, + .exit_conf_mode = pnp_exit_conf_mode_aa, }; @ depends on exit_match_aa @ identifier mode_match.exit; @@ -exit(...) {...} @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @ @@ #include <device/pnp.h> +#include <superio/conf_mode.h> @ mode_match_55_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_55, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_55_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_55_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; @ mode_match_8787_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_8787_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_8787_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/3484 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/3484 for details. -gerrit

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New patch to review for coreboot: f53cdaf lint: Use temporary build directory
by Nico Huber 03 Jul '13

03 Jul '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3593 -gerrit commit f53cdafb2e9a408c05ad5de400dc8da3258e630f Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jul 2 16:39:28 2013 +0200 lint: Use temporary build directory `util/lint/lint-stable-002-build-dir-handling` always overwrites your current `config.h` and `auto.conf` when the pre-commit hook is run. It can be very confusing when your configuration is suddenly broken. So fix it by not using the default build directory. Change-Id: If2bbc97ac2f12a8203a3769d813386a023f93dd6 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/lint/lint-stable-002-build-dir-handling | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/util/lint/lint-stable-002-build-dir-handling b/util/lint/lint-stable-002-build-dir-handling index 2dad8a6..0954cd4 100755 --- a/util/lint/lint-stable-002-build-dir-handling +++ b/util/lint/lint-stable-002-build-dir-handling @@ -53,9 +53,10 @@ if [ "$MAKE" = "" ]; then fi # prepare a config to use +TMPOBJ=`mktemp -d .tmpobj.XXXXXX` TMPCONFIG=`mktemp .tmpconfig.XXXXXX` rm -f $TMPCONFIG -$MAKE DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null +$MAKE obj=$TMPOBJ DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null # look up parent directory CURRENTDIR=`pwd -P` @@ -66,5 +67,5 @@ compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/o compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.romstage.o" compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.romstage.o" -rm -f $TMPCONFIG +rm -rf $TMPCONFIG $TMPOBJ

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New patch to review for coreboot: e61dcc9 w83627hf/acpi: Fix offset of logical device activation
by Nico Huber 03 Jul '13

03 Jul '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3592 -gerrit commit e61dcc93252eafba1845cbd355aeba8079c1f5a9 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Jul 3 12:07:43 2013 +0200 w83627hf/acpi: Fix offset of logical device activation The PnP's logical device activation normally resides at 0x30. This might have been overlooked as 0x29 looks very close to 0x30 in human eyes. Change-Id: Id5d5a92f2683ebe1808b943f686c062151d216da Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/superio/winbond/w83627hf/acpi/superio.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index ff95dfc..84d46f8 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -113,6 +113,7 @@ Device(SIO) { LCKC, 1, /* Lock Configuration Registers */ Offset (0x29), IO3S, 8, /* GPIO3 pin selection register */ + Offset (0x30), ACTR, 1, /* Logical device activation */ ACT1, 1, /* Logical part activation 1 (mostly unused) */ ACT2, 1, /* Logical part activation 2 (mostly unused) */

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Patch set updated for coreboot: 264c623 lenovo/x60/romstage.c: Collect timestamps in romstage
by Paul Menzel 03 Jul '13

03 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3587 -gerrit commit 264c6237bf70054758859892a67fbba82b15e613 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jul 2 09:54:17 2013 +0200 lenovo/x60/romstage.c: Collect timestamps in romstage Collect early timestamps in Lenovo X60’s romstage like the Lenovo T60 does (»lenovo/t60: Collect timestamps in romstage« (44c392f8) [1]). Selecting the option `COLLECT_TIMESTAMPS` in Kconfig and then doing `cbmem --timestamps` should output the timestamps. [1] http://review.coreboot.org/3499 Change-Id: I7bd30f03a1b85c38e89c19cdf88b2d20b24abed8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/romstage.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 222b999..4d0eac7 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -30,6 +30,7 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <cbmem.h> +#include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -218,6 +219,20 @@ void main(unsigned long bist) int cbmem_was_initted; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; +#if CONFIG_COLLECT_TIMESTAMPS + tsc_t start_romstage_time; + tsc_t before_dram_time; + tsc_t after_dram_time; + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; +#endif + +#if CONFIG_COLLECT_TIMESTAMPS + start_romstage_time = rdtsc(); +#endif + if (bist == 0) enable_lapic(); @@ -281,7 +296,13 @@ void main(unsigned long bist) dump_spd_registers(); #endif +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = rdtsc(); +#endif sdram_initialize(boot_mode, spd_addrmap); +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = rdtsc(); +#endif /* Perform some initialization that must run before stage2 */ early_ich7_init(); @@ -340,6 +361,14 @@ void main(unsigned long bist) } #endif +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit();

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Patch set updated for coreboot: 699013f Winbond W83627HF: ACPI: Make `AddressMax` a multiple of `AddressAlignment`
by Paul Menzel 03 Jul '13

03 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2942 -gerrit commit 699013f1ae635e01ee4244070b4cc763134aea71 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Mar 28 14:59:34 2013 +0100 Winbond W83627HF: ACPI: Make `AddressMax` a multiple of `AddressAlignment` When hooking the ASL into the DSDT of the ASRock E350M1, the build fails with the following error. $ LANG=C make […] IASL build/mainboard/asrock/e350m1/dsdt.ramstage.o Intel ACPI Component Architecture ASL Optimizing Compiler version 20121114-32 [Apr 22 2013] Copyright (c) 2000 - 2012 Intel Corporation dsdt.ramstage.asl 1779: CreateByteField (Arg0, IRQ0._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 1917: IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) Error 4001 - ^ Must be a multiple of alignment/granularity value dsdt.ramstage.asl 2051: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 2160: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 2269: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 2341: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 2424: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 2491: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) ASL Input: dsdt.ramstage.asl - 2996 lines, 59383 bytes, 1610 keywords Hex Dump: dsdt.ramstage.hex - 160002 bytes Compilation complete. 1 Errors, 7 Warnings, 0 Remarks, 553 Optimizations make: *** [build/mainboard/asrock/e350m1/dsdt.ramstage.o] Error 255 […] According to the ACPI specification the maximum acceptable starting address `AddressMax` has to be a multiple of the alignment granularity for the I/O address. Citing ACPI specification 4.0a, page 612 [1]. 18.5.56 IO (IO Resource Descriptor Macro) ### Syntax IO (Decode, AddressMin, AddressMax, AddressAlignment, RangeLength, DescriptorName) => Buffer ### Argument […] AddressMax evaluates to a 16-bit integer that specifies the maximum acceptable starting address for the I/O range. It must be an even multiple of AddressAlignment. The field DescriptorName._MAX is automatically created to refer to this portion of the resource descriptor. Using address 0x0FF8, a multiple of 0x08, instead of 0x0FFC, fixes the error. [1] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf Change-Id: I272e09d091149791f2867b1d06e4fc27bc1bb2cd Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/superio/winbond/w83627hf/acpi/superio.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index ff95dfc..67cf67a 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -559,7 +559,7 @@ Device(SIO) { /* Any configurable address (EPP mode) */ StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) IRQNoFlags () {3,4,5,7,9,10,11,12} } /* Any configurable address (No EPP mode) */

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Patch set updated for coreboot: e9f6c9e ASRock E350M1: Include ASL file of Winbond W83627HF in the DSDT
by Paul Menzel 03 Jul '13

03 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2943 -gerrit commit e9f6c9e759c97dfb0a188b4b4001e4e608765165 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Mar 28 14:05:45 2013 +0100 ASRock E350M1: Include ASL file of Winbond W83627HF in the DSDT Unfortunately there are still some problems, but note that the ASRock E350M1 actually has a Nuvoton NCT6775F, which is supposed to be compatible though [1]. At least Scott chose it in its `devicetree.cb`. Hooking up this ACPI snippet, under Linux, serial does not work anymore. It works fine for coreboot, SeaBIOS and GRUB. $ grep -i -e 8042 -e kbd -e mpu -e pnp /tmp/kern.log | cut -d " " -f 7- [ 0.210990] acpi PNP0A08:00: Requesting ACPI _OSC control (0x1d) [ 0.211079] acpi PNP0A08:00: ACPI _OSC control (0x1d) granted [ 0.215591] calling pnp_init+0x0/0xf @ 1 [ 0.215616] initcall pnp_init+0x0/0xf returned 0 after 0 usecs [ 0.222362] calling pnp_system_init+0x0/0xa @ 1 [ 0.222399] initcall pnp_system_init+0x0/0xa returned 0 after 29 usecs [ 0.222404] calling pnpacpi_init+0x0/0x77 @ 1 [ 0.222407] pnp: PnP ACPI init [ 0.222438] ACPI: bus type PNP registered [ 0.223012] pnp 00:00: Plug and Play ACPI device, IDs PNP0b00 (active) [ 0.223156] pnp 00:01: Plug and Play ACPI device, IDs PNP0800 (active) [ 0.223186] pnp 00:02: [dma 4] [ 0.223233] pnp 00:02: Plug and Play ACPI device, IDs PNP0200 (active) [ 0.223363] pnp 00:03: Plug and Play ACPI device, IDs PNP0c04 (active) [ 0.223718] pnp 00:04: Plug and Play ACPI device, IDs PNP0a05 (active) [ 0.223994] pnp 00:05: Plug and Play ACPI device, IDs PNP0700 (disabled) [ 0.224304] pnp 00:06: Plug and Play ACPI device, IDs PNP0400 (disabled) [ 0.224581] pnp 00:07: Plug and Play ACPI device, IDs PNP0501 (disabled) [ 0.224886] pnp 00:08: Plug and Play ACPI device, IDs PNP0501 (disabled) [ 0.225336] pnp 00:09: Plug and Play ACPI device, IDs PNP0303 (disabled) [ 0.225610] pnp 00:0a: Plug and Play ACPI device, IDs PNP0f13 (disabled) [ 0.225849] pnp 00:0b: Plug and Play ACPI device, IDs PNPb02f (disabled) [ 0.226083] pnp 00:0c: Plug and Play ACPI device, IDs PNPb006 (disabled) [ 0.226339] system 00:0d: Plug and Play ACPI device, IDs PNP0c02 (disabled) [ 0.226357] pnp: PnP ACPI: found 14 devices [ 0.226360] ACPI: bus type PNP unregistered [ 0.226437] initcall pnpacpi_init+0x0/0x77 returned 0 after 3930 usecs [ 0.226443] calling pnpbios_init+0x0/0x31c @ 1 [ 0.226448] PnPBIOS: Disabled by ACPI PNP [ 0.226455] initcall pnpbios_init+0x0/0x31c returned -19 after 5 usecs [ 0.921532] calling pnpbios_thread_init+0x0/0x54 @ 1 [ 0.921540] initcall pnpbios_thread_init+0x0/0x54 returned 0 after 0 usecs [ 0.921545] calling isapnp_init+0x0/0x5c6 @ 1 [ 0.921549] isapnp: ISA Plug & Play support disabled [ 0.921555] initcall isapnp_init+0x0/0x5c6 returned 0 after 3 usecs [ 0.947430] calling i8042_init+0x0/0x383 @ 1 [ 0.947540] i8042 kbd 00:09: [irq 1] [ 0.947549] i8042 kbd 00:09: unable to assign resources [ 2.552437] i8042 kbd: probe of 00:09 failed with error -16 [ 2.552657] i8042 aux 00:0a: [irq 12] [ 2.553260] i8042 aux 00:0a: activated [ 2.553283] i8042: PNP: PS/2 Controller [PNP0f13:PS2M] at 0x0,0x0 irq 12 [ 2.553287] i8042: PNP: PS/2 controller has invalid data port 0x0; using default 0x60 [ 2.553290] i8042: PNP: PS/2 controller has invalid command port 0x0; using default 0x64 [ 2.553293] i8042: PNP: PS/2 controller doesn't have KBD irq; using default 1 [ 2.807764] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 2.807869] initcall i8042_init+0x0/0x383 returned 0 after 1816824 usecs [ 2.808424] calling atkbd_init+0x0/0x1b @ 1 [ 2.808474] initcall atkbd_init+0x0/0x1b returned 0 after 42 usecs [ 2.808479] calling xenkbd_init+0x0/0x28 @ 1 [ 2.808484] initcall xenkbd_init+0x0/0x28 returned -19 after 0 usecs [ 68.133211] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input2 [ 71.322602] calling alsa_mpu401_uart_init+0x0/0x1000 [snd_mpu401_uart] @ 697 [ 71.322615] initcall alsa_mpu401_uart_init+0x0/0x1000 [snd_mpu401_uart] returned 0 after 0 usecs [ 73.965508] calling alsa_card_mpu401_init+0x0/0x1000 [snd_mpu401] @ 697 [ 73.965574] mpu401: probe of 00:0c failed with error -16 [ 73.965590] MPU-401 device not found or device busy [ 75.509538] initcall alsa_card_mpu401_init+0x0/0x1000 [snd_mpu401] returned -19 after 1507823 usecs [1] https://www.kernel.org/doc/Documentation/hwmon/w83627ehf Change-Id: I82c98f16e6879d47594fcf90140a827b98a39a7f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/dsdt.asl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 0620360..f64ea95 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -48,6 +48,9 @@ DefinitionBlock ( #include <southbridge/amd/cimx/sb800/acpi/fch.asl> } + + #include <superio/winbond/w83627hf/acpi/superio.asl> + } /* End Scope(_SB) */ /* Contains the supported sleep states for this chipset */

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Patch merged into coreboot/master: abe6847 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`
by gerrit＠coreboot.org 02 Jul '13

02 Jul '13

the following patch was just integrated into master: commit abe6847cd21b553dd66fcb0540de166f82ebaf00 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed May 8 17:08:55 2013 +0200 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c` Use the same indentation, comment placement and spelling of words. Run `indent -linux …`. Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3220 Reviewed-by: Nico Huber <nico.huber(a)secunet.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3220 for details. -gerrit

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coreboot-gerrit July 2013