Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3602
-gerrit
commit aa5d3373563760390f3c34a0d8d0366eff4eaefd
Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
Date: Thu Jul 4 02:51:42 2013 +0200
w83627hf/acpi: Fix endianess error in floppy drive enumeration code
The enumeration results are stored as five DWORDs in one 20 byte buffer.
Bytes 3, 7, 11 and 15 were used to set the lowest bit of each DWORD.
ACPI uses little endian, so 1, 4, 8 and 12 are the correct indices.
Change-Id: I793225cb1bb62fd148ecfa1e61e02f5d7be62cdb
Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
---
src/superio/winbond/w83627hf/acpi/superio.asl | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl
index ff95dfc..5058d89 100644
--- a/src/superio/winbond/w83627hf/acpi/superio.asl
+++ b/src/superio/winbond/w83627hf/acpi/superio.asl
@@ -351,10 +351,10 @@ Device(SIO) {
}
OperationRegion (FIO2, SystemIO, 0x3F7, 0x01)
- CreateByteField (_FDE, 3, FD1)
- CreateByteField (_FDE, 7, FD2)
- CreateByteField (_FDE, 11, FD3)
- CreateByteField (_FDE, 15, FD4)
+ CreateByteField (_FDE, 1, FD1)
+ CreateByteField (_FDE, 4, FD2)
+ CreateByteField (_FDE, 8, FD3)
+ CreateByteField (_FDE, 12, FD4)
Store(One, ACT1)
Store(0, SELE)
Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3603
-gerrit
commit b656b2e4fb95492623d371c5e0e87ba3ed7fbd08
Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
Date: Thu Jul 4 02:54:04 2013 +0200
w83627hf/acpi: Fix type error in floppy drive enumeration code
The enumeration method tried to evaluate an one-byte OperationRegion
instead of a field in this OperationRegion, which resulted in an
AE_TYPE error at runtime.
Indexing the OperationRegion with a single field fixes this error.
Change-Id: I15dd7aa6ecafb3a215d165d2b721003446815025
Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
---
src/superio/winbond/w83627hf/acpi/superio.asl | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl
index 5058d89..e8c031a 100644
--- a/src/superio/winbond/w83627hf/acpi/superio.asl
+++ b/src/superio/winbond/w83627hf/acpi/superio.asl
@@ -350,6 +350,10 @@ Device(SIO) {
DATA, 8,
}
OperationRegion (FIO2, SystemIO, 0x3F7, 0x01)
+ Field (FIO2, ByteAcc, NoLock, Preserve)
+ {
+ SIFR, 8
+ }
CreateByteField (_FDE, 1, FD1)
CreateByteField (_FDE, 4, FD2)
@@ -359,25 +363,25 @@ Device(SIO) {
Store(One, ACT1)
Store(0, SELE)
Sleep(0x64)
- If (FIO2) { Store (One, FD1) }
+ If (SIFR) { Store (One, FD1) }
Store(Zero, ACT1)
Store(One, ACT2)
Store(1, SELE)
Sleep(0x64)
- If (FIO2) { Store (One, FD2) }
+ If (SIFR) { Store (One, FD2) }
Store(Zero, ACT2)
Store(One, ACT3)
Store(2, SELE)
Sleep(0x64)
- If (FIO2) { Store (One, FD3) }
+ If (SIFR) { Store (One, FD3) }
Store(Zero, ACT3)
Store(One, ACT4)
Store(3, SELE)
Sleep(0x64)
- If (FIO2) { Store (One, FD4) }
+ If (SIFR) { Store (One, FD4) }
Store(Zero, ACT4)
Store(Zero, SELE)
#endif
Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3603
-gerrit
commit afff4d2e00cafa909444569bb2a6bebb7672de58
Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
Date: Thu Jul 4 02:54:04 2013 +0200
w83627hf/acpi: Fix type error in floppy drive enumeration code
The enumeration method tried to evaluate an one-byte OperationRegion
instead of a field in this OperationRegion, which resulted in an
AE_TYPE error at runtime.
Indexing the OperationRegion with a single field fixes this error.
Change-Id: I15dd7aa6ecafb3a215d165d2b721003446815025
Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
---
src/superio/winbond/w83627hf/acpi/superio.asl | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl
index 5058d89..e8c031a 100644
--- a/src/superio/winbond/w83627hf/acpi/superio.asl
+++ b/src/superio/winbond/w83627hf/acpi/superio.asl
@@ -350,6 +350,10 @@ Device(SIO) {
DATA, 8,
}
OperationRegion (FIO2, SystemIO, 0x3F7, 0x01)
+ Field (FIO2, ByteAcc, NoLock, Preserve)
+ {
+ SIFR, 8
+ }
CreateByteField (_FDE, 1, FD1)
CreateByteField (_FDE, 4, FD2)
@@ -359,25 +363,25 @@ Device(SIO) {
Store(One, ACT1)
Store(0, SELE)
Sleep(0x64)
- If (FIO2) { Store (One, FD1) }
+ If (SIFR) { Store (One, FD1) }
Store(Zero, ACT1)
Store(One, ACT2)
Store(1, SELE)
Sleep(0x64)
- If (FIO2) { Store (One, FD2) }
+ If (SIFR) { Store (One, FD2) }
Store(Zero, ACT2)
Store(One, ACT3)
Store(2, SELE)
Sleep(0x64)
- If (FIO2) { Store (One, FD3) }
+ If (SIFR) { Store (One, FD3) }
Store(Zero, ACT3)
Store(One, ACT4)
Store(3, SELE)
Sleep(0x64)
- If (FIO2) { Store (One, FD4) }
+ If (SIFR) { Store (One, FD4) }
Store(Zero, ACT4)
Store(Zero, SELE)
#endif
Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3602
-gerrit
commit 7551db6fcba4f7ba0aa27c21bdd41dfebab7fd5f
Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
Date: Thu Jul 4 02:51:42 2013 +0200
w83627hf/acpi: Fix endianess error in floppy drive enumeration code
The enumeration results are stored as five DWORDs in one 20 byte buffer.
Bytes 3, 7, 11 and 15 were used to set the lowest bit of each DWORD.
ACPI uses little endian, so 1, 4, 8 and 12 are the correct indices.
Change-Id: I793225cb1bb62fd148ecfa1e61e02f5d7be62cdb
Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
---
src/superio/winbond/w83627hf/acpi/superio.asl | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl
index ff95dfc..5058d89 100644
--- a/src/superio/winbond/w83627hf/acpi/superio.asl
+++ b/src/superio/winbond/w83627hf/acpi/superio.asl
@@ -351,10 +351,10 @@ Device(SIO) {
}
OperationRegion (FIO2, SystemIO, 0x3F7, 0x01)
- CreateByteField (_FDE, 3, FD1)
- CreateByteField (_FDE, 7, FD2)
- CreateByteField (_FDE, 11, FD3)
- CreateByteField (_FDE, 15, FD4)
+ CreateByteField (_FDE, 1, FD1)
+ CreateByteField (_FDE, 4, FD2)
+ CreateByteField (_FDE, 8, FD3)
+ CreateByteField (_FDE, 12, FD4)
Store(One, ACT1)
Store(0, SELE)
the following patch was just integrated into master:
commit 9e974232e4896ee971745c5127cbc37f1682171b
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Mon Jul 1 11:21:53 2013 +0300
intel/i5000: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on two boards
with i5000 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.
Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/3601 for details.
-gerrit
the following patch was just integrated into master:
commit 575e6817e690d1540bfa14a0b1fc7b8a40ef095a
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 2 11:37:35 2013 +0300
Move select MMCONF_SUPPORT under northbridge (fix)
I missed the board with gm45 when I moved MMCONF_SUPPORT lines.
Also, the intel/i3100 does not have MMCONF_SUPPORT implemented
even though it was previously selected for intel/eagleheights board.
Change-Id: I9c7f6b0a150b4d54288a1e015277b9d98467fca4
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3598
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/3598 for details.
-gerrit
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3601
-gerrit
commit 4cf124f57faa59f49cf06f8ecc8a762bf5bde785
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Mon Jul 1 11:21:53 2013 +0300
intel/i5000: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on two boards
with i5000 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.
Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/asus/dsbf/romstage.c | 4 ----
src/mainboard/supermicro/x7db8/romstage.c | 4 ----
src/northbridge/intel/i5000/Kconfig | 10 +++++++++-
src/northbridge/intel/i5000/bootblock.c | 21 +++++++++++++++++++++
4 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c
index cb63f45..f4e65cb 100644
--- a/src/mainboard/asus/dsbf/romstage.c
+++ b/src/mainboard/asus/dsbf/romstage.c
@@ -129,10 +129,6 @@ void main(unsigned long bist)
enable_smbus();
- /* setup PCIe MMCONF base address */
- pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
- CONFIG_MMCONF_BASE_ADDRESS >> 16);
-
smbus_write_byte(0x6f, 0x00, 0x63);
smbus_write_byte(0x6f, 0x01, 0x04);
smbus_write_byte(0x6f, 0x02, 0x53);
diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c
index fa73412..bc54ed7 100644
--- a/src/mainboard/supermicro/x7db8/romstage.c
+++ b/src/mainboard/supermicro/x7db8/romstage.c
@@ -128,10 +128,6 @@ void main(unsigned long bist)
enable_smbus();
- /* setup PCIe MMCONF base address */
- pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
- CONFIG_MMCONF_BASE_ADDRESS >> 16);
-
outb(0x07, 0x11b8);
/* These are smbus write captured with serialice. They
diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig
index b9c3547..f7344ca 100644
--- a/src/northbridge/intel/i5000/Kconfig
+++ b/src/northbridge/intel/i5000/Kconfig
@@ -20,9 +20,17 @@
config NORTHBRIDGE_INTEL_I5000
bool
select MMCONF_SUPPORT
+ select MMCONF_SUPPORT_DEFAULT
select HAVE_DEBUG_RAM_SETUP
+if NORTHBRIDGE_INTEL_I5000
+
config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
bool
prompt "Run ramcheck after RAM initialization"
- depends on NORTHBRIDGE_INTEL_I5000
+
+config BOOTBLOCK_NORTHBRIDGE_INIT
+ string
+ default "northbridge/intel/i5000/bootblock.c"
+
+endif
diff --git a/src/northbridge/intel/i5000/bootblock.c b/src/northbridge/intel/i5000/bootblock.c
new file mode 100644
index 0000000..eabbee6
--- /dev/null
+++ b/src/northbridge/intel/i5000/bootblock.c
@@ -0,0 +1,21 @@
+#include <arch/io.h>
+
+static void bootblock_northbridge_init(void)
+{
+ /*
+ * The "io" variant of the config access is explicitly used to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * to true. That way all subsequent non-explicit config accesses use
+ * MCFG. This code also assumes that bootblock_northbridge_init() is
+ * the first thing called in the non-asm boot block code. The final
+ * assumption is that no assembly code is using the
+ * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+ *
+ * The PCIEXBAR is assumed to live in the memory mapped IO space under
+ * 4GiB.
+ */
+
+ /* setup PCIe MMCONF base address */
+ pci_io_write_config32(PCI_DEV(0, 16, 0), 0x64,
+ CONFIG_MMCONF_BASE_ADDRESS >> 16);
+}