Patch set updated for coreboot: fc2357f w83627hf/acpi: Fix logical device power down in ACPI
by Christoph Grenz 06 Jul '13
by Christoph Grenz 06 Jul '13
06 Jul '13
Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3605
-gerrit
commit fc2357fc57c254111d73bb0294f00c8c3ee61924
Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
Date: Thu Jul 4 03:41:39 2013 +0200
w83627hf/acpi: Fix logical device power down in ACPI
As Nico noticed for the W83627DHG, the power management bits to power down
individual logical devices on Winbond superios are named counterintuitively
and need to be set when the logical device should be powered.
This corrects the power management methods for the W83627HF.
Change-Id: I98bccd550a0513c62bfa9480275f88c566691bc8
Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
---
src/superio/winbond/w83627hf/acpi/superio.asl | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl
index efb7fba..427d63c 100644
--- a/src/superio/winbond/w83627hf/acpi/superio.asl
+++ b/src/superio/winbond/w83627hf/acpi/superio.asl
@@ -242,13 +242,13 @@ Device(SIO) {
/* Disable power saving mode */
Method (_PS0) {
ENCM (0xFF)
- Store (Zero, FDPW)
+ Store (One, FDPW)
EXCM ()
}
/* Enable power saving mode */
Method (_PS1) {
ENCM (0xFF)
- Store (One, FDPW)
+ Store (Zero, FDPW)
EXCM ()
}
@@ -462,12 +462,12 @@ Device(SIO) {
}
Method (_PS0) {
ENCM (0xFF)
- Store (Zero, PRPW)
+ Store (One, PRPW)
EXCM ()
}
Method (_PS1) {
ENCM (0xFF)
- Store (One, PRPW)
+ Store (Zero, PRPW)
EXCM ()
}
@@ -639,12 +639,12 @@ Device(SIO) {
}
Method (_PS0) {
ENCM (0xFF)
- Store (Zero, UAPW)
+ Store (One, UAPW)
EXCM ()
}
Method (_PS1) {
ENCM (0xFF)
- Store (One, UAPW)
+ Store (Zero, UAPW)
EXCM ()
}
@@ -764,12 +764,12 @@ Device(SIO) {
}
Method (_PS0) {
ENCM (0xFF)
- Store (Zero, UBPW)
+ Store (One, UBPW)
EXCM ()
}
Method (_PS1) {
ENCM (0xFF)
- Store (One, UBPW)
+ Store (Zero, UBPW)
EXCM ()
}
@@ -889,12 +889,12 @@ Device(SIO) {
}
Method (_PS0) {
ENCM (0xFF)
- Store (Zero, UBPW)
+ Store (One, UBPW)
EXCM ()
}
Method (_PS1) {
ENCM (0xFF)
- Store (One, UBPW)
+ Store (Zero, UBPW)
EXCM ()
}
@@ -1414,14 +1414,14 @@ Device(SIO) {
Method (_PS0)
{
ENCM (0xFF)
- Store (Zero, HWPW)
+ Store (One, HWPW)
EXCM ()
}
Method (_PS1)
{
ENCM (0xFF)
- Store (One, HWPW)
+ Store (Zero, HWPW)
EXCM ()
}
1
0
Patch set updated for coreboot: 8b635bb CBFS: Use memmove instead of memcpy when loading a file from CBFS.
by Ronald G. Minnich 06 Jul '13
by Ronald G. Minnich 06 Jul '13
06 Jul '13
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3577
-gerrit
commit 8b635bb43568c0e9171bbdfb4e3a9e704759d041
Author: Gabe Black <gabeblack(a)chromium.org>
Date: Mon Jul 1 04:28:23 2013 -0700
CBFS: Use memmove instead of memcpy when loading a file from CBFS.
It might be the case that a file is being loaded from a portion of CBFS which
has already been loaded into a limitted bit of memory somewhere, and we want
to load that file in place, effectively, so that its original location in
CBFS overlaps with its new location. That's only guaranteed to work if you use
memmove instead of memcpy.
In the case that the copy is 'sane', i.e. dest <= src, we can just call
memcpy, which gets us the processor-optimized code. We've got no statistics
on how common the overlapping case is.
Change-Id: Id550138c875907749fff05f330fcd2fb5f9ed924
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/arch/armv7/Kconfig | 8 ++++++++
src/lib/Makefile.inc | 3 ++-
src/lib/cbfs_core.c | 2 +-
src/lib/memmove.c | 31 ++++++++++++++++++++++++++++---
4 files changed, 39 insertions(+), 5 deletions(-)
diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig
index 488ca97..eea6d40 100644
--- a/src/arch/armv7/Kconfig
+++ b/src/arch/armv7/Kconfig
@@ -49,4 +49,12 @@ config ARM_DCACHE_POLICY_WRITETHROUGH
bool
default n
+config HAVE_ARCH_MEMSET
+ bool
+ default n
+
+config HAVE_ARCH_MEMCPY
+ bool
+ default n
+
endmenu
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d44f4a7..88c34c1 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -26,6 +26,7 @@ ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
bootblock-y += memcpy.c
endif
bootblock-y += memcmp.c
+bootblock-y += memmove.c
ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
romstage-y += memset.c
@@ -115,7 +116,7 @@ endif
ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
smm-y += memcpy.c
endif
-smm-y += cbfs.c memcmp.c
+smm-y += cbfs.c memcmp.c memmove.c
smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
smm-$(CONFIG_USBDEBUG) += usbdebug.c
diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c
index 852b37f..39c1ff6 100644
--- a/src/lib/cbfs_core.c
+++ b/src/lib/cbfs_core.c
@@ -195,7 +195,7 @@ int cbfs_decompress(int algo, void *src, void *dst, int len)
{
switch (algo) {
case CBFS_COMPRESS_NONE:
- memcpy(dst, src, len);
+ memmove(dst, src, len);
return 0;
#ifdef CBFS_CORE_WITH_LZMA
case CBFS_COMPRESS_LZMA:
diff --git a/src/lib/memmove.c b/src/lib/memmove.c
index 241917c..e567da5 100644
--- a/src/lib/memmove.c
+++ b/src/lib/memmove.c
@@ -1,13 +1,38 @@
+/*
+ * Copyright 2013 Google Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
#include <string.h>
+
void *memmove(void *vdest, const void *vsrc, size_t count)
{
const char *src = vsrc;
char *dest = vdest;
+ /* N.B. You may be tempted to not copy in the case
+ * that dest == src. Please don't make that mistake.
+ */
if (dest <= src) {
- while (count--) {
- *dest++ = *src++;
- }
+ /* easy way to get the processor-optimized copy */
+ memcpy(vdest, vsrc, count);
} else {
src += count - 1;
dest += count - 1;
1
0
Patch set updated for coreboot: 508606d CBFS: Use memmove instead of memcpy when loading a file from CBFS.
by Ronald G. Minnich 06 Jul '13
by Ronald G. Minnich 06 Jul '13
06 Jul '13
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3577
-gerrit
commit 508606d5e805e2669d9b6ad7ed9695bfd0970fb0
Author: Gabe Black <gabeblack(a)chromium.org>
Date: Mon Jul 1 04:28:23 2013 -0700
CBFS: Use memmove instead of memcpy when loading a file from CBFS.
It might be the case that a file is being loaded from a portion of CBFS which
has already been loaded into a limitted bit of memory somewhere, and we want
to load that file in place, effectively, so that it's original location in
CBFS overlaps with its new location. That's only guaranteed to work if you use
memmove instead of memcpy.
One significant downside of this change is that there aren't yet architecture
optimized (aka not horribly performing) implementations of memmove available
for either x86 or ARM. It's not clear whether the performance difference would
be significant enough to notice in practice since the things in CBFS are
probably not that big. It might still be a good idea to hold off on this
change until optimized versions are available to avoid any potential
performance hit.
This also means that memmove needs to be built into the bootblock.
Change-Id: Id550138c875907749fff05f330fcd2fb5f9ed924
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/arch/armv7/Kconfig | 8 ++++++++
src/lib/Makefile.inc | 3 ++-
src/lib/cbfs_core.c | 2 +-
src/lib/memmove.c | 23 +++++++++++++++++++++++
4 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig
index 488ca97..eea6d40 100644
--- a/src/arch/armv7/Kconfig
+++ b/src/arch/armv7/Kconfig
@@ -49,4 +49,12 @@ config ARM_DCACHE_POLICY_WRITETHROUGH
bool
default n
+config HAVE_ARCH_MEMSET
+ bool
+ default n
+
+config HAVE_ARCH_MEMCPY
+ bool
+ default n
+
endmenu
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d44f4a7..88c34c1 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -26,6 +26,7 @@ ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
bootblock-y += memcpy.c
endif
bootblock-y += memcmp.c
+bootblock-y += memmove.c
ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
romstage-y += memset.c
@@ -115,7 +116,7 @@ endif
ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
smm-y += memcpy.c
endif
-smm-y += cbfs.c memcmp.c
+smm-y += cbfs.c memcmp.c memmove.c
smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
smm-$(CONFIG_USBDEBUG) += usbdebug.c
diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c
index 852b37f..39c1ff6 100644
--- a/src/lib/cbfs_core.c
+++ b/src/lib/cbfs_core.c
@@ -195,7 +195,7 @@ int cbfs_decompress(int algo, void *src, void *dst, int len)
{
switch (algo) {
case CBFS_COMPRESS_NONE:
- memcpy(dst, src, len);
+ memmove(dst, src, len);
return 0;
#ifdef CBFS_CORE_WITH_LZMA
case CBFS_COMPRESS_LZMA:
diff --git a/src/lib/memmove.c b/src/lib/memmove.c
index 241917c..b4f5b92 100644
--- a/src/lib/memmove.c
+++ b/src/lib/memmove.c
@@ -1,4 +1,27 @@
+/*
+ * Copyright 2013 Google Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
#include <string.h>
+
void *memmove(void *vdest, const void *vsrc, size_t count)
{
const char *src = vsrc;
1
0
Patch merged into coreboot/master: 8cfa33e am335x: Implement support for the UART.
by gerritï¼ coreboot.org 06 Jul '13
by gerritï¼ coreboot.org 06 Jul '13
06 Jul '13
the following patch was just integrated into master:
commit 8cfa33eb7c93c0b4fb24a520b4c521591720999d
Author: Gabe Black <gabeblack(a)chromium.org>
Date: Tue Jun 11 21:58:18 2013 -0400
am335x: Implement support for the UART.
This patch was started by Dave Hendricks and implements the procedure for
setting up the UART as described in the manual. Some unused code was removed.
Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3490
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/3490 for details.
-gerrit
1
0
Patch set updated for coreboot: 96d59ec am335x: Implement support for the UART.
by Ronald G. Minnich 06 Jul '13
by Ronald G. Minnich 06 Jul '13
06 Jul '13
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3490
-gerrit
commit 96d59eca7aebe20009892e6d71d50ab4e258f311
Author: Gabe Black <gabeblack(a)chromium.org>
Date: Tue Jun 11 21:58:18 2013 -0400
am335x: Implement support for the UART.
This patch was started by Dave Hendricks and implements the procedure for
setting up the UART as described in the manual. Some unused code was removed.
Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/ti/am335x/uart.c | 178 ++++++++++++++++++++++++++++++++---------------
1 file changed, 123 insertions(+), 55 deletions(-)
diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c
index fdf5c05..395ed86 100644
--- a/src/cpu/ti/am335x/uart.c
+++ b/src/cpu/ti/am335x/uart.c
@@ -1,9 +1,5 @@
/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang(a)samsung.com>
- * Heungjun Kim <riverful.kim(a)samsung.com>
- *
- * based on drivers/serial/s3c64xx.c
+ * Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,9 +14,9 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
*/
+#include <config.h>
#include <types.h>
#include <uart.h>
#include <arch/io.h>
@@ -29,9 +25,14 @@
#include <cpu/ti/am335x/uart.h>
-#define RX_FIFO_COUNT_MASK 0xff
-#define RX_FIFO_FULL_MASK (1 << 8)
-#define TX_FIFO_FULL_MASK (1 << 24)
+#define EFR_ENHANCED_EN (1 << 4)
+#define FCR_FIFO_EN (1 << 0)
+#define MCR_TCR_TLR (1 << 6)
+#define SYSC_SOFTRESET (1 << 1)
+#define SYSS_RESETDONE (1 << 0)
+
+#define LSR_RXFIFOE (1 << 0)
+#define LSR_TXFIFOE (1 << 5)
/*
* Initialise the serial port with the given baudrate. The settings
@@ -39,28 +40,109 @@
*/
static void am335x_uart_init_dev(void)
{
- /* FIXME: implement this
- * ref: section 19.4.1.1.1 for reset
- * ref: section 19.4.1.1.2 for FIFO, skip DMA
- * ref: section 19.4.1.1.3 for baud rate, skip
- * interrupts and protocol stuff.
- * */
-#if 0
- struct s5p_uart *uart = (struct s5p_uart *)base_port;
-
- // TODO initialize with correct peripheral id by base_port.
- exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
-
- /* enable FIFOs */
- writel(0x1, &uart->ufcon);
- writel(0, &uart->umcon);
- /* 8N1 */
- writel(0x3, &uart->ulcon);
- /* No interrupts, no DMA, pure polling */
- writel(0x245, &uart->ucon);
-
- serial_setbrg_dev();
-#endif
+ struct am335x_uart *uart = (struct am335x_uart *)
+ CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+ uint16_t lcr_orig, efr_orig, mcr_orig;
+
+ /* reset the UART */
+ write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc);
+ while (!(read16(&uart->syss) & SYSS_RESETDONE))
+ ;
+
+ /* 1. switch to register config mode B */
+ lcr_orig = read16(&uart->lcr);
+ write16(0xbf, &uart->lcr);
+
+ /*
+ * 2. Set EFR ENHANCED_EN bit. To access this bit, registers must
+ * be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1.
+ */
+ efr_orig = read16(&uart->efr);
+ write16(efr_orig | EFR_ENHANCED_EN, &uart->efr);
+
+ /* 3. Switch to register config mode A */
+ write16(0x80, &uart->lcr);
+
+ /* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */
+ mcr_orig = read16(&uart->mcr);
+ write16(mcr_orig | MCR_TCR_TLR, &uart->mcr);
+
+ /* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */
+ write16(FCR_FIFO_EN, &uart->fcr);
+
+ /* 6. Switch to configuration mode B */
+ write16(0xbf, &uart->lcr);
+ /* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */
+
+ /* 9. Restore original EFR value */
+ write16(efr_orig, &uart->efr);
+
+ /* 10. Switch to config mode A */
+ write16(0x80, &uart->lcr);
+
+ /* 11. Restore original MCR value */
+ write16(mcr_orig, &uart->mcr);
+
+ /* 12. Restore original LCR value */
+ write16(lcr_orig, &uart->lcr);
+
+ /* Protocol, baud rate and interrupt settings */
+
+ /* 1. Disable UART access to DLL and DLH registers */
+ write16(read16(&uart->mdr1) | 0x7, &uart->mdr1);
+
+ /* 2. Switch to config mode B */
+ write16(0xbf, &uart->lcr);
+
+ /* 3. Enable access to IER[7:4] */
+ write16(efr_orig | EFR_ENHANCED_EN, &uart->efr);
+
+ /* 4. Switch to operational mode */
+ write16(0x0, &uart->lcr);
+
+ /* 5. Clear IER */
+ write16(0x0, &uart->ier);
+
+ /* 6. Switch to config mode B */
+ write16(0xbf, &uart->lcr);
+
+ /* 7. Set dll and dlh to the desired values (table 19-25) */
+ if (CONFIG_CONSOLE_SERIAL_9600) {
+ write16(0x01, &uart->dlh);
+ write16(0x38, &uart->dll);
+ } else if (CONFIG_CONSOLE_SERIAL_19200) {
+ write16(0x00, &uart->dlh);
+ write16(0x9c, &uart->dll);
+ } else if (CONFIG_CONSOLE_SERIAL_38400) {
+ write16(0x00, &uart->dlh);
+ write16(0x4e, &uart->dll);
+ } else if (CONFIG_CONSOLE_SERIAL_57600) {
+ write16(0x00, &uart->dlh);
+ write16(0x34, &uart->dll);
+ } else if (CONFIG_CONSOLE_SERIAL_115200) {
+ write16(0x00, &uart->dlh);
+ write16(0x1a, &uart->dll);
+ } else {
+ /* Unrecognized baud rate? */
+ }
+
+ /* 8. Switch to operational mode to access ier */
+ write16(0x0, &uart->lcr);
+
+ /* 9. Clear ier to disable all interrupts */
+ write16(0x0, &uart->ier);
+
+ /* 10. Switch to config mode B */
+ write16(0xbf, &uart->lcr);
+
+ /* 11. Restore efr */
+ write16(efr_orig, &uart->efr);
+
+ /* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */
+ write16(0x3, &uart->lcr);
+
+ /* 13. Load the new UART mode */
+ write16(0x0, &uart->mdr1);
}
/*
@@ -70,20 +152,12 @@ static void am335x_uart_init_dev(void)
*/
static unsigned char am335x_uart_rx_byte(void)
{
- /* FIXME: stub */
-#if 0
- struct s5p_uart *uart = (struct s5p_uart *)base_port;
-
- /* wait for character to arrive */
- while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
- RX_FIFO_FULL_MASK))) {
- if (exynos5_uart_err_check(0))
- return 0;
- }
+ struct am335x_uart *uart =
+ (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
- return readb(&uart->urxh) & 0xff;
-#endif
- return 0xaa;
+ while (!(read16(&uart->lsr) & LSR_RXFIFOE));
+
+ return read8(&uart->rhr);
}
/*
@@ -91,18 +165,12 @@ static unsigned char am335x_uart_rx_byte(void)
*/
static void am335x_uart_tx_byte(unsigned char data)
{
- /* FIXME: stub */
-#if 0
- struct s5p_uart *uart = (struct s5p_uart *)base_port;
-
- /* wait for room in the tx FIFO */
- while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
- if (exynos5_uart_err_check(1))
- return;
- }
+ struct am335x_uart *uart =
+ (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
- writeb(data, &uart->utxh);
-#endif
+ while (!(read16(&uart->lsr) & LSR_TXFIFOE));
+
+ return write8(data, &uart->thr);
}
uint32_t uartmem_getbaseaddr(void)
1
0
Patch merged into coreboot/master: 8522f99 Add support for DMP Vortex86EX PCI mainboard.
by gerritï¼ coreboot.org 05 Jul '13
by gerritï¼ coreboot.org 05 Jul '13
05 Jul '13
the following patch was just integrated into master:
commit 8522f9940af8291772e37eef077339d6f3ffcda9
Author: Andrew Wu <arw(a)dmp.com.tw>
Date: Fri Jul 5 17:29:41 2013 +0800
Add support for DMP Vortex86EX PCI mainboard.
Change-Id: I8d42f765519e356d8f0cc6ed339d9b74f0a3e4d7
Signed-off-by: Andrew Wu <arw(a)dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3610
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/3610 for details.
-gerrit
1
0
New patch to review for coreboot: 50f2e0d nehalem: Replace cache-as-ram init
by Kyösti Mälkki 05 Jul '13
by Kyösti Mälkki 05 Jul '13
05 Jul '13
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3612
-gerrit
commit 50f2e0d40a7ea6f787df84a7d329923052677c3f
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Jun 16 03:45:34 2013 +0300
nehalem: Replace cache-as-ram init
In comparison to model_206ax/cache_as_ram.inc following changes
can be identified. These changes were not argumented before merge
and contradict publicly available documentation for Nehalem.
Romstage stack pointer is initialized at an arbitrary address
in relation to CONFIG_DCACHE_RAM_BASE.
MSR 0x02ff is not part of MTRR tables, it is really MTRRdefType_MSR.
This MSR is programmed right after the MTRRs are cleared. Note that
it has high 32bits documented as reserved and should not be zeroed.
MSRs 0x0210, 0x211, 0x212 and 0x213 are documented for Nehalem too
as existing MTRRS.
Change-Id: Id195e30fea6bb0bc71b121183a7df1987a194e0f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/intel/model_2065x/Makefile.inc | 2 +-
src/cpu/intel/model_2065x/cache_as_ram.inc | 347 -----------------------------
2 files changed, 1 insertion(+), 348 deletions(-)
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 963fb1b..e82c02f 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -13,4 +13,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-cpu_incs += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
+cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
deleted file mode 100644
index db0eaae..0000000
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com>
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <cpu/x86/stack.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/post_code.h>
-#include <cbmem.h>
-
-#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-
-/* Cache 4GB - MRC_SIZE_KB for MRC */
-#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
-#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
-#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
-
-#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
-
-#define NoEvictMod_MSR 0x2e0
-
- /* Save the BIST result. */
- movl %eax, %ebp
-
-cache_as_ram:
- post_code(0x20)
-
- /* Send INIT IPI to all excluding ourself. */
- movl $0x000C4500, %eax
- movl $0xFEE00300, %esi
- movl %eax, (%esi)
-
- /* All CPUs need to be in Wait for SIPI state */
-wait_for_sipi:
- movl (%esi), %eax
- bt $12, %eax
- jc wait_for_sipi
-
- post_code(0x21)
- /* Zero out all fixed range and variable range MTRRs. */
- movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) / 2), %edi
- xorl %eax, %eax
- xorl %edx, %edx
-clear_mtrrs:
- movw (%esi), %bx
- movzx %bx, %ecx
- wrmsr
- add $2, %esi
- dec %edi
- jnz clear_mtrrs
-
- post_code(0x22)
- /* Configure the default memory type to uncacheable. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- andl $(~0x00000cff), %eax
- wrmsr
-
- post_code(0x23)
- /* Set Cache-as-RAM base address. */
- movl $(MTRRphysBase_MSR(0)), %ecx
- movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
- xorl %edx, %edx
- wrmsr
-
- post_code(0x24)
- /* Set Cache-as-RAM mask. */
- movl $(MTRRphysMask_MSR(0)), %ecx
- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-
- post_code(0x25)
-
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $MTRRdefTypeEn, %eax
- wrmsr
-
- /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
- movl %cr0, %eax
- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
- invd
- movl %eax, %cr0
-
- /* enable the 'no eviction' mode */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- orl $1, %eax
- andl $~2, %eax
- wrmsr
-
- /* Clear the cache memory region. This will also fill up the cache */
- movl $CACHE_AS_RAM_BASE, %esi
- movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
- // movl $0x23322332, %eax
- xorl %eax, %eax
- rep stosl
-
- /* enable the 'no eviction run' state */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- orl $3, %eax
- wrmsr
-
- post_code(0x26)
- /* Enable Cache-as-RAM mode by disabling cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- /* Enable cache for our code in Flash because we do XIP here */
- movl $MTRRphysBase_MSR(1), %ecx
- xorl %edx, %edx
- /*
- * IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
- */
- movl $copy_and_run, %eax
- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
- orl $MTRR_TYPE_WRPROT, %eax
- wrmsr
-
- movl $MTRRphysMask_MSR(1), %ecx
- movl $CPU_PHYSMASK_HI, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
- wrmsr
-
- post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
- /* Enable caching for ram init code to run faster */
- movl $MTRRphysBase_MSR(2), %ecx
- movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRRphysMask_MSR(2), %ecx
- movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-#endif
-
- post_code(0x28)
- /* Enable cache. */
- movl %cr0, %eax
- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
- movl %eax, %cr0
-
- /* Set up the stack pointer below MRC variable space. */
- movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
- CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4 - 4096), %eax
- movl %eax, %esp
-
- /* Restore the BIST result. */
- movl %ebp, %eax
- movl %esp, %ebp
- pushl %eax
-
-before_romstage:
- post_code(0x29)
- /* Call romstage.c main function. */
- call main
-
- post_code(0x2f)
-
- /* Copy global variable space (for USBDEBUG) to memory */
-#if CONFIG_USBDEBUG
- cld
- movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
- movl $(CONFIG_RAMTOP - 24), %edi
- movl $24, %ecx
- rep movsb
-#endif
-
- post_code(0x30)
-
- /* Disable cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- post_code(0x31)
-
- /* Disable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- andl $(~MTRRdefTypeEn), %eax
- wrmsr
-
- post_code(0x31)
-
- /* Disable the no eviction run state */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- andl $~2, %eax
- wrmsr
-
- invd
-
- /* Disable the no eviction mode */
- rdmsr
- andl $~1, %eax
- wrmsr
-
-#if CONFIG_CACHE_MRC_BIN
- /* Clear MTRR that was used to cache MRC */
- xorl %eax, %eax
- xorl %edx, %edx
- movl $MTRRphysBase_MSR(2), %ecx
- wrmsr
- movl $MTRRphysMask_MSR(2), %ecx
- wrmsr
-#endif
-
- post_code(0x33)
-
- /* Enable cache. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x36)
-
- /* Disable cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- post_code(0x38)
-
- /* Enable Write Back and Speculative Reads for the first MB
- * and coreboot_ram.
- */
- movl $MTRRphysBase_MSR(0), %ecx
- movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRRphysMask_MSR(0), %ecx
- movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
- movl $CPU_PHYSMASK_HI, %edx // 36bit address space
- wrmsr
-
-#if CONFIG_CACHE_ROM_SIZE
- /* Enable Caching and speculative Reads for the
- * complete ROM now that we actually have RAM.
- */
- movl $MTRRphysBase_MSR(1), %ecx
- movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
- movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-#endif
-
- post_code(0x39)
-
- /* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x3a)
-
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $MTRRdefTypeEn, %eax
- wrmsr
-
- post_code(0x3b)
-
- /* Invalidate the cache again. */
- invd
-
- post_code(0x3c)
-
-#if CONFIG_HAVE_ACPI_RESUME
- movl CBMEM_BOOT_MODE, %eax
- cmpl $0x2, %eax // Resume?
- jne __acpi_resume_backup_done
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high
- * tables memory completely, but that's a wonderful clean up task for
- * another day.
- */
- cld
- movl $CONFIG_RAMBASE, %esi
- movl CBMEM_RESUME_BACKUP, %edi
- movl $HIGH_MEMORY_SAVE / 4, %ecx
- rep movsl
-
-__acpi_resume_backup_done:
-#endif
-
- post_code(0x3d)
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
- cld /* Clear direction flag. */
-
- movl $ROMSTAGE_STACK, %esp
- movl %esp, %ebp
- call copy_and_run
-
-.Lhlt:
- post_code(POST_DEAD_CODE)
- hlt
- jmp .Lhlt
-
-mtrr_table:
- .word 0x02FF
-
- /* Fixed MTRRs */
- .word 0x250, 0x258, 0x259
- .word 0x268, 0x269, 0x26A
- .word 0x26B, 0x26C, 0x26D
- .word 0x26E, 0x26F
-
- /* Variable MTRRs */
- .word 0x200, 0x201, 0x202, 0x203
- .word 0x204, 0x205, 0x206, 0x207
- .word 0x208, 0x209, 0x20A, 0x20B
- .word 0x20C, 0x20D, 0x20E, 0x20F
-mtrr_table_end:
-
1
0
New patch to review for coreboot: eee1a9c [NOTFORMERGE] ASUS M5A88-V AGESA port
by Sebastian Parborg 05 Jul '13
by Sebastian Parborg 05 Jul '13
05 Jul '13
Sebastian Parborg (darkdefende(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3611
-gerrit
commit eee1a9c4915d6e3d9cfeea5908dc1321ef8d8a32
Author: Sebastian Parborg <darkdefende(a)gmail.com>
Date: Fri Jul 5 12:57:58 2013 +0200
[NOTFORMERGE] ASUS M5A88-V AGESA port
Port of the m5a88-v board to agesa for bulldozer support.
This should work with f10 and f15 CPUs. However it's only been tested on
f15 (bulldozer) so far.
Currently it boots in to linux with either seabios or grub2 as a payload
but the linux kernel fails to init the sata drives with:
"ata1: softreset failed (1st FIS failed)"
Because of this I would not like this to be merged. However I would
really like to have some help with this.
I've posted boot logs on the mailing list:
http://www.coreboot.org/pipermail/coreboot/2013-July/076114.html
Besides that the USB3 ports and some of USB2 ports are not working.
The onboard GPU is not working either because if I use the vgabios that
I extracted from the original bios it fails to boot any further after it
loads the rom image. However it seems like the original coreboot m5a88-v
port didn't manange to get the GPU working either.
Change-Id: Ie9c089165437107360f0f0005a4ceb7ef24d1570
Signed-off-by: Sebastian Parborg <darkdefende(a)gmail.com>
---
src/mainboard/asus/m5a88-v/BiosCallOuts.c | 520 +++++++++
src/mainboard/asus/m5a88-v/BiosCallOuts.h | 78 ++
src/mainboard/asus/m5a88-v/Kconfig | 17 +-
src/mainboard/asus/m5a88-v/Makefile.inc | 45 +-
src/mainboard/asus/m5a88-v/OptionsIds.h | 67 ++
src/mainboard/asus/m5a88-v/PlatformGnbPcie.c | 167 +++
.../asus/m5a88-v/PlatformGnbPcieComplex.h | 72 ++
src/mainboard/asus/m5a88-v/acpi/routing.asl | 384 ++-----
src/mainboard/asus/m5a88-v/acpi_tables.c | 297 +++--
src/mainboard/asus/m5a88-v/agesawrapper.c | 1194 ++++++++++++++++++++
src/mainboard/asus/m5a88-v/agesawrapper.h | 87 ++
src/mainboard/asus/m5a88-v/buildOpts.c | 446 ++++++++
src/mainboard/asus/m5a88-v/devicetree.cb | 17 +-
src/mainboard/asus/m5a88-v/dsdt.asl | 909 +++++++--------
src/mainboard/asus/m5a88-v/get_bus_conf.c | 78 +-
src/mainboard/asus/m5a88-v/mainboard.c | 5 +-
src/mainboard/asus/m5a88-v/mb_sysconf.h | 43 -
src/mainboard/asus/m5a88-v/mptable.c | 64 +-
src/mainboard/asus/m5a88-v/resourcemap.c | 278 -----
src/mainboard/asus/m5a88-v/romstage.c | 235 ++--
20 files changed, 3570 insertions(+), 1433 deletions(-)
diff --git a/src/mainboard/asus/m5a88-v/BiosCallOuts.c b/src/mainboard/asus/m5a88-v/BiosCallOuts.c
new file mode 100644
index 0000000..6e41456
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/BiosCallOuts.c
@@ -0,0 +1,520 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include "amdlib.h"
+#include "BiosCallOuts.h"
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+
+STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
+{
+ {
+ AGESA_ALLOCATE_BUFFER,
+ BiosAllocateBuffer
+ },
+
+ {
+ AGESA_DEALLOCATE_BUFFER,
+ BiosDeallocateBuffer
+ },
+
+ {
+ AGESA_DO_RESET,
+ BiosReset
+ },
+
+ {
+ AGESA_LOCATE_BUFFER,
+ BiosLocateBuffer
+ },
+
+ {
+ AGESA_READ_SPD,
+ BiosReadSpd
+ },
+
+ {
+ AGESA_READ_SPD_RECOVERY,
+ BiosDefaultRet
+ },
+
+ {
+ AGESA_RUNFUNC_ONAP,
+ BiosRunFuncOnAp
+ },
+
+ {
+ AGESA_GET_IDS_INIT_DATA,
+ BiosGetIdsInitData
+ },
+
+ {
+ AGESA_HOOKBEFORE_DQS_TRAINING,
+ BiosHookBeforeDQSTraining
+ },
+
+ {
+ AGESA_HOOKBEFORE_DRAM_INIT,
+ BiosHookBeforeDramInit
+ },
+ {
+ AGESA_HOOKBEFORE_EXIT_SELF_REF,
+ BiosHookBeforeExitSelfRefresh
+ },
+};
+
+extern AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ AGESA_STATUS CalloutStatus;
+
+ for (i = 0; i < REQUIRED_CALLOUTS; i++) {
+ if (BiosCallouts[i].CalloutName == Func) {
+ break;
+ }
+ }
+
+ if(i >= REQUIRED_CALLOUTS) {
+ return AGESA_UNSUPPORTED;
+ }
+
+ CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+
+ return CalloutStatus;
+}
+
+
+CONST IDS_NV_ITEM IdsData[] =
+{
+ /*{
+ AGESA_IDS_NV_MAIN_PLL_CON,
+ 0x1
+ },
+ {
+ AGESA_IDS_NV_MAIN_PLL_FID_EN,
+ 0x1
+ },
+ {
+ AGESA_IDS_NV_MAIN_PLL_FID,
+ 0x8
+ },
+
+ {
+ AGESA_IDS_NV_CUSTOM_NB_PSTATE,
+ },
+ {
+ AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
+ },
+ {
+ AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
+ },
+ {
+ AGESA_IDS_NV_FORCE_NB_PSTATE,
+ },
+ */
+ {
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
+
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ IDS_NV_ITEM *IdsPtr;
+
+ IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
+
+ if (Data == IDS_CALLOUT_INIT) {
+ for (i = 0; i < NUM_IDS_ENTRIES; i++) {
+ IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
+ IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AvailableHeapSize;
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 CurrNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 BestFitNodeOffset;
+ UINT32 BestFitPrevNodeOffset;
+ UINT32 NextFreeOffset;
+ BIOS_BUFFER_NODE *CurrNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *BestFitNodePtr;
+ BIOS_BUFFER_NODE *BestFitPrevNodePtr;
+ BIOS_BUFFER_NODE *NextFreePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+ AllocParams->BufferPointer = NULL;
+
+ AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+ /* First allocation */
+ CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+ CurrNodePtr->BufferSize = AllocParams->BufferLength;
+ CurrNodePtr->NextNodeOffset = 0;
+ AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+ /* Update the remaining free space */
+ FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ /* Update the offsets for Allocated and Freed nodes */
+ BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+ BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+ } else {
+ /* Find out whether BufferHandle has been allocated on the heap. */
+ /* If it has, return AGESA_BOUNDS_CHK */
+ CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+ while (CurrNodeOffset != 0) {
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+ return AGESA_BOUNDS_CHK;
+ }
+ CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+ /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+ to the end of the allocated nodes list.
+ */
+
+ }
+ /* Find the node that best fits the requested buffer size */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ PrevNodeOffset = FreedNodeOffset;
+ BestFitNodeOffset = 0;
+ BestFitPrevNodeOffset = 0;
+ while (FreedNodeOffset != 0) {
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+ if (BestFitNodeOffset == 0) {
+ /* First node that fits the requested buffer size */
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ } else {
+ /* Find out whether current node is a better fit than the previous nodes */
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ }
+ }
+ }
+ PrevNodeOffset = FreedNodeOffset;
+ FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+ } /* end of while loop */
+
+
+ if (BestFitNodeOffset == 0) {
+ /* If we could not find a node that fits the requested buffer */
+ /* size, return AGESA_BOUNDS_CHK */
+ return AGESA_BOUNDS_CHK;
+ } else {
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+ /* If BestFitNode is larger than the requested buffer, fragment the node further */
+ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+ NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+ NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+ NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+ NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+ } else {
+ /* Otherwise, next free node is NextNodeOffset of BestFitNode */
+ NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+ }
+
+ /* If BestFitNode is the first buffer in the list, then update
+ StartOfFreedNodes to reflect the new free node
+ */
+ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+ BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+ } else {
+ BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+ }
+
+ /* Add BestFitNode to the list of Allocated nodes */
+ CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+ BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+ BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+ BestFitNodePtr->NextNodeOffset = 0;
+
+ /* Remove BestFitNode from list of Freed nodes */
+ AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+ }
+ }
+
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 AllocNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 NextNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 EndNodeOffset;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_BUFFER_NODE *PrevNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *NextNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ /* Find target node to deallocate in list of allocated nodes.
+ Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+ */
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ PrevNodeOffset = AllocNodeOffset;
+
+ while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ return AGESA_BOUNDS_CHK;
+ }
+ PrevNodeOffset = AllocNodeOffset;
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+
+ /* Remove target node from list of allocated nodes */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+ /* Zero out the buffer, and clear the BufferHandle */
+ LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+ AllocNodePtr->BufferHandle = 0;
+ AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+ /* Add deallocated node in order to the list of freed nodes */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+ EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+ if (AllocNodeOffset < FreedNodeOffset) {
+ /* Add to the start of the freed list */
+ if (EndNodeOffset == FreedNodeOffset) {
+ /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+ AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+ /* Clear the BufferSize and NextNodeOffset of the previous first node */
+ FreedNodePtr->BufferSize = 0;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ } else {
+ /* Otherwise, add freed node to the start of the list
+ Update NextNodeOffset and BufferSize to include the
+ size of BIOS_BUFFER_NODE
+ */
+ AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+ }
+ /* Update StartOfFreedNodes to the new first node */
+ BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+ } else {
+ /* Traverse list of freed nodes to find where the deallocated node
+ should be place
+ */
+ NextNodeOffset = FreedNodeOffset;
+ NextNodePtr = FreedNodePtr;
+ while (AllocNodeOffset > NextNodeOffset) {
+ PrevNodeOffset = NextNodeOffset;
+ if (NextNodePtr->NextNodeOffset == 0) {
+ break;
+ }
+ NextNodeOffset = NextNodePtr->NextNodeOffset;
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ }
+
+ /* If deallocated node is adjacent to the next node,
+ concatenate both nodes
+ */
+ if (NextNodeOffset == EndNodeOffset) {
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+ NextNodePtr->BufferSize = 0;
+ NextNodePtr->NextNodeOffset = 0;
+ } else {
+ /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+ AllocNodePtr->NextNodeOffset = NextNodeOffset;
+ }
+ /* If deallocated node is adjacent to the previous node,
+ concatenate both nodes
+ */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+ if (AllocNodeOffset == EndNodeOffset) {
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+ PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
+ AllocNodePtr->BufferSize = 0;
+ AllocNodePtr->NextNodeOffset = 0;
+ } else {
+ PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AllocNodeOffset;
+ UINT8 *BiosHeapBaseAddr;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+ while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ AllocParams->BufferPointer = NULL;
+ AllocParams->BufferLength = 0;
+ return AGESA_BOUNDS_CHK;
+ } else {
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+ }
+
+ AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+ AllocParams->BufferLength = AllocNodePtr->BufferSize;
+
+ return AGESA_SUCCESS;
+
+}
+
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+
+ Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+ return Status;
+}
+
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ UINT8 Value;
+ UINTN ResetType;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ ResetType = Data;
+ StdHeader = ConfigPtr;
+
+ //
+ // Perform the RESET based upon the ResetType. In case of
+ // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+ // AmdResetManager. During the critical condition, where reset is required
+ // immediately, the reset will be invoked directly by writing 0x04 to port
+ // 0xCF9 (Reset Port).
+ //
+ switch (ResetType) {
+ case WARM_RESET_WHENEVER:
+ case COLD_RESET_WHENEVER:
+ break;
+
+ case WARM_RESET_IMMEDIATELY:
+ case COLD_RESET_IMMEDIATELY:
+ Value = 0x06;
+ LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+ break;
+
+ default:
+ break;
+ }
+
+ Status = 0;
+ return Status;
+}
+
+AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+#ifdef __PRE_RAM__
+ Status = agesa_ReadSPD (Func, Data, ConfigPtr);
+#else
+ Status = AGESA_UNSUPPORTED;
+#endif
+
+ return Status;
+}
+
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_UNSUPPORTED;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
diff --git a/src/mainboard/asus/m5a88-v/BiosCallOuts.h b/src/mainboard/asus/m5a88-v/BiosCallOuts.h
new file mode 100644
index 0000000..24a05fb
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/BiosCallOuts.h
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BIOS_CALLOUT_H_
+#define _BIOS_CALLOUT_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#define REQUIRED_CALLOUTS 12
+#define BIOS_HEAP_START_ADDRESS 0x00010000
+#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
+
+typedef struct _BIOS_HEAP_MANAGER {
+ //UINT32 AvailableSize;
+ UINT32 StartOfAllocatedNodes;
+ UINT32 StartOfFreedNodes;
+} BIOS_HEAP_MANAGER;
+
+typedef struct _BIOS_BUFFER_NODE {
+ UINT32 BufferHandle;
+ UINT32 BufferSize;
+ UINT32 NextNodeOffset;
+} BIOS_BUFFER_NODE;
+
+/*
+ * CALLOUTS
+ */
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* REQUIRED CALLOUTS
+ * AGESA ADVANCED CALLOUTS - CPU
+ */
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* AGESA ADVANCED CALLOUTS - MEMORY */
+AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr);
+
+/* BIOS DEFAULT RET */
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+#define SB_GPIO_REG02 2
+#define SB_GPIO_REG09 9
+#define SB_GPIO_REG10 10
+#define SB_GPIO_REG15 15
+#define SB_GPIO_REG17 17
+#define SB_GPIO_REG21 21
+#define SB_GPIO_REG25 25
+#define SB_GPIO_REG28 28
+#endif //_BIOS_CALLOUT_H_
+
diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig
index 942a81d..fece785 100644
--- a/src/mainboard/asus/m5a88-v/Kconfig
+++ b/src/mainboard/asus/m5a88-v/Kconfig
@@ -3,11 +3,10 @@ if BOARD_ASUS_M5A88_V
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select CPU_AMD_SOCKET_AM3
- select DIMM_DDR3
- select DIMM_REGISTERED
- select QRANK_DIMM_SUPPORT
- select NORTHBRIDGE_AMD_AMDFAM10
+ select CPU_AMD_AGESA_FAMILY15
+ select CPU_AMD_SOCKET_AM3R2
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15
select SOUTHBRIDGE_AMD_RS780
select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_ITE_IT8721F
@@ -17,8 +16,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
- select HAVE_MP_TABLE
- select HAVE_ACPI_TABLES
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select RAMINIT_SYSINFO
select ENABLE_APIC_EXT_ID
@@ -94,4 +93,8 @@ config VGA_BIOS_ID
string
default "1002,9715"
+config WARNINGS_ARE_ERRORS
+ bool
+ default n
+
endif #BOARD_ASUS_M5A88_V
diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc
index 924f9d6..2db3df0 100644
--- a/src/mainboard/asus/m5a88-v/Makefile.inc
+++ b/src/mainboard/asus/m5a88-v/Makefile.inc
@@ -1,15 +1,36 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
-#SB800 CIMx share AGESA V5 lib code
-ifneq ($(CONFIG_CPU_AMD_AGESA),y)
- AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
- romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
- ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
+CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx
+AGESA_ROOT ?= $(AGESA_PREFIX)/f15
+SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb800
- AGESA_INC := -I$(AGESA_ROOT)/ \
- -I$(AGESA_ROOT)/Include \
- -I$(AGESA_ROOT)/Proc/IDS/ \
- -I$(AGESA_ROOT)/Proc/CPU/ \
- -I$(AGESA_ROOT)/Proc/CPU/Family
+subdirs-y += ../../../../$(AGESA_ROOT)
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += BiosCallOuts.c
+romstage-y += PlatformGnbPcie.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += PlatformGnbPcie.c
- CFLAGS += $(AGESA_INC)
-endif
diff --git a/src/mainboard/asus/m5a88-v/OptionsIds.h b/src/mainboard/asus/m5a88-v/OptionsIds.h
new file mode 100644
index 0000000..0dcd9f7
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/OptionsIds.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
+//#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/asus/m5a88-v/PlatformGnbPcie.c b/src/mainboard/asus/m5a88-v/PlatformGnbPcie.c
new file mode 100644
index 0000000..55cdced
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/PlatformGnbPcie.c
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This is the stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ AGESA_STATUS Status;
+ VOID *BrazosPcieComplexListPtr;
+ VOID *BrazosPciePortPtr;
+ VOID *BrazosPcieDdiPtr;
+
+ ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+PCIe_PORT_DESCRIPTOR PortList [] = {
+ // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+ },
+ #if 1
+ // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
+ },
+ // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+ },
+ // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+ },
+ #endif
+ // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+ {
+ DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+ }
+};
+
+PCIe_DDI_DESCRIPTOR DdiList [] = {
+ // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+ {
+ 0, //Descriptor flags
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+ //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ {ConnectorTypeDP, Aux1, Hdp1}
+ },
+ // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+ {
+ DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+ //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ {ConnectorTypeDP, Aux2, Hdp2}
+ }
+};
+
+PCIe_COMPLEX_DESCRIPTOR Brazos = {
+ DESCRIPTOR_TERMINATE_LIST,
+ 0,
+ &PortList[0],
+ &DdiList[0]
+};
+
+ // GNB PCIe topology Porting
+
+ //
+ // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+ //
+ AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
+ sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
+ sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
+
+ AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+ AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+ Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+ if ( Status!= AGESA_SUCCESS) {
+ // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+ ASSERT(FALSE);
+ }
+
+ BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
+ BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+
+ AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
+ BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ LibAmdMemFill (BrazosPcieComplexListPtr,
+ 0,
+ sizeof (PCIe_COMPLEX_DESCRIPTOR),
+ &InitEarly->StdHeader);
+
+ LibAmdMemFill (BrazosPciePortPtr,
+ 0,
+ sizeof (PCIe_PORT_DESCRIPTOR) * 5,
+ &InitEarly->StdHeader);
+
+ LibAmdMemFill (BrazosPcieDdiPtr,
+ 0,
+ sizeof (PCIe_DDI_DESCRIPTOR) * 2,
+ &InitEarly->StdHeader);
+
+ LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
+ LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader);
+ LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);
+
+
+ ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
+ ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+
+ InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+ InitEarly->GnbConfig.PsppPolicy = 0;
+}
+
diff --git a/src/mainboard/asus/m5a88-v/PlatformGnbPcieComplex.h b/src/mainboard/asus/m5a88-v/PlatformGnbPcieComplex.h
new file mode 100644
index 0000000..b51089f
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/PlatformGnbPcieComplex.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
+#define _PLATFORM_GNB_PCIE_COMPLEX_H
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+//GNB GPP Port4
+#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port5
+#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port6
+#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port7
+#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port8
+#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ );
+
+#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/asus/m5a88-v/acpi/routing.asl b/src/mainboard/asus/m5a88-v/acpi/routing.asl
index 87a79f9..1303d27 100644
--- a/src/mainboard/asus/m5a88-v/acpi/routing.asl
+++ b/src/mainboard/asus/m5a88-v/acpi/routing.asl
@@ -29,205 +29,137 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
Scope(\_SB) {
Name(PR0, Package(){
/* NB devices */
- /* Bus 0, Dev 0 - RS780 Host Controller */
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
+ /* Bus 0, Dev 0 - SR5650 HT */
+ Package() { 0xFFFF, Zero, INTA, Zero },
+
+ /* Bus 0, Dev 1 - CLKCONFIG */
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package() {0x0002FFFF, 0, INTE, 0 },
+
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, INTA, 0 },
- Package(){0x0004FFFF, 1, INTB, 0 },
- Package(){0x0004FFFF, 2, INTC, 0 },
- Package(){0x0004FFFF, 3, INTD, 0 },
+ Package() {0x0004FFFF, 0, INTE, 0 },
+
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- /* Package(){0x0005FFFF, 0, INTB, 0 }, */
- /* Package(){0x0005FFFF, 1, INTC, 0 }, */
- /* Package(){0x0005FFFF, 2, INTD, 0 }, */
- /* Package(){0x0005FFFF, 3, INTA, 0 }, */
+
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
- Package(){0x0006FFFF, 0, INTC, 0 },
- Package(){0x0006FFFF, 1, INTD, 0 },
- Package(){0x0006FFFF, 2, INTA, 0 },
- Package(){0x0006FFFF, 3, INTB, 0 },
+
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
- Package(){0x0007FFFF, 0, INTD, 0 },
- Package(){0x0007FFFF, 1, INTA, 0 },
- Package(){0x0007FFFF, 2, INTB, 0 },
- Package(){0x0007FFFF, 3, INTC, 0 },
- Package(){0x0009FFFF, 0, INTB, 0 },
- Package(){0x0009FFFF, 1, INTC, 0 },
- Package(){0x0009FFFF, 2, INTD, 0 },
- Package(){0x0009FFFF, 3, INTA, 0 },
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
- Package(){0x000AFFFF, 0, INTC, 0 },
- Package(){0x000AFFFF, 1, INTD, 0 },
- Package(){0x000AFFFF, 2, INTA, 0 },
- Package(){0x000AFFFF, 3, INTB, 0 },
+ /* Bus 0, Dev 9 - PCIe Bridge */
- Package(){0x000BFFFF, 0, INTD, 0 },
- Package(){0x000BFFFF, 1, INTA, 0 },
- Package(){0x000BFFFF, 2, INTB, 0 },
- Package(){0x000BFFFF, 3, INTC, 0 },
+ /* Bus 0, Dev a - PCIe Bridge */
- Package(){0x000CFFFF, 0, INTA, 0 },
- Package(){0x000CFFFF, 1, INTB, 0 },
- Package(){0x000CFFFF, 2, INTC, 0 },
- Package(){0x000CFFFF, 3, INTD, 0 },
+ /* Bus 0, Dev b - PCIe Bridge */
+ Package() {0x000BFFFF, 0, INTG, 0 },
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+ /* Bus 0, Dev c - PCIe Bridge */
+ Package() {0x000CFFFF, 0, INTG, 0 },
+
+ /* Bus 0, Dev d - PCIe Bridge for Intel 82576 Giga NIC*/
+ Package() {0x000DFFFF, 0, INTG, 0 },
/* SB devices */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0011FFFF, 0, INTD, 0 },
+ /* Bus 0, Dev 17 - SATA controller */
+ Package() {0x0011FFFF, 0, INTG, 0 },
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
* EHCI, dev 18, 19 func 2 */
- Package(){0x0012FFFF, 0, INTC, 0 },
- Package(){0x0012FFFF, 1, INTB, 0 },
-
- Package(){0x0013FFFF, 0, INTC, 0 },
- Package(){0x0013FFFF, 1, INTB, 0 },
+ Package() {0x0012FFFF, 0, INTA, 0 },
+ Package() {0x0012FFFF, 1, INTB, 0 },
+ Package() {0x0012FFFF, 2, INTC, 0 },
+ Package() {0x0012FFFF, 3, INTD, 0 },
- Package(){0x0016FFFF, 0, INTC, 0 },
- Package(){0x0016FFFF, 1, INTB, 0 },
-
- /* Package(){0x0014FFFF, 1, INTA, 0 }, */
+ Package() {0x0013FFFF, 0, INTC, 0 },
+ Package() {0x0013FFFF, 1, INTD, 0 },
+ Package() {0x0013FFFF, 2, INTA, 0 },
+ Package() {0x0013FFFF, 2, INTB, 0 },
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTC, 0 },
Package(){0x0014FFFF, 3, INTD, 0 },
-
- Package(){0x0015FFFF, 0, INTA, 0 },
- Package(){0x0015FFFF, 1, INTB, 0 },
- Package(){0x0015FFFF, 2, INTC, 0 },
- Package(){0x0015FFFF, 3, INTD, 0 },
})
Name(APR0, Package(){
/* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS780 Host Controller */
+ /* Bus 0, Dev 0 - SR5650 HT */
+ Package() { 0xFFFF, Zero, Zero, 55 },
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
Package(){0x0001FFFF, 1, 0, 19 },
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, 0, 18 },
- /* Package(){0x0002FFFF, 1, 0, 19 }, */
- /* Package(){0x0002FFFF, 2, 0, 16 }, */
- /* Package(){0x0002FFFF, 3, 0, 17 }, */
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */
+ Package() {0x0002FFFF, 0, 0, 0x34 },
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, 0, 19 },
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, 0, 16 },
- /* Package(){0x0004FFFF, 1, 0, 17 }, */
- /* Package(){0x0004FFFF, 2, 0, 18 }, */
- /* Package(){0x0004FFFF, 3, 0, 19 }, */
+ Package() {0x0004FFFF, 0, 0, 0x34 },
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- /* Package(){0x0005FFFF, 0, 0, 17 }, */
- /* Package(){0x0005FFFF, 1, 0, 18 }, */
- /* Package(){0x0005FFFF, 2, 0, 19 }, */
- /* Package(){0x0005FFFF, 3, 0, 16 }, */
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- /* Package(){0x0006FFFF, 0, 0, 18 }, */
- /* Package(){0x0006FFFF, 1, 0, 19 }, */
- /* Package(){0x0006FFFF, 2, 0, 16 }, */
- /* Package(){0x0006FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 7 - PCIe Bridge for network card */
- /* Package(){0x0007FFFF, 0, 0, 19 }, */
- /* Package(){0x0007FFFF, 1, 0, 16 }, */
- /* Package(){0x0007FFFF, 2, 0, 17 }, */
- /* Package(){0x0007FFFF, 3, 0, 18 }, */
-
- /* Bus 0, Dev 9 - PCIe Bridge for network card */
- Package(){0x0009FFFF, 0, 0, 17 },
- /* Package(){0x0009FFFF, 1, 0, 16 }, */
- /* Package(){0x0009FFFF, 2, 0, 17 }, */
- /* Package(){0x0009FFFF, 3, 0, 18 }, */
- /* Bus 0, Dev A - PCIe Bridge for network card */
- Package(){0x000AFFFF, 0, 0, 18 },
- /* Package(){0x000AFFFF, 1, 0, 16 }, */
- /* Package(){0x000AFFFF, 2, 0, 17 }, */
- /* Package(){0x000AFFFF, 3, 0, 18 }, */
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 7 - PCIe Bridge */
+
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 9 - PCIe Bridge */
+
+ /* Bus 0, Dev A - PCIe Bridge */
+
+ /* Bus 0, Dev B - PCIe Bridge */
+ Package() {0x000BFFFF, 0, 0, 0x36 },
+
+ /* Bus 0, Dev C - PCIe Bridge */
+ Package() {0x000CFFFF, 0, 0, 0x36 },
+
+ /* Bus 0, Dev D - PCIe Bridge For Intel 82576 Giga NIC*/
+ Package() {0x000DFFFF, 0, 0, 0x36 },
/* SB devices in APIC mode */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0011FFFF, 0, 0, 19 },
+ /* Bus 0, Dev 17 - SATA controller */
+ Package() {0x0011FFFF, 0, 0, 0x16 },
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
* EHCI, dev 18, 19 func 2 */
- Package(){0x0012FFFF, 0, 0, 18 },
- Package(){0x0012FFFF, 1, 0, 17 },
- /* Package(){0x0012FFFF, 2, 0, 18 }, */
-
- Package(){0x0013FFFF, 0, 0, 18 },
- Package(){0x0013FFFF, 1, 0, 17 },
- /* Package(){0x0013FFFF, 2, 0, 16 }, */
+ Package( ){0x0012FFFF, 0, 0, 16 },
+ Package() {0x0012FFFF, 1, 0, 17 },
+ Package() {0x0012FFFF, 2, 0, 18 },
+ Package() {0x0012FFFF, 3, 0, 19 },
- /* Package(){0x00140000, 0, 0, 16 }, */
-
- Package(){0x0016FFFF, 0, 0, 18 },
- Package(){0x0016FFFF, 1, 0, 17 },
+ Package() {0x0013FFFF, 0, 0, 18 },
+ Package() {0x0013FFFF, 1, 0, 19 },
+ Package() {0x0013FFFF, 2, 0, 16 },
+ Package() {0x0013FFFF, 3, 0, 17 },
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- /* Package(){0x00140004, 2, 0, 18 }, */
- /* Package(){0x00140004, 3, 0, 19 }, */
- /* Package(){0x00140005, 1, 0, 17 }, */
- /* Package(){0x00140006, 1, 0, 17 }, */
-
- /* TODO: pcie */
- Package(){0x0015FFFF, 0, 0, 16 },
- Package(){0x0015FFFF, 1, 0, 17 },
- Package(){0x0015FFFF, 2, 0, 18 },
- Package(){0x0015FFFF, 3, 0, 19 },
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS780 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, INTA, 0 },
- Package(){0x0005FFFF, 1, INTB, 0 },
- Package(){0x0005FFFF, 2, INTC, 0 },
- Package(){0x0005FFFF, 3, INTD, 0 },
- })
- Name(APR1, Package(){
- /* Internal graphics - RS780 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- /* Package(){0x0005FFFF, 2, 0, 20 }, */
- /* Package(){0x0005FFFF, 3, 0, 17 }, */
+ Package() {0x0014FFFF, 0, 0, 16 },
+ Package() {0x0014FFFF, 1, 0, 17 },
+ Package() {0x0014FFFF, 2, 0, 18 },
+ Package() {0x0014FFFF, 3, 0, 19 },
})
Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
+ /* The external GFX - Hooked to PCIe slot 4 */
+ Package() {0x0000FFFF, 0, INTC, 0 },
+ Package() {0x0000FFFF, 1, INTD, 0 },
+ Package() {0x0000FFFF, 2, INTA, 0 },
+ Package() {0x0000FFFF, 3, INTB, 0 },
})
Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
+ /* The external GFX - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 0x18 },
+ Package(){0x0000FFFF, 1, 0, 0x19 },
+ Package(){0x0000FFFF, 2, 0, 0x1A },
+ Package(){0x0000FFFF, 3, 0, 0x1B },
})
Name(PS4, Package(){
@@ -239,160 +171,54 @@ Scope(\_SB) {
})
Name(APS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
+ Package(){0x0000FFFF, 0, 0, 0x2C },
+ Package(){0x0000FFFF, 1, 0, 0x2D },
+ Package(){0x0000FFFF, 2, 0, 0x2E },
+ Package(){0x0000FFFF, 3, 0, 0x2F },
})
- Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
- Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
- Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
- Name(APS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-
- Name(PS9, Package(){
- /* PCIe slot - Hooked to PCIe slot 9 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
- Name(APS9, Package(){
- /* PCIe slot - Hooked to PCIe slot 9 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PSa, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
+ Name(PSb, Package(){
+ /* PCIe slot - Hooked to PCIe slot 11 */
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
- Name(APSa, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
+ Name(APSb, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 0x20 },
+ Package(){0x0000FFFF, 1, 0, 0x21 },
+ Package(){0x0000FFFF, 2, 0, 0x22 },
+ Package(){0x0000FFFF, 3, 0, 0x23 },
})
- Name(PE0, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
+ Name(PSc, Package(){
+ /* PCIe slot - Hooked to PCIe slot 12 */
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
- Name(APE0, Package(){
+ Name(APSc, Package(){
/* PCIe slot - Hooked to PCIe */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
+ Package(){0x0000FFFF, 0, 0, 0x24 },
+ Package(){0x0000FFFF, 1, 0, 0x25 },
+ Package(){0x0000FFFF, 2, 0, 0x26 },
+ Package(){0x0000FFFF, 3, 0, 0x27 },
})
- Name(PE1, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
+ Name(PSd, Package(){
+ /* PCIe slot - Hooked to PCIe slot 13 */
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
- Name(APE1, Package(){
- /* PCIe slot - Hooked to PCIe */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PE2, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
- Name(APE2, Package(){
+ Name(APSd, Package(){
/* PCIe slot - Hooked to PCIe */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PE3, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
- Name(APE3, Package(){
- /* PCIe slot - Hooked to PCIe */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
- Package(){0x0007FFFF, 0, 0, 0x16 },
- Package(){0x0007FFFF, 1, 0, 0x17 },
- Package(){0x0007FFFF, 2, 0, 0x14 },
- Package(){0x0007FFFF, 3, 0, 0x15 },
+ Package(){0x0000FFFF, 0, 0, 0x28 },
+ Package(){0x0000FFFF, 1, 0, 0x29 },
+ Package(){0x0000FFFF, 2, 0, 0x2A },
+ Package(){0x0000FFFF, 3, 0, 0x2B },
})
}
diff --git a/src/mainboard/asus/m5a88-v/acpi_tables.c b/src/mainboard/asus/m5a88-v/acpi_tables.c
index 2591d84..9ad8806 100644
--- a/src/mainboard/asus/m5a88-v/acpi_tables.c
+++ b/src/mainboard/asus/m5a88-v/acpi_tables.c
@@ -20,14 +20,17 @@
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/acpigen.h>
#include <arch/ioapic.h>
+#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
+#include "agesawrapper.h"
+
#define DUMP_ACPI_TABLES 0
@@ -48,14 +51,29 @@ static void dump_mem(u32 start, u32 end)
#endif
extern const unsigned char AmlCode[];
-extern const unsigned char AmlCode_ssdt[];
-#if CONFIG_ACPI_SSDTX_NUM >= 1
-extern const unsigned char AmlCode_ssdt2[];
-extern const unsigned char AmlCode_ssdt3[];
-extern const unsigned char AmlCode_ssdt4[];
-extern const unsigned char AmlCode_ssdt5[];
-#endif
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+ int lens;
+ msr_t msr;
+ char pscope[] = "\\_SB.PCI0";
+
+ lens = acpigen_write_scope(pscope);
+ msr = rdmsr(TOP_MEM);
+ lens += acpigen_write_name_dword("TOM1", msr.lo);
+ msr = rdmsr(TOP_MEM2);
+ /*
+ * Since XP only implements parts of ACPI 2.0, we can't use a qword
+ * here.
+ * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+ * slide 22ff.
+ * Shift value right by 20 bit to make it fit into 32bit,
+ * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+ */
+ lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+ acpigen_patch_len(lens - 1);
+ return (unsigned long) (acpigen_get_current());
+}
unsigned long acpi_fill_mcfg(unsigned long current)
{
@@ -65,29 +83,91 @@ unsigned long acpi_fill_mcfg(unsigned long current)
unsigned long acpi_fill_madt(unsigned long current)
{
- /* create all subtables for processors */
+ device_t dev;
+ u32 dword;
+ u32 gsi_base = 0;
+ u32 apicid_rs780;
+ u32 apicid_sb800;
+ /*
+ * AGESA v5 Apply apic enumeration rules
+ * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+ * put the local-APICs at m..z
+ * For systems with < 16 APICs, put the Local-APICs at 0..n and
+ * put the IO-APICs at (n + 1)..z
+ */
+#if CONFIG_MAX_CPUS >= 16
+ apicid_sb800 = 0x0;
+#else
+ apicid_sb800 = CONFIG_MAX_CPUS + 1;
+#endif
+
+ apicid_rs780 = apicid_sb800 + 1;
+
+ /* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write SB800 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
- IO_APIC_ADDR, 0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_sb800, IO_APIC_ADDR, 0);
+
+ /* IOAPIC on rs780 */
+ gsi_base += IO_APIC_INTERRUPTS; /* SB800 has 24 IOAPIC entries. */
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (dev) {
+ pci_write_config32(dev, 0xF8, 0x1);
+ dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_rs780,
+ dword,
+ gsi_base
+ );
+ }
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high */
/* create all subtables for processors */
- /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
/* 1: LINT1 connect to NMI */
return current;
}
+unsigned long acpi_fill_hest(acpi_hest_t *hest)
+{
+ void *addr, *current;
+
+ /* Skip the HEST header. */
+ current = (void *)(hest + 1);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ return (unsigned long)current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
@@ -101,13 +181,11 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
-#if CONFIG_ACPI_SSDTX_NUM >= 1
- acpi_header_t *ssdtx;
- void *p;
- int i;
-#endif
+ acpi_header_t *ssdt2;
+ acpi_header_t *alib;
+ acpi_hest_t *hest;
- get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */
start = ALIGN(start, 16);
@@ -127,11 +205,36 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt);
+ /* DSDT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
+ dsdt = (acpi_header_t *)current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+ /* FACS */ // it needs 64 bit alignment
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* FADT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
/*
* We explicitly add these tables later on:
*/
current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
+ printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
@@ -139,110 +242,80 @@ unsigned long write_acpi_tables(unsigned long start)
/* If we want to use HPET Timers Linux wants an MADT */
current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
+ printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdp, madt);
+ /* HEST */
+ current = ALIGN(current, 8);
+ hest = (acpi_hest_t *)current;
+ acpi_write_hest((void *)current);
+ acpi_add_table(rsdp, (void *)current);
+ current += ((acpi_header_t *)current)->length;
+
/* SRAT */
current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
- srat = (acpi_srat_t *) current;
- acpi_create_srat(srat);
- current += srat->header.length;
- acpi_add_table(rsdp, srat);
+ printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
+ srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+ if (srat != NULL) {
+ memcpy((void *)current, srat, srat->header.length);
+ srat = (acpi_srat_t *) current;
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
+ }
/* SLIT */
current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
- slit = (acpi_slit_t *) current;
- acpi_create_slit(slit);
- current += slit->header.length;
- acpi_add_table(rsdp, slit);
+ printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
+ slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+ if (slit != NULL) {
+ memcpy((void *)current, slit, slit->header.length);
+ slit = (acpi_slit_t *) current;
+ current += slit->header.length;
+ acpi_add_table(rsdp, slit);
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
+ }
/* SSDT */
current = ALIGN(current, 16);
- printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
- ssdt = (acpi_header_t *)current;
- memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
- current += ssdt->length;
- memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
- //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
- update_ssdt((void*)ssdt);
- /* recalculate checksum */
- ssdt->checksum = 0;
- ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
- acpi_add_table(rsdp,ssdt);
-
- printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
- current = acpi_add_ssdt_pstates(rsdp, current);
-
-#if CONFIG_ACPI_SSDTX_NUM >= 1
-
- /* same htio, but different position? We may have to copy,
- change HCIN, and recalculate the checknum and add_table */
-
- for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
- if((sysconf.pci1234[i] & 1) != 1 ) continue;
- u8 c;
- if (i < 7) {
- c = (u8) ('4' + i - 1);
- } else {
- c = (u8) ('A' + i - 1 - 6);
- }
- current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
- ssdtx = (acpi_header_t *)current;
- switch (sysconf.hcid[i]) {
- case 1:
- p = &AmlCode_ssdt2;
- break;
- case 2:
- p = &AmlCode_ssdt3;
- break;
- case 3: /* 8131 */
- p = &AmlCode_ssdt4;
- break;
- default:
- /* HTX no io apic */
- p = &AmlCode_ssdt5;
- break;
- }
- memcpy(ssdtx, p, sizeof(acpi_header_t));
- current += ssdtx->length;
- memcpy(ssdtx, p, ssdtx->length);
- update_ssdtx((void *)ssdtx, i);
- ssdtx->checksum = 0;
- ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
- acpi_add_table(rsdp, ssdtx);
+ printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
+ alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+ if (alib != NULL) {
+ memcpy((void *)current, alib, alib->length);
+ alib = (acpi_header_t *) current;
+ current += alib->length;
+ acpi_add_table(rsdp, (void *)alib);
+ } else {
+ printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
}
-#endif
- /* DSDT */
- current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
- dsdt = (acpi_header_t *)current; // it will used by fadt
- memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
- current += dsdt->length;
- memcpy(dsdt, &AmlCode, dsdt->length);
- printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-
- /* FACS */ // it needs 64 bit alignment
- current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
- facs = (acpi_facs_t *) current; // it will be used by fadt
- current += sizeof(acpi_facs_t);
- acpi_create_facs(facs);
-
- /* FADT */
- current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
- fadt = (acpi_fadt_t *) current;
- current += sizeof(acpi_fadt_t);
+ /* The DSDT needs additional work for the AGESA SSDT Pstate table */
+ /* Keep the comment for a while. */
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current);
+ ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+ if (ssdt != NULL) {
+ memcpy((void *)current, ssdt, ssdt->length);
+ ssdt = (acpi_header_t *) current;
+ current += ssdt->length;
+ acpi_add_table(rsdp,ssdt);
+ } else {
+ printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n");
+ }
- acpi_create_fadt(fadt, facs, dsdt);
- acpi_add_table(rsdp, fadt);
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current);
+ ssdt2 = (acpi_header_t *) current;
+ acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
+ current += ssdt2->length;
+ acpi_add_table(rsdp,ssdt2);
#if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n");
@@ -263,8 +336,14 @@ unsigned long write_acpi_tables(unsigned long start)
printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+ printk(BIOS_DEBUG, "ssdt2\n");
+ dump_mem(ssdt2, ((void *)ssdt2) + ssdt2->length);
+
printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+
+ printk(BIOS_DEBUG, "hest\n");
+ dump_mem(hest, ((void *)hest) + hest->header.length);
#endif
printk(BIOS_INFO, "ACPI: done.\n");
diff --git a/src/mainboard/asus/m5a88-v/agesawrapper.c b/src/mainboard/asus/m5a88-v/agesawrapper.c
new file mode 100644
index 0000000..ee291c0
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/agesawrapper.c
@@ -0,0 +1,1194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "agesawrapper.h"
+#include "BiosCallOuts.h"
+#include "cpuRegisters.h"
+#include "cpuCacheInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "Dispatcher.h"
+#include "cpuCacheInit.h"
+#include "amdlib.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable = NULL;
+VOID *AcpiPstate = NULL;
+VOID *AcpiSrat = NULL;
+VOID *AcpiSlit = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+VOID *AcpiAlib = NULL;
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+static UINT32 agesawrapper_amdinitcpuio(VOID)
+{
+ AGESA_STATUS Status;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+ UINT32 nodes;
+ UINT32 node;
+ UINT32 sblink;
+ UINT32 i;
+ UINT32 TOM;
+
+ /* get the number of coherent nodes in the system */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0]
+
+ /* Find out the Link ID of Node0 that connects to the
+ * Southbridge (system IO hub). e.g. family10 MCM Processor,
+ * sbLink is Processor0 Link2, internal Node0 Link3
+ */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ sblink = (PciData >> 8) & 3; //assume ganged
+
+ /* Enable MMIO on AMD CPU Address Map Controller for all nodes */
+ for (node = 0; node < nodes; node++) {
+ /* clear all MMIO Mapped Base/Limit Registers */
+ for (i = 0; i < 8; i++) {
+ PciData = 0x00000000;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ }
+
+ /* clear all IO Space Base/Limit Registers */
+ for (i = 0; i < 4; i++) {
+ PciData = 0x00000000;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ }
+
+ /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
+ PciData = 0x00000B00;
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
+ PciData = 0x00000A03;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set TOM1-FFFFFFFF to Node0 sbLink. */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
+ PciData = 0x00FFFF00;
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ TOM = (UINT32)MsrRead(TOP_MEM);
+ PciData = (TOM >> 8) | 0x03;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set MMCONF space to Node0 sbLink with NP set.
+ * default E0000000-EFFFFFFF
+ * Just have all mmio set to non-posted,
+ * coreboot not implemente the range by range setting yet.
+ */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
+ PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus
+ PciData = (PciData >> 8) & 0xFFFFFF00;
+ PciData |= 0x80; //NP
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8);
+ PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+
+ /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
+ PciData = 0x00FFF000;
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
+ PciData = 0x00000033;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ }
+
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32 agesawrapper_amdinitmmio(VOID)
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /*
+ * Set the MMIO Configuration Base Address and Bus Range onto
+ * MMIO configuration base Address MSR register.
+ */
+ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+ LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
+
+ /*
+ * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+ */
+ LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
+ MsrReg = MsrReg | (1ULL << 46);
+ LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
+ LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
+
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32 agesawrapper_amdinitreset(VOID)
+{
+ AGESA_STATUS status = AGESA_SUCCESS;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESET_PARAMS AmdResetParams;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ LibAmdMemFill(&AmdResetParams,
+ 0,
+ sizeof(AMD_RESET_PARAMS),
+ &(AmdResetParams.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+ AmdParamStruct.AllocationMethod = ByHost;
+ AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+ AmdParamStruct.NewStructPtr = &AmdResetParams;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = NULL;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ status = AmdCreateStruct(&AmdParamStruct);
+ if (status != AGESA_SUCCESS) {
+ return (UINT32)status;
+ }
+ AmdResetParams.HtConfig.Depth = 0;
+
+ //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default
+ //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work
+#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
+ status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+#endif
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct(&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitearly(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
+ UINT32 TscRateInMhz;
+ CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ status = AmdCreateStruct(&AmdParamStruct);
+ if (status != AGESA_SUCCESS) {
+ return (UINT32)status;
+ }
+
+ AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+ OemCustomizeInitEarly(AmdEarlyParamsPtr);
+
+ status = AmdInitEarly(AmdEarlyParamsPtr);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+
+ GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader);
+ FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
+ printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
+
+ AmdReleaseStruct(&AmdParamStruct);
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitpost(VOID)
+{
+ AGESA_STATUS status;
+ UINT16 i;
+ UINT32 *HeadPtr;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_POST_PARAMS *PostParams;
+ BIOS_HEAP_MANAGER *BiosManagerPtr;
+ UINT32 TscRateInMhz;
+ CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ status = AmdCreateStruct(&AmdParamStruct);
+ if (status != AGESA_SUCCESS) {
+ return (UINT32)status;
+ }
+ PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
+ status = AmdInitPost(PostParams);
+ if (status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
+ }
+ AmdReleaseStruct(&AmdParamStruct);
+
+ /* Initialize heap space */
+ BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+ HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof(BIOS_HEAP_MANAGER));
+ for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof(BIOS_HEAP_MANAGER)/4)); i++) {
+ *HeadPtr = 0x00000000;
+ HeadPtr++;
+ }
+ BiosManagerPtr->StartOfAllocatedNodes = 0;
+ BiosManagerPtr->StartOfFreedNodes = 0;
+
+ GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader);
+ FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
+ printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
+
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitenv(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_ENV_PARAMS *EnvParams;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ status = AmdCreateStruct(&AmdParamStruct);
+ if (status != AGESA_SUCCESS) {
+ return (UINT32)status;
+ }
+ EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
+ status = AmdInitEnv(EnvParams);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus);
+
+ AmdReleaseStruct(&AmdParamStruct);
+ return (UINT32)status;
+}
+
+VOID * agesawrapper_getlateinitptr(int pick)
+{
+ switch (pick) {
+ case PICK_DMI:
+ return DmiTable;
+
+ case PICK_PSTATE:
+ return AcpiPstate;
+
+ case PICK_SRAT:
+ return AcpiSrat;
+
+ case PICK_SLIT:
+ return AcpiSlit;
+ case PICK_WHEA_MCE:
+ return AcpiWheaMce;
+ case PICK_WHEA_CMC:
+ return AcpiWheaCmc;
+ case PICK_ALIB:
+ return AcpiAlib;
+ default:
+ return NULL;
+ }
+
+ return NULL;
+}
+
+UINT32 agesawrapper_amdinitmid(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ /* Enable MMIO on AMD CPU Address Map Controller */
+ agesawrapper_amdinitcpuio();
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ status = AmdCreateStruct(&AmdParamStruct);
+ if (status != AGESA_SUCCESS) {
+ return (UINT32)status;
+ }
+ status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct(&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitlate(VOID)
+{
+ AGESA_STATUS Status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_LATE_PARAMS *AmdLateParamsPtr;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+ AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
+
+ printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
+
+ Status = AmdInitLate(AmdLateParamsPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+ DmiTable = AmdLateParamsPtr->DmiTable;
+ AcpiPstate = AmdLateParamsPtr->AcpiPState;
+ AcpiSrat = AmdLateParamsPtr->AcpiSrat;
+ AcpiSlit = AmdLateParamsPtr->AcpiSlit;
+ AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
+ AcpiAlib = AmdLateParamsPtr->AcpiAlib;
+
+ printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
+ " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
+ " Mce:%p\n Cmc:%p\n Alib:%p\n",
+ __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
+ AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
+
+ /* Don't release the structure until coreboot has copied the ACPI tables.
+ * AmdReleaseStruct (&AmdLateParams);
+ */
+
+ return (UINT32)Status;
+}
+
+/**
+ * @param[in] UINTN ApicIdOfCore,
+ * @param[in] AP_EXE_PARAMS *LaunchApParams
+ */
+UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ AMD_LATE_PARAMS AmdLateParams;
+
+ LibAmdMemFill(&AmdLateParams,
+ 0,
+ sizeof(AMD_LATE_PARAMS),
+ &(AmdLateParams.StdHeader));
+
+ AmdLateParams.StdHeader.AltImageBasePtr = 0;
+ AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdLateParams.StdHeader.Func = 0;
+ AmdLateParams.StdHeader.ImageBasePtr = 0;
+ AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM;
+
+ printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data);
+ Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus);
+ ASSERT(Status <= AGESA_UNSUPPORTED);
+ }
+
+ return (UINT32)Status;
+}
+
+/**
+ *
+ */
+static void agesa_bound_check(EVENT_PARAMS *event)
+{
+ switch (event->EventInfo) {
+ case CPU_ERROR_HEAP_IS_FULL:
+ printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n");
+ break;
+
+ case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED:
+ printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n");
+ break;
+
+ case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT:
+ printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n");
+ break;
+
+ case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT:
+ printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n");
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_alert(EVENT_PARAMS *event)
+{
+ switch (event->EventInfo) {
+ case MEM_ALERT_USER_TMG_MODE_OVERRULED:
+ printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
+ "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case MEM_ALERT_ORG_MISMATCH_DIMM:
+ printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
+ "DIMM organization miss-match\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case MEM_ALERT_BK_INT_DIS:
+ printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
+ "Bank interleaving disable for internal issue\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case CPU_EVENT_BIST_ERROR:
+ printk(BIOS_DEBUG, "BIST error: %lx reported on Socket %lx Core %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_HW_SYNCFLOOD:
+ printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %lx Link %lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case HT_EVENT_HW_HTCRC:
+ printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %lx Link %lx Lanemask:%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_warning(EVENT_PARAMS *event)
+{
+/*
+ if (event->EventInfo == CPU_EVENT_STACK_REENTRY) {
+ printk(BIOS_DEBUG,
+ "The stack has already been enabled and this is a
+ redundant invocation of AMD_ENABLE_STACK. There is no event logged and
+ no data values. The event sub-class is returned along with the status code\n");
+ return;
+ }
+*/
+
+ switch (event->EventInfo >> 24) {
+ case 0x04:
+ printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case 0x08:
+ printk(BIOS_DEBUG, "Processor: ");
+ break;
+
+ case 0x10:
+ printk(BIOS_DEBUG, "Hyper Transport: ");
+ break;
+
+ default:
+ break;
+ }
+
+ switch (event->EventInfo) {
+ case MEM_WARNING_UNSUPPORTED_QRDIMM:
+ printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_UDIMM:
+ printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_SODIMM:
+ printk(BIOS_DEBUG, "SO-DIMMs detected but not supported");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_X4DIMM:
+ printk(BIOS_DEBUG, "x4 DIMMs detected but not supported");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_RDIMM:
+ printk(BIOS_DEBUG, "Registered DIMMs detected but not supported");
+ break;
+
+/*
+ case MEM_WARNING_UNSUPPORTED_LRDIMM:
+ printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported");
+ break;
+*/
+
+ case MEM_WARNING_NO_SPDTRC_FOUND:
+ printk(BIOS_DEBUG, "NO_SPDTRC_FOUND");
+ break;
+
+ case MEM_WARNING_EMP_NOT_SUPPORTED:
+ printk(BIOS_DEBUG, "Processor is not capable for EMP");//
+ break;
+
+ case MEM_WARNING_EMP_CONFLICT:
+ printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");//
+ break;
+
+ case MEM_WARNING_EMP_NOT_ENABLED:
+ printk(BIOS_DEBUG, "Memory size is not power of two\n");//
+ break;
+
+ case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED:
+ printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n");
+ break;
+
+ case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n");
+ break;
+
+ case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n");
+ break;
+
+ case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n");
+ break;
+
+ case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED:
+ printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n");
+ break;
+
+/*
+ case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO:
+ printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n");
+ break;
+
+ case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO:
+ printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n");
+ break;
+*/
+
+ case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR:
+ printk(BIOS_DEBUG, "Allocation rule number that has been violated:");
+ if ((event->EventInfo & 0x000000FF) == 0x01) {
+ printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x02) {
+ printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x03) {
+ printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n");
+ }
+ printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case CPU_WARNING_ADJUSTED_LEVELING_MODE:
+ printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE "
+ "requested: %lx, actual level:%lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case CPU_EVENT_PM_PSTATE_OVERCURRENT:
+ printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT "
+ "Socket: %lx, Pstate:%lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG:
+ printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n");
+ break;
+
+/*
+ case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION:
+ printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+*/
+
+ case HT_EVENT_OPT_REQUIRED_CAP_RETRY:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_OPT_REQUIRED_CAP_GEN3:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %lx Link %lx Depth %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_OPT_UNUSED_LINKS:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%lx LinkA%lx SocketB%lx LinkB%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ break;
+
+ case HT_EVENT_OPT_LINK_PAIR_EXCEED:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%lx MasterLink%lx SocketB%lx AltLink%lx\n",
+
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_error(EVENT_PARAMS *event)
+{
+
+ switch (event->EventInfo >> 24) {
+ case 0x04:
+ printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case 0x08:
+ printk(BIOS_DEBUG, "Processor: ");
+ break;
+
+ case 0x10:
+ printk(BIOS_DEBUG, "Hyper Transport: ");
+ break;
+
+ default:
+ break;
+ }
+
+ switch (event->EventInfo) {
+ case MEM_ERROR_NO_DQS_POS_RD_WINDOW:
+ printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n");
+ break;
+
+ case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW:
+ printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n");
+ break;
+
+ case MEM_ERROR_NO_DQS_POS_WR_WINDOW:
+ printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n");
+ break;
+
+ case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW:
+ printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n");
+ break;
+
+ case MEM_ERROR_DIMM_SPARING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n");
+ break;
+
+ case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE:
+ printk(BIOS_DEBUG, "Receive Enable value is too large\n");
+ break;
+ case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW:
+ printk(BIOS_DEBUG, "There is no DQS receiver enable window\n");
+ break;
+
+ case MEM_ERROR_DRAM_ENABLED_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n");
+ break;
+
+ case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n");
+ break;
+
+ case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n");
+ break;
+
+ case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n");
+ break;
+
+ case MEM_ERROR_ENTER_SELF_REF_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n");
+ break;
+
+ case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n");
+ break;
+
+ case MEM_ERROR_EXIT_SELF_REF_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n");
+ break;
+
+ case MEM_ERROR_SEND_MRS_CMD_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n");
+ break;
+
+ case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n");
+ break;
+
+ case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n");
+ break;
+
+ case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n");
+ break;
+
+ case MEM_ERROR_MEM_CLEARED_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n");
+ break;
+
+ case MEM_ERROR_FLUSH_WR_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n");
+ break;
+
+ case MEM_ERROR_MAX_LAT_NO_WINDOW:
+ printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n");
+ break;
+
+ case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL:
+ printk(BIOS_DEBUG, "Fail to launch training code on an AP\n");
+ break;
+
+ case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT:
+ printk(BIOS_DEBUG, "Fail to finish parallel training\n");
+ break;
+
+ case MEM_ERROR_NO_ADDRESS_MAPPING:
+ printk(BIOS_DEBUG, "No address mapping found for a dimm\n");
+ break;
+
+ case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT:
+ printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n");
+ break;
+
+ case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE:
+ printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n");
+ break;
+
+ case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR:
+ printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n");
+ break;
+
+ case MEM_ERROR_NO_CHIPSELECT:
+ printk(BIOS_DEBUG, "No chipselects found\n");
+ break;
+
+ case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM:
+ printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n");
+ break;
+
+ case MEM_ERROR_WL_PRE_OUT_OF_RANGE:
+ printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n");
+ break;
+
+ case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE:
+ printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n");
+ break;
+
+ case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED:
+ printk(BIOS_DEBUG, "Unable to load micro code patch\n");
+ break;
+
+ case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE:
+ printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n");
+ break;
+
+/*
+ case CPU_ERROR_PM_NB_PSTATE_MISMATCH:
+ printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n");
+ break;
+*/
+
+ case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR:
+ printk(BIOS_DEBUG, "Allocation rule number that has been violated:");
+ if ((event->EventInfo & 0x000000FF) == 0x04) {
+ printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x05) {
+ printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x06) {
+ printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x07) {
+ printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n");
+ }
+ printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_COH_NO_TOPOLOGY:
+ printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %lx\n",
+ event->DataParam1);
+ break;
+
+ case HT_EVENT_NCOH_BUID_EXCEED:
+ printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%lx Link%lx Depth%lx"
+ "Current BUID: %lx, Unit Count: %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4 >> 16,
+ event->DataParam4 & 0x0000FFFF);
+ break;
+
+ case HT_EVENT_NCOH_BUS_MAX_EXCEED:
+ printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %lx Link %lx Bus %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_NCOH_CFG_MAP_EXCEED:
+ printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %lx Link %lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case HT_EVENT_NCOH_DEVICE_FAILED:
+ printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID"
+ "Socket %lx Link %lx Depth %lx DeviceID %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ default:
+ break;
+ }
+}
+/**
+ *
+ */
+static void agesa_critical(EVENT_PARAMS *event)
+{
+ switch (event->EventInfo) {
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3:
+ printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR3\n",
+ event->DataParam1);
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2:
+ printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR2\n",
+ event->DataParam1);
+ break;
+
+ case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG:
+ printk(BIOS_DEBUG, "Socket: %lx, Dimm population is not supported\n",
+ event->DataParam1);
+ break;
+
+ case HT_EVENT_COH_PROCESSOR_TYPE_MIX:
+ printk(BIOS_DEBUG, "Socket %lx Link %lx TotalSockets %lx, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_COH_MPCAP_MISMATCH:
+ printk(BIOS_DEBUG, "Socket %lx Link %lx MpCap %lx TotalSockets %lx, HT_EVENT_COH_MPCAP_MISMATCH\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_fatal(EVENT_PARAMS *event)
+{
+
+ switch (event->EventInfo >> 24) {
+ case 0x04:
+ printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case 0x08:
+ printk(BIOS_DEBUG, "Processor: ");
+ break;
+
+ case 0x10:
+ printk(BIOS_DEBUG, "Hyper Transport: ");
+ break;
+
+ default:
+ break;
+ }
+
+ switch (event->EventInfo) {
+ case MEM_ERROR_MINIMUM_MODE:
+ printk(BIOS_DEBUG, "Running in minimum mode\n");
+ break;
+
+ case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM:
+ printk(BIOS_DEBUG, "DIMM modules are missmatched\n");
+ break;
+
+ case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM:
+ printk(BIOS_DEBUG, "No DIMMs have been foun\n");
+ break;
+
+ case MEM_ERROR_MISMATCH_DIMM_CLOCKS:
+ printk(BIOS_DEBUG, "DIMM clocks miss-matched\n");
+ break;
+
+ case MEM_ERROR_NO_CYC_TIME:
+ printk(BIOS_DEBUG, "No cycle time found\n");
+ break;
+ case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS:
+ printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs:
+ printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV:
+ printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD:
+ printk(BIOS_DEBUG, "Heap allocation error for SPD data\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA:
+ printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS:
+ printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA:
+ printk(BIOS_DEBUG, "Heap allocation error for Training Data\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK:
+ printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n");
+ break;
+
+ case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM:
+ printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n");
+ break;
+
+ case MEM_ERROR_VDDIO_UNSUPPORTED:
+ printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n");
+ break;
+
+ case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT:
+ printk(BIOS_DEBUG, "Socket: %lx, All PStates exceeded the motherboard current limit on specified socket\n",
+ event->DataParam1);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ * Interprte the agesa event log to an user readable string
+ */
+static void interpret_agesa_eventlog(EVENT_PARAMS *event)
+{
+ switch (event->EventClass) {
+ case AGESA_BOUNDS_CHK:
+ agesa_bound_check(event);
+ break;
+
+ case AGESA_ALERT:
+ agesa_alert(event);
+ break;
+
+ case AGESA_WARNING:
+ agesa_warning(event);
+ break;
+
+ case AGESA_ERROR:
+ agesa_error(event);
+ break;
+
+ case AGESA_CRITICAL:
+ agesa_critical(event);
+ break;
+
+ case AGESA_FATAL:
+ agesa_fatal(event);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @param HeapStatus -the current HeapStatus
+ */
+UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus)
+{
+ printk(BIOS_DEBUG, "enter in %s\n", __func__);
+ AGESA_STATUS Status;
+ EVENT_PARAMS AmdEventParams;
+
+ LibAmdMemFill(&AmdEventParams,
+ 0,
+ sizeof(EVENT_PARAMS),
+ &(AmdEventParams.StdHeader));
+
+ AmdEventParams.StdHeader.AltImageBasePtr = 0;
+ AmdEventParams.StdHeader.CalloutPtr = NULL;
+ AmdEventParams.StdHeader.Func = 0;
+ AmdEventParams.StdHeader.ImageBasePtr = 0;
+ /* I have to know the current HeapStatus to Locate the EventLogHeapPointer */
+ AmdEventParams.StdHeader.HeapStatus = HeapStatus;
+ Status = AmdReadEventLog(&AmdEventParams);
+ while (AmdEventParams.EventClass != 0) {
+ printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+ printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+ printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+ interpret_agesa_eventlog(&AmdEventParams);
+ Status = AmdReadEventLog(&AmdEventParams);
+ }
+
+ printk(BIOS_DEBUG, "exit %s \n", __func__);
+ return (UINT32)Status;
+}
+
diff --git a/src/mainboard/asus/m5a88-v/agesawrapper.h b/src/mainboard/asus/m5a88-v/agesawrapper.h
new file mode 100644
index 0000000..43c7d10
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/agesawrapper.h
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+
+enum {
+ PICK_DMI, /* DMI Interface */
+ PICK_PSTATE, /* Acpi Pstate SSDT Table */
+ PICK_SRAT, /* SRAT Table */
+ PICK_SLIT, /* SLIT Table */
+ PICK_WHEA_MCE, /* WHEA MCE table */
+ PICK_WHEA_CMC, /* WHEA CMV table */
+ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
+};
+
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+ UINT32 CalloutName;
+ AGESA_STATUS (*CalloutPtr)(UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+} BIOS_CALLOUT_STRUCT;
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+UINT32 agesawrapper_amdinitreset (void);
+UINT32 agesawrapper_amdinitearly (void);
+UINT32 agesawrapper_amdinitenv (void);
+UINT32 agesawrapper_amdinitlate (void);
+UINT32 agesawrapper_amdinitpost (void);
+UINT32 agesawrapper_amdinitmid (void);
+UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus);
+UINT32 agesawrapper_amdinitmmio (void);
+void *agesawrapper_getlateinitptr (int pick);
+UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr);
+
+#endif
diff --git a/src/mainboard/asus/m5a88-v/buildOpts.c b/src/mainboard/asus/m5a88-v/buildOpts.c
new file mode 100644
index 0000000..d0eeaf0
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/buildOpts.c
@@ -0,0 +1,446 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
+ */
+
+#include "AGESA.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+/* Select the cpu family. */
+#define INSTALL_FAMILY_10_SUPPORT TRUE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE
+/* Select the cpu socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP1_SOCKET_SUPPORT FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT TRUE
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT FALSE
+#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
+#define BLDOPT_REMOVE_FAMILY_14_SUPPORT TRUE
+#define BLDOPT_REMOVE_FAMILY_15_SUPPORT FALSE
+
+#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT FALSE
+#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
+
+/*
+ * Agesa entry points used in this implementation.
+ */
+#define AGESA_ENTRY_INIT_RESET TRUE
+#define AGESA_ENTRY_INIT_RECOVERY FALSE
+#define AGESA_ENTRY_INIT_EARLY TRUE
+#define AGESA_ENTRY_INIT_POST TRUE
+#define AGESA_ENTRY_INIT_ENV TRUE
+#define AGESA_ENTRY_INIT_MID TRUE
+#define AGESA_ENTRY_INIT_LATE TRUE
+#define AGESA_ENTRY_INIT_S3SAVE TRUE
+#define AGESA_ENTRY_INIT_RESUME TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
+
+#define BLDOPT_REMOVE_DMI TRUE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+//#define BLDOPT_REMOVE_DMI FALSE //TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+
+/*
+ * Agesa configuration values selection.
+ * Uncomment and specify the value for the configuration options
+ * needed by the system.
+ */
+
+/* The fixed MTRR values to be set after memory initialization. */
+CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+
+#define BLDCFG_VRM_CURRENT_LIMIT 120000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
+
+//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
+//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE
+//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled
+//#define BLDCFG_PLATFORM_C1E_OPDATA 0
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
+#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
+#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP
+//#define BLDCFG_STARTING_BUSNUM 0
+//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
+//#define BLDCFG_ALLOCATED_BUSNUMS 0x20
+//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0
+//#define BLDCFG_BUID_SWAP_LIST 0
+//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0
+//#define BLDCFG_HTFABRIC_LIMITS_LIST 0
+//#define BLDCFG_HTCHAIN_LIMITS_LIST 0
+//#define BLDCFG_BUS_NUMBERS_LIST 0
+//#define BLDCFG_IGNORE_LINK_LIST 0
+//#define BLDCFG_LINK_SKIP_REGANG_LIST 0
+//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0
+//#define BLDCFG_USE_HT_ASSIST TRUE
+//#define BLDCFG_USE_ATM_MODE TRUE
+//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
+#define BLDCFG_S3_LATE_RESTORE FALSE
+//#define BLDCFG_USE_32_BYTE_REFRESH FALSE
+//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
+//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
+//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
+//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
+//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
+//#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_CFG_ABM_SUPPORT FALSE
+//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
+//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
+#define BLDCFG_MEM_INIT_PSTATE 0
+#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+//#define BLDCFG_ENABLE_ECC_FEATURE TRUE
+//#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
+#define BLDCFG_UMA_ALLOCATION_SIZE 0
+#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
+#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
+
+/* Include the files that instantiate the configuration definitions. */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ //
+ // The following macros are supported (use comma to separate macros):
+ //
+ // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+ // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+ // AGESA will base on this value to disable unused MemClk to save power.
+ // Example:
+ // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+ // Bit AM3/S1g3 pin name
+ // 0 M[B,A]_CLK_H/L[0]
+ // 1 M[B,A]_CLK_H/L[1]
+ // 2 M[B,A]_CLK_H/L[2]
+ // 3 M[B,A]_CLK_H/L[3]
+ // 4 M[B,A]_CLK_H/L[4]
+ // 5 M[B,A]_CLK_H/L[5]
+ // 6 M[B,A]_CLK_H/L[6]
+ // 7 M[B,A]_CLK_H/L[7]
+ // And platform has the following routing:
+ // CS0 M[B,A]_CLK_H/L[4]
+ // CS1 M[B,A]_CLK_H/L[2]
+ // CS2 M[B,A]_CLK_H/L[3]
+ // CS3 M[B,A]_CLK_H/L[5]
+ // Then platform can specify the following macro:
+ // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+ //
+ // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+ // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+ // AGESA will base on this value to tristate unused CKE to save power.
+ //
+ // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+ // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+ // AGESA will base on this value to tristate unused ODT pins to save power.
+ //
+ // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+ // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+ // AGESA will base on this value to tristate unused Chip select to save power.
+ //
+ // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+ // Specifies the number of DIMM slots per channel.
+ //
+ // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+ // Specifies the number of Chip selects per channel.
+ //
+ // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+ // Specifies the number of channels per socket.
+ //
+ // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+ // Specifies DDR bus speed of channel ChannelID on socket SocketID.
+ //
+ // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+ // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+ //
+ // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ // Byte6Seed, Byte7Seed, ByteEccSeed)
+ // Specifies the write leveling seed for a channel of a socket.
+ //
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ PSO_END
+};
+
+/*
+ * These tables are optional and may be used to adjust memory timing settings
+ */
+#include "mm.h"
+#include "mn.h"
+
+//DA Customer table
+CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
+{
+ // Hardcoded Memory Training Values
+
+ // The following macro should be used to override training values for your platform
+ //
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+ //
+ // NOTE:
+ // The following training hardcode values are example values that were taken from a tilapia motherboard
+ // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
+ // the table and replace the byte lane values with your own.
+ //
+ // ------------------ BYTE LANES ----------------------
+ // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
+ // Write Data Timing
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+ // DQS Receiver Enable
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+ // Write DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+ // Read DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+ //--------------------------------------------------------------------------------------------------------------------------------------------------
+ // TABLE END
+ NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
+};
+CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
+
+
+/* ***************************************************************************
+ * Optional User code to be included into the AGESA build
+ * These may be 32-bit call-out routines...
+ */
+//AGESA_STATUS
+//AgesaReadSpd (
+// IN UINTN FcnData,
+// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+// )
+//{
+// /* platform code to read an SPD... */
+// return Status;
+//}
+
+
diff --git a/src/mainboard/asus/m5a88-v/devicetree.cb b/src/mainboard/asus/m5a88-v/devicetree.cb
index 4b3142e..e8b8ca8 100644
--- a/src/mainboard/asus/m5a88-v/devicetree.cb
+++ b/src/mainboard/asus/m5a88-v/devicetree.cb
@@ -1,13 +1,14 @@
# sample config for advansus/A785E-I
-chip northbridge/amd/amdfam10/root_complex
+chip northbridge/amd/agesa/family15/root_complex
device cpu_cluster 0 on
- chip cpu/amd/socket_AM3 #L1 and DDR3
- device lapic 0 on end
+ chip cpu/amd/agesa/family15
+ #device lapic 0x20 on end #f15
+ device lapic 0x10 on end #f10
end
end
device domain 0 on
subsystemid 0x1043 0x843e inherit #TODO: Set the correctly subsystem id.
- chip northbridge/amd/amdfam10
+ chip northbridge/amd/agesa/family15 # CPU side of HT root complex
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600
@@ -91,7 +92,7 @@ chip northbridge/amd/amdfam10/root_complex
end
device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO_SUSLED
- device pnp 2e.a off end # ACPI
+ device pnp 2e.a on end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
@@ -119,6 +120,12 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
+ device pci 18.5 on end #f15
+ register "spdAddrLookup" = "
+ {
+ { {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
end
end #domain
end
diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl
index 11684c4..2ca8dc3 100644
--- a/src/mainboard/asus/m5a88-v/dsdt.asl
+++ b/src/mainboard/asus/m5a88-v/dsdt.asl
@@ -27,7 +27,7 @@ DefinitionBlock (
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
@@ -36,10 +36,11 @@ DefinitionBlock (
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
- Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
@@ -64,57 +65,90 @@ DefinitionBlock (
*/
Scope (\_PR) { /* define processor scope */
Processor(
- CPU0, /* name space name */
- 0, /* Unique number for this processor */
- 0x808, /* PBLK system I/O address !hardcoded! */
+ C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */
+ 0x00, /* Unique number for this processor */
+ 0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
- #include "acpi/cpstate.asl"
- }
-
- Processor(
- CPU1, /* name space name */
- 1, /* Unique number for this processor */
- 0x0000, /* PBLK system I/O address !hardcoded! */
- 0x00 /* PBLKLEN for boot processor */
- ) {
- #include "acpi/cpstate.asl"
- }
-
- Processor(
- CPU2, /* name space name */
- 2, /* Unique number for this processor */
- 0x0000, /* PBLK system I/O address !hardcoded! */
- 0x00 /* PBLKLEN for boot processor */
- ) {
- #include "acpi/cpstate.asl"
- }
-
- Processor(
- CPU3, /* name space name */
- 3, /* Unique number for this processor */
- 0x0000, /* PBLK system I/O address !hardcoded! */
- 0x00 /* PBLKLEN for boot processor */
- ) {
- #include "acpi/cpstate.asl"
}
+ Processor(C001, 0x01, 0x00000000, 0x00) {}
+ Processor(C002, 0x02, 0x00000000, 0x00) {}
+ Processor(C003, 0x03, 0x00000000, 0x00) {}
+ Processor(C004, 0x04, 0x00000000, 0x00) {}
+ Processor(C005, 0x05, 0x00000000, 0x00) {}
+ Processor(C006, 0x06, 0x00000000, 0x00) {}
+ Processor(C007, 0x07, 0x00000000, 0x00) {}
+ Processor(C008, 0x08, 0x00000000, 0x00) {}
+ Processor(C009, 0x09, 0x00000000, 0x00) {}
+ Processor(C00A, 0x0A, 0x00000000, 0x00) {}
+ Processor(C00B, 0x0B, 0x00000000, 0x00) {}
+ Processor(C00C, 0x0C, 0x00000000, 0x00) {}
+ Processor(C00D, 0x0D, 0x00000000, 0x00) {}
+ Processor(C00E, 0x0E, 0x00000000, 0x00) {}
+ Processor(C00F, 0x0F, 0x00000000, 0x00) {}
+ Processor(C010, 0x10, 0x00000000, 0x00) {}
+ Processor(C011, 0x11, 0x00000000, 0x00) {}
+ Processor(C012, 0x12, 0x00000000, 0x00) {}
+ Processor(C013, 0x13, 0x00000000, 0x00) {}
+ Processor(C014, 0x14, 0x00000000, 0x00) {}
+ Processor(C015, 0x15, 0x00000000, 0x00) {}
+ Processor(C016, 0x16, 0x00000000, 0x00) {}
+ Processor(C017, 0x17, 0x00000000, 0x00) {}
+ Processor(C018, 0x18, 0x00000000, 0x00) {}
+ Processor(C019, 0x19, 0x00000000, 0x00) {}
+ Processor(C01A, 0x1A, 0x00000000, 0x00) {}
+ Processor(C01B, 0x1B, 0x00000000, 0x00) {}
+ Processor(C01C, 0x1C, 0x00000000, 0x00) {}
+ Processor(C01D, 0x1D, 0x00000000, 0x00) {}
+ Processor(C01E, 0x1E, 0x00000000, 0x00) {}
+ Processor(C01F, 0x1F, 0x00000000, 0x00) {}
+ Processor(C020, 0x20, 0x00000000, 0x00) {}
+ Processor(C021, 0x21, 0x00000000, 0x00) {}
+ Processor(C022, 0x22, 0x00000000, 0x00) {}
+ Processor(C023, 0x23, 0x00000000, 0x00) {}
+ Processor(C024, 0x24, 0x00000000, 0x00) {}
+ Processor(C025, 0x25, 0x00000000, 0x00) {}
+ Processor(C026, 0x26, 0x00000000, 0x00) {}
+ Processor(C027, 0x27, 0x00000000, 0x00) {}
+ Processor(C028, 0x28, 0x00000000, 0x00) {}
+ Processor(C029, 0x29, 0x00000000, 0x00) {}
+ Processor(C02A, 0x2A, 0x00000000, 0x00) {}
+ Processor(C02B, 0x2B, 0x00000000, 0x00) {}
+ Processor(C02C, 0x2C, 0x00000000, 0x00) {}
+ Processor(C02D, 0x2D, 0x00000000, 0x00) {}
+ Processor(C02E, 0x2E, 0x00000000, 0x00) {}
+ Processor(C02F, 0x2F, 0x00000000, 0x00) {}
+ Alias (C000, CPU0)
+ Alias (C001, CPU1)
+ Alias (C002, CPU2)
+ Alias (C003, CPU3)
+ Alias (C004, CPU4)
+ Alias (C005, CPU5)
+ Alias (C006, CPU6)
+ Alias (C007, CPU7)
+ Alias (C008, CPU8)
} /* End _PR scope */
- /* PIC IRQ mapping registers, C00h-C01h. */
+ /* PIC IRQ mapping registers, C00h-C01h */
OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
Field(PRQM, ByteAcc, NoLock, Preserve) {
PRQI, 0x00000008,
PRQD, 0x00000008, /* Offset: 1h */
}
IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PIRA, 0x00000008, /* Index 0 */
- PIRB, 0x00000008, /* Index 1 */
- PIRC, 0x00000008, /* Index 2 */
- PIRD, 0x00000008, /* Index 3 */
- PIRE, 0x00000008, /* Index 4 */
- PIRF, 0x00000008, /* Index 5 */
- PIRG, 0x00000008, /* Index 6 */
- PIRH, 0x00000008, /* Index 7 */
+ PINA, 0x00000008, /* Index 0 */
+ PINB, 0x00000008, /* Index 1 */
+ PINC, 0x00000008, /* Index 2 */
+ PIND, 0x00000008, /* Index 3 */
+ AINT, 0x00000008, /* Index 4 */
+ SINT, 0x00000008, /* Index 5 */
+ , 0x00000008, /* Index 6 */
+ AAUD, 0x00000008, /* Index 7 */
+ AMOD, 0x00000008, /* Index 8 */
+ PINE, 0x00000008, /* Index 9 */
+ PINF, 0x00000008, /* Index A */
+ PING, 0x00000008, /* Index B */
+ PINH, 0x00000008, /* Index C */
}
/* PCI Error control register */
@@ -129,13 +163,13 @@ DefinitionBlock (
/* Client Management index/data registers */
OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
+ CMTI, 8,
/* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
}
/* GPM Port register */
@@ -154,7 +188,7 @@ DefinitionBlock (
/* Flash ROM program enable register */
OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
+ , 0x00000006,
FLRE, 0x00000001,
}
@@ -165,7 +199,7 @@ DefinitionBlock (
PM2D, 0x00000008,
}
- /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+ /* Power Management I/O registers */
OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
Field(PIOR, ByteAcc, NoLock, Preserve) {
PIOI, 0x00000008,
@@ -203,7 +237,7 @@ DefinitionBlock (
IO2S, 1,
IO1S, 1,
IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */
+ Offset(0x20), /* AcpiPmEvtBlk */
APEB, 16,
Offset(0x36), /* GEvtLevelConfig */
, 6,
@@ -300,9 +334,16 @@ DefinitionBlock (
PWDA, 1,
}
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x10),
+ FLG0, 8
+ }
+
Scope(\_SB) {
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
@@ -405,27 +446,23 @@ DefinitionBlock (
}
}
-
#include "acpi/routing.asl"
Scope(\_SB) {
-
Method(CkOT, 0){
-
if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
-
if(CondRefOf(\_OSI,Local1))
{
- Store(1, OSTP) /* Assume some form of XP */
+ Store(1, OSTP) /* Assume some form of XP */
if (\_OSI("Windows 2006")) /* Vista */
{
Store(2, OSTP)
}
} else {
If(WCMP(\_OS,"Linux")) {
- Store(3, OSTP) /* Linux */
+ Store(3, OSTP) /* Linux */
} Else {
- Store(4, OSTP) /* Gotta be WinCE */
+ Store(4, OSTP) /* Gotta be WinCE */
}
}
Return(OSTP)
@@ -440,14 +477,14 @@ DefinitionBlock (
Store(Arg0, PMOD)
}
Method(CIRQ, 0x00, NotSerialized){
- Store(0, PIRA)
- Store(0, PIRB)
- Store(0, PIRC)
- Store(0, PIRD)
- Store(0, PIRE)
- Store(0, PIRF)
- Store(0, PIRG)
- Store(0, PIRH)
+ Store(0, PINA)
+ Store(0, PINB)
+ Store(0, PINC)
+ Store(0, PIND)
+ Store(0, PINE)
+ Store(0, PINF)
+ Store(0, PING)
+ Store(0, PINH)
}
Name(IRQB, ResourceTemplate(){
@@ -467,7 +504,7 @@ DefinitionBlock (
Name(_UID, 1)
Method(_STA, 0) {
- if (PIRA) {
+ if (PINA) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
@@ -476,7 +513,7 @@ DefinitionBlock (
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PIRA)
+ Store(0, PINA)
} /* End Method(_SB.INTA._DIS) */
Method(_PRS ,0) {
@@ -487,7 +524,7 @@ DefinitionBlock (
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKA\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIRA, IRQN)
+ ShiftLeft(1, PINA, IRQN)
Return(IRQB)
} /* Method(_SB.INTA._CRS) */
@@ -500,7 +537,7 @@ DefinitionBlock (
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PIRA)
+ Store(Local0, PINA)
} /* End Method(_SB.INTA._SRS) */
} /* End Device(INTA) */
@@ -509,7 +546,7 @@ DefinitionBlock (
Name(_UID, 2)
Method(_STA, 0) {
- if (PIRB) {
+ if (PINB) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
@@ -518,7 +555,7 @@ DefinitionBlock (
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PIRB)
+ Store(0, PINB)
} /* End Method(_SB.INTB._DIS) */
Method(_PRS ,0) {
@@ -529,7 +566,7 @@ DefinitionBlock (
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKB\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIRB, IRQN)
+ ShiftLeft(1, PINB, IRQN)
Return(IRQB)
} /* Method(_SB.INTB._CRS) */
@@ -542,7 +579,7 @@ DefinitionBlock (
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PIRB)
+ Store(Local0, PINB)
} /* End Method(_SB.INTB._SRS) */
} /* End Device(INTB) */
@@ -551,7 +588,7 @@ DefinitionBlock (
Name(_UID, 3)
Method(_STA, 0) {
- if (PIRC) {
+ if (PINC) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
@@ -560,7 +597,7 @@ DefinitionBlock (
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PIRC)
+ Store(0, PINC)
} /* End Method(_SB.INTC._DIS) */
Method(_PRS ,0) {
@@ -571,7 +608,7 @@ DefinitionBlock (
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKC\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIRC, IRQN)
+ ShiftLeft(1, PINC, IRQN)
Return(IRQB)
} /* Method(_SB.INTC._CRS) */
@@ -584,7 +621,7 @@ DefinitionBlock (
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PIRC)
+ Store(Local0, PINC)
} /* End Method(_SB.INTC._SRS) */
} /* End Device(INTC) */
@@ -593,7 +630,7 @@ DefinitionBlock (
Name(_UID, 4)
Method(_STA, 0) {
- if (PIRD) {
+ if (PIND) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
@@ -602,7 +639,7 @@ DefinitionBlock (
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIRD)
+ Store(0, PIND)
} /* End Method(_SB.INTD._DIS) */
Method(_PRS ,0) {
@@ -613,7 +650,7 @@ DefinitionBlock (
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKD\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIRD, IRQN)
+ ShiftLeft(1, PIND, IRQN)
Return(IRQB)
} /* Method(_SB.INTD._CRS) */
@@ -626,7 +663,7 @@ DefinitionBlock (
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PIRD)
+ Store(Local0, PIND)
} /* End Method(_SB.INTD._SRS) */
} /* End Device(INTD) */
@@ -635,7 +672,7 @@ DefinitionBlock (
Name(_UID, 5)
Method(_STA, 0) {
- if (PIRE) {
+ if (PINE) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
@@ -644,7 +681,7 @@ DefinitionBlock (
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PIRE)
+ Store(0, PINE)
} /* End Method(_SB.INTE._DIS) */
Method(_PRS ,0) {
@@ -655,7 +692,7 @@ DefinitionBlock (
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKE\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIRE, IRQN)
+ ShiftLeft(1, PINE, IRQN)
Return(IRQB)
} /* Method(_SB.INTE._CRS) */
@@ -668,7 +705,7 @@ DefinitionBlock (
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PIRE)
+ Store(Local0, PINE)
} /* End Method(_SB.INTE._SRS) */
} /* End Device(INTE) */
@@ -677,7 +714,7 @@ DefinitionBlock (
Name(_UID, 6)
Method(_STA, 0) {
- if (PIRF) {
+ if (PINF) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
@@ -686,7 +723,7 @@ DefinitionBlock (
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PIRF)
+ Store(0, PINF)
} /* End Method(_SB.INTF._DIS) */
Method(_PRS ,0) {
@@ -697,7 +734,7 @@ DefinitionBlock (
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKF\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIRF, IRQN)
+ ShiftLeft(1, PINF, IRQN)
Return(IRQB)
} /* Method(_SB.INTF._CRS) */
@@ -710,7 +747,7 @@ DefinitionBlock (
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PIRF)
+ Store(Local0, PINF)
} /* End Method(_SB.INTF._SRS) */
} /* End Device(INTF) */
@@ -719,7 +756,7 @@ DefinitionBlock (
Name(_UID, 7)
Method(_STA, 0) {
- if (PIRG) {
+ if (PING) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
@@ -728,7 +765,7 @@ DefinitionBlock (
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PIRG)
+ Store(0, PING)
} /* End Method(_SB.INTG._DIS) */
Method(_PRS ,0) {
@@ -739,7 +776,7 @@ DefinitionBlock (
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKG\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIRG, IRQN)
+ ShiftLeft(1, PING, IRQN)
Return(IRQB)
} /* Method(_SB.INTG._CRS) */
@@ -752,7 +789,7 @@ DefinitionBlock (
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PIRG)
+ Store(Local0, PING)
} /* End Method(_SB.INTG._SRS) */
} /* End Device(INTG) */
@@ -761,7 +798,7 @@ DefinitionBlock (
Name(_UID, 8)
Method(_STA, 0) {
- if (PIRH) {
+ if (PINH) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
@@ -770,7 +807,7 @@ DefinitionBlock (
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PIRH)
+ Store(0, PINH)
} /* End Method(_SB.INTH._DIS) */
Method(_PRS ,0) {
@@ -781,7 +818,7 @@ DefinitionBlock (
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKH\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIRH, IRQN)
+ ShiftLeft(1, PINH, IRQN)
Return(IRQB)
} /* Method(_SB.INTH._CRS) */
@@ -794,7 +831,7 @@ DefinitionBlock (
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PIRH)
+ Store(Local0, PINH)
} /* End Method(_SB.INTH._SRS) */
} /* End Device(INTH) */
@@ -865,6 +902,7 @@ DefinitionBlock (
/* Clear wake status structure. */
Store(0, Index(WKST,0))
Store(0, Index(WKST,1))
+ \_SB.PCI0.SIOS (Arg0)
} /* End Method(\_PTS) */
/*
@@ -943,226 +981,164 @@ DefinitionBlock (
* Store(Arg0, Index(WKST,1))
* }
*/
+ \_SB.PCI0.SIOW (Arg0)
Return(WKST)
} /* End Method(\_WAK) */
Scope(\_GPE) { /* Start Scope GPE */
/* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
+ Method(_L00) {
+ //DBGO("\\_GPE\\_L00\n")
+ }
/* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
+ Method(_L01) {
+ //DBGO("\\_GPE\\_L01\n")
+ }
/* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
+ Method(_L02) {
+ //DBGO("\\_GPE\\_L02\n")
+ }
/* General event 3 */
Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
+ //DBGO("\\_GPE\\_L00\n")
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
+ Method(_L04) {
+ //DBGO("\\_GPE\\_L04\n")
+ }
/* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
+ Method(_L05) {
+ //DBGO("\\_GPE\\_L05\n")
+ }
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
+ /* _L06 General event 6 - Used for GPM6, moved to USB.asl */
+ /* _L07 General event 7 - Used for GPM7, moved to USB.asl */
/* Legacy PM event */
Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
+ //DBGO("\\_GPE\\_L08\n")
}
/* Temp warning (TWarn) event */
Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- /* Notify (\_TZ.TZ00, 0x80) */
+ //DBGO("\\_GPE\\_L09\n")
+ Notify (\_TZ.TZ00, 0x80)
}
/* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
+ Method(_L0A) {
+ //DBGO("\\_GPE\\_L0A\n")
+ }
/* USB controller PME# */
Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
+ //DBGO("\\_GPE\\_L0B\n")
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
+ Method(_L0C) {
+ //DBGO("\\_GPE\\_L0C\n")
+ }
/* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
+ Method(_L0D) {
+ //DBGO("\\_GPE\\_L0D\n")
+ }
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
+ /* _L0E GPM9 SCI event - Moved to USB.asl */
/* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
+ Method(_L0F) {
+ //DBGO("\\_GPE\\_L0F\n")
+ }
/* ExtEvent0 SCI event */
Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
+ //DBGO("\\_GPE\\_L10\n")
}
/* ExtEvent1 SCI event */
Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
+ //DBGO("\\_GPE\\_L11\n")
}
/* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
+ Method(_L12) {
+ //DBGO("\\_GPE\\_L12\n")
+ }
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
+ /* _L13 GPM0 SCI event - Moved to USB.asl */
+ /* _L14 GPM1 SCI event - Moved to USB.asl */
+ /* _L15 GPM2 SCI event - Moved to USB.asl */
+ /* _L16 GPM3 SCI event - Moved to USB.asl */
+ /* _L17 GPM8 SCI event - Moved to USB.asl */
/* GPIO0 or GEvent8 event */
Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
+ //DBGO("\\_GPE\\_L18\n")
Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
+ /* _L19 GPM4 SCI event - Moved to USB.asl */
+ /* _L1A GPM5 SCI event - Moved to USB.asl */
/* Azalia SCI event */
Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
+ //DBGO("\\_GPE\\_L1B\n")
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
+ Method(_L1C) {
+ //DBGO("\\_GPE\\_L1C\n")
+ }
/* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
+ Method(_L1D) {
+ //DBGO("\\_GPE\\_L1D\n")
+ }
/* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
+ Method(_L1E) {
+ //DBGO("\\_GPE\\_L1E\n")
+ }
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
+ /* _L1F SATA SCI event - Moved to sata.asl */
} /* End Scope GPE */
#include "acpi/usb.asl"
- /* South Bridge */
+ /* System Bus */
Scope(\_SB) { /* Start \_SB scope */
#include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
/* _SB.PCI0 */
/* Note: Only need HID on Primary Bus */
Device(PCI0) {
- External (TOM1)
- External (TOM2)
+ External (TOM1) //assigned when update_ssdt()
+ External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
+
Name(_HID, EISAID("PNP0A03"))
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
Method(_BBN, 0) { /* Bus number = 0 */
@@ -1174,8 +1150,8 @@ DefinitionBlock (
}
Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
} /* end _PRT */
/* Describe the Northbridge devices */
@@ -1183,125 +1159,53 @@ DefinitionBlock (
Name(_ADR, 0x00000000)
} /* end AMRT */
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
/* The external GFX bridge */
Device(PBR2) {
Name(_ADR, 0x00020000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
+ If(PMOD){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
} /* end _PRT */
} /* end PBR2 */
- /* Dev3 is also an external GFX bridge, not used in Herring */
+ /* Dev3 is also an external GFX bridge */
Device(PBR4) {
Name(_ADR, 0x00040000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
} /* end _PRT */
} /* end PBR4 */
- Device(PBR5) {
- Name(_ADR, 0x00050000)
+ Device(PBRb) {
+ Name(_ADR, 0x000b0000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
+ If(PMOD){ Return(APSb) } /* APIC mode */
+ Return (PSb) /* PIC Mode */
} /* end _PRT */
- } /* end PBR5 */
+ } /* end PBRb */
- Device(PBR6) {
- Name(_ADR, 0x00060000)
+ Device(PBRc) {
+ Name(_ADR, 0x000c0000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
+ If(PMOD){ Return(APSc) } /* APIC mode */
+ Return (PSc) /* PIC Mode */
} /* end _PRT */
- } /* end PBR6 */
+ } /* end PBRc */
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
+ Device(PBRd) {
+ Name(_ADR, 0x000d0000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
+ If(PMOD){ Return(APSd) } /* APIC mode */
+ Return (PSd) /* PIC Mode */
} /* end _PRT */
- } /* end PBR7 */
-
- /* GPP */
- Device(PBR9) {
- Name(_ADR, 0x00090000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS9) } /* APIC mode */
- Return (PS9) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR9 */
-
- Device(PBRa) {
- Name(_ADR, 0x000A0000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APSa) } /* APIC mode */
- Return (PSa) /* PIC Mode */
- } /* end _PRT */
- } /* end PBRa */
-
- Device(PE20) {
- Name(_ADR, 0x00150000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APE0) } /* APIC mode */
- Return (PE0) /* PIC Mode */
- } /* end _PRT */
- } /* end PE20 */
- Device(PE21) {
- Name(_ADR, 0x00150001)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APE1) } /* APIC mode */
- Return (PE1) /* PIC Mode */
- } /* end _PRT */
- } /* end PE21 */
- Device(PE22) {
- Name(_ADR, 0x00150002)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APE2) } /* APIC mode */
- Return (APE2) /* PIC Mode */
- } /* end _PRT */
- } /* end PE22 */
- Device(PE23) {
- Name(_ADR, 0x00150003)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APE3) } /* APIC mode */
- Return (PE3) /* PIC Mode */
- } /* end _PRT */
- } /* end PE23 */
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
+ } /* end PBRd */
/* Describe the Southbridge devices */
Device(STCR) {
@@ -1310,37 +1214,32 @@ DefinitionBlock (
} /* end STCR */
Device(UOH1) {
- Name(_ADR, 0x00120000)
+ Name(_ADR, 0x00130000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH1 */
Device(UOH2) {
- Name(_ADR, 0x00120002)
+ Name(_ADR, 0x00130001)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH2 */
Device(UOH3) {
- Name(_ADR, 0x00130000)
+ Name(_ADR, 0x00130002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH3 */
Device(UOH4) {
- Name(_ADR, 0x00130002)
+ Name(_ADR, 0x00130003)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH4 */
Device(UOH5) {
- Name(_ADR, 0x00160000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UOH6) {
- Name(_ADR, 0x00160002)
+ Name(_ADR, 0x00130004)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */
Device(UEH1) {
- Name(_ADR, 0x00140005)
+ Name(_ADR, 0x00130005)
Name(_PRW, Package() {0x0B, 3})
} /* end UEH1 */
@@ -1397,7 +1296,7 @@ DefinitionBlock (
/* Real Time Clock Device */
Device(RTC0) {
- Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
+ Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
Name(_CRS, ResourceTemplate() {
IRQNoFlags(){8}
IO(Decode16,0x0070, 0x0070, 0, 2)
@@ -1437,10 +1336,10 @@ DefinitionBlock (
Name(_CRS, ResourceTemplate() {
DMA(Compatibility,BusMaster,Transfer8){4}
IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x00, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x00, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x00, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x00, 0x01)
+ IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
@@ -1452,21 +1351,59 @@ DefinitionBlock (
IRQNoFlags(){13}
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-#if 0
- Device(HPTM) {
+
+ Device (PS2M) {
+ Name (_HID, EisaId ("PNP0F13"))
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
+ IRQNoFlags () {12}
+ })
+ Method (_STA, 0, NotSerialized) {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) {
+ Return (0x0F)
+ } Else {
+ Return (0x00)
+ }
+ }
+ }
+
+ Device (PS2K) {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized) {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) {
+ Return (0x0F)
+ } Else {
+ Return (0x00)
+ }
+ }
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+
+#if 0 //acpi_create_hpet
+ Device(HPET) {
Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Name(CRS, ResourceTemplate() {
+ IRQNoFlags () {0}
+ IRQNoFlags () {2}
+ IRQNoFlags () {8}
+ Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, MNT) /* 1kb reserved space */
})
- Method(_STA, 0) {
+ Method(_STA, 0, NotSerialized) {
Return(0x0F) /* sata is visible */
}
- Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
+ Method(_CRS, 0, NotSerialized) {
+ CreateDwordField(CRS, ^MNT._BAS, HPT)
+ Store(HPBA, HPT)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LIBR.HPET) */
#endif
} /* end LIBR */
@@ -1482,113 +1419,146 @@ DefinitionBlock (
Name(_ADR, 0x00140006)
} /* end Ac97modem */
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-#if 0
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-#endif
- /* memory space for PCI BARs below 4GB */
- Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-#if 0
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
+ /* ITE8718 Support */
+ OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
+ Field (IOID, ByteAcc, NoLock, Preserve)
+ {
+ SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
}
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
+ IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ LDN, 8, /* Logical Device Number */
+ Offset (0x20),
+ CID1, 8, /* Chip ID Byte 1, 0x87 */
+ CID2, 8, /* Chip ID Byte 2, 0x12 */
+ Offset (0x30),
+ ACTR, 8, /* Function activate */
+ Offset (0xF0),
+ APC0, 8, /* APC/PME Event Enable Register */
+ APC1, 8, /* APC/PME Status Register */
+ APC2, 8, /* APC/PME Control Register 1 */
+ APC3, 8, /* Environment Controller Special Configuration Register */
+ APC4, 8 /* APC/PME Control Register 2 */
+ }
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
+ /* Enter the 8718 MB PnP Mode */
+ Method (EPNP)
+ {
+ Store(0x87, SIOI)
+ Store(0x01, SIOI)
+ Store(0x55, SIOI)
+ Store(0x55, SIOI) /* 8718 magic number */
+ }
+ /* Exit the 8718 MB PnP Mode */
+ Method (XPNP)
+ {
+ Store (0x02, SIOI)
+ Store (0x02, SIOD)
+ }
+ /*
+ * Keyboard PME is routed to SB700 Gevent3. We can wake
+ * up the system by pressing the key.
+ */
+ Method (SIOS, 1)
+ {
+ /* We only enable KBD PME for S5. */
+ If (LLess (Arg0, 0x05))
+ {
+ EPNP()
+ /* DBGO("8718F\n") */
+
+ Store (0x4, LDN)
+ Store (One, ACTR) /* Enable EC */
+ /*
+ Store (0x4, LDN)
+ Store (0x04, APC4)
+ */ /* falling edge. which mode? Not sure. */
+
+ Store (0x4, LDN)
+ Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+ Store (0x4, LDN)
+ Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+ XPNP()
}
-#endif
- CreateDWordField(CRES, ^MMIO._BAS, MM1B)
- CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+ }
+ Method (SIOW, 1)
+ {
+ EPNP()
+ Store (0x4, LDN)
+ Store (Zero, APC0) /* disable keyboard PME */
+ Store (0x4, LDN)
+ Store (0xFF, APC1) /* clear keyboard PME status */
+ XPNP()
+ }
+
+ Name (CRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,,)
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x03AF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x03B0, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x03E0, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0918, // Length
+ ,, , TypeStatic)
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x03B0, // Range Minimum
+ 0x03BB, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x000C, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x03C0, // Range Minimum
+ 0x03DF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0020, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic)
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space
+
+ Memory32Fixed (ReadOnly,
+ 0xE0000000, // Address Base
+ 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default)
+ MMIO)
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
+ CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
+
/*
* Declare memory between TOM1 and 4GB as available
* for PCI MMIO.
@@ -1597,22 +1567,23 @@ DefinitionBlock (
* 32bit (0x00000000 - TOM1) will wrap and give the same
* result as 64bit (0x100000000 - TOM1).
*/
- Store(TOM1, MM1B)
+ Store(TOM1, BAS1)
ShiftLeft(0x10000000, 4, Local0)
Subtract(Local0, TOM1, Local0)
- Store(Local0, MM1L)
+ Store(Local0, LEN1)
+ //DBGO(TOM1)
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
+ Return (CRS)
+ }
/*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
Method(_INI, 0) {
/* DBGO("\\_SB\\_INI\n") */
/* DBGO(" DSDT.ASL code from ") */
@@ -1629,12 +1600,11 @@ DefinitionBlock (
/* Determine the OS we're running on */
CkOT()
-
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
+ * Store(0,\PWDE)
+ *}
+ */
} /* End Method(_SB._INI) */
} /* End Device(PCI0) */
@@ -1654,7 +1624,7 @@ DefinitionBlock (
/* DBGO("\n") */
}
} /* End Scope SI */
-#if 0
+
/* SMBUS Support */
Mutex (SBX0, 0x00)
OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
@@ -1819,6 +1789,5 @@ DefinitionBlock (
} /* end of _TMP */
} /* end of TZ00 */
}
-#endif
}
/* End of ASL file */
diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c
index c45364a..7c91bff 100644
--- a/src/mainboard/asus/m5a88-v/get_bus_conf.c
+++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c
@@ -23,10 +23,8 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS
-#include <cpu/amd/multicore.h>
-#endif
-#include <cpu/amd/amdfam10_sysconf.h>
+#include "agesawrapper.h"
+
#if CONFIG_AMD_SB_CIMX
#include <sb_cimx.h>
#endif
@@ -34,7 +32,7 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-int bus_isa;
+u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb800[3];
u32 apicid_sb800;
@@ -48,14 +46,6 @@ u32 pci1234x[] = {
0x0000ff0,
};
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
- 0x20202020,
-};
-
u32 bus_type[256];
u32 sbdn_rs780;
@@ -67,27 +57,40 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
- u32 apicid_base;
+ u32 apicid_base;
+ u32 status;
+
device_t dev;
int i, j;
if (get_bus_conf_done == 1)
- return; /* do it only once */
+ return; /* do it only once */
+
get_bus_conf_done = 1;
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
+ /*
+ * This is the call to AmdInitLate. It is really in the wrong place, conceptually,
+ * but functionally within the coreboot model, this is the best place to make the
+ * call. The logically correct place to call AmdInitLate is after PCI scan is done,
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM. The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain". There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions. The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
+ * called before the ACPI tables are written. This routine is called at the beginning
+ * of each of the write functions called prior to the ACPI write functions, so this
+ * becomes the best place for this call.
+ */
+ status = agesawrapper_amdinitlate();
+ if(status) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
}
- get_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
- sbdn_rs780 = sysconf.sbdn;
sbdn_sb800 = 0;
- for (i = 0; i < 3; i++) {
+ for (i = 0; i < ARRAY_SIZE(bus_sb800); i++) {
bus_sb800[i] = 0;
}
for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
@@ -98,34 +101,23 @@ void get_bus_conf(void)
bus_type[i] = 0; /* default ISA bus. */
}
- bus_type[0] = 1; /* pci */
+ bus_type[0] = 1; /* pci */
- bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+ bus_rs780[0] = 0;
bus_sb800[0] = bus_rs780[0];
- bus_type[bus_rs780[0]] = 1;
-
/* sb800 */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+
if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
for (j = bus_sb800[1]; j < bus_isa; j++)
bus_type[j] = 1;
}
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x15, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- }
- }
- for (j = bus_sb800[2]; j < bus_isa; j++)
- bus_type[j] = 1;
-
/* rs780 */
for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
@@ -141,12 +133,8 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
-#if CONFIG_LOGICAL_CPUS
- apicid_base = get_apicid_base(1);
-#else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-#endif
- apicid_sb800 = apicid_base + 0;
+ apicid_base = CONFIG_MAX_CPUS;
+ apicid_sb800 = apicid_base;
#if CONFIG_AMD_SB_CIMX
sb_Late_Post();
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 8ee338e..4ee12fa 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -26,7 +26,6 @@
#include <device/pci_def.h>
#include "SBPLATFORM.h"
-
u8 is_dev3_present(void);
void set_pcie_dereset(void);
void set_pcie_reset(void);
@@ -37,10 +36,8 @@ void enable_int_gfx(void)
{
volatile u8 *gpio_reg;
-#ifdef UNUSED_CODE
RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
- RWPMIO(SB_PMIOA_REGF6, AccWidthuint8, ~(BIT0), BIT0); /* Disable Gec */
-#endif
+ RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
/* make sure the MMIO(fed80000) is accessible */
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
diff --git a/src/mainboard/asus/m5a88-v/mb_sysconf.h b/src/mainboard/asus/m5a88-v/mb_sysconf.h
deleted file mode 100644
index 289b094..0000000
--- a/src/mainboard/asus/m5a88-v/mb_sysconf.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- u8 bus_isa;
- u8 bus_8132_0;
- u8 bus_8132_1;
- u8 bus_8132_2;
- u8 bus_8111_0;
- u8 bus_8111_1;
- u8 bus_8132a[31][3];
- u8 bus_8151[31][2];
-
- u32 apicid_8111;
- u32 apicid_8132_1;
- u32 apicid_8132_2;
- u32 apicid_8132a[31][2];
- u32 sbdn3;
- u32 sbdn3a[31];
- u32 sbdn5[31];
- u32 bus_type[256];
-};
-
-#endif
diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c
index 6438a68..e80ceb3 100644
--- a/src/mainboard/asus/m5a88-v/mptable.c
+++ b/src/mainboard/asus/m5a88-v/mptable.c
@@ -29,7 +29,6 @@
extern int bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb800[2];
-extern u32 apicid_sb800;
extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb800;
@@ -47,23 +46,47 @@ u8 intr_data[] = {
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
+ u32 apicid_sb800;
+ u32 apicid_rs780;
+ device_t dev;
u32 dword;
- u8 byte;
+ u8 byte;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
-
get_bus_conf();
-
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+ /*
+ * AGESA v5 Apply apic enumeration rules
+ * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+ * put the local-APICs at m..z
+ * For systems with < 16 APICs, put the Local-APICs at 0..n and
+ * put the IO-APICs at (n + 1)..z
+ */
+#if CONFIG_MAX_CPUS >= 16
+ apicid_sb800 = 0x0;
+#else
+ apicid_sb800 = CONFIG_MAX_CPUS + 1;
+#endif
+ apicid_rs780 = apicid_sb800 + 1;
+
+ dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb800 + 0x14, 0));
+ if (dev) {
+ /* Set sb800 IOAPIC ID */
+ dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+
+ /* Set rs780 IOAPIC ID */
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (dev) {
+ pci_write_config32(dev, 0xF8, 0x1);
+ dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ smp_write_ioapic(mc, apicid_rs780, 0x20, dword);
+ }
+ }
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
@@ -128,11 +151,24 @@ static void *smp_write_config_table(void *v)
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+ PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+ PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+ PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+ PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
+ PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
+ PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+
+ /* PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c
deleted file mode 100644
index 183883a..0000000
--- a/src/mainboard/asus/m5a88-v/resourcemap.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index ddb0e6f..8f7661e 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -17,6 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+
//#define SYSTEM_TYPE 0 /* SERVER */
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
@@ -26,83 +27,42 @@
#define FAM10_ALLOCATE_IO_RANGE 0
#include <lib.h>
+#include <reset.h>
#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
#include <arch/io.h>
+#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include "northbridge/amd/amdfam10/raminit.h"
-#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <arch/stages.h>
#include "cpu/x86/bist.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "agesawrapper.h"
+#include "northbridge/amd/agesa/family10/reset_test.h"
#include "superio/ite/it8721f/early_serial.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include <cpu/amd/mtrr.h>
-#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "drivers/pc80/i8254.c"
+#include "drivers/pc80/i8259.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <sb_cimx.h>
#include <SBPLATFORM.h> /* SB OEM constants */
-#include <southbridge/amd/cimx/sb800/smbus.h>
-#include "northbridge/amd/amdfam10/debug.c"
-
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
-static int spd_read_byte(u32 device, u32 address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/pci.c"
-#include "resourcemap.c"
-#include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
-#include "cpu/amd/microcode/microcode.c"
-#if CONFIG_UPDATE_CPU_MICROCODE
-#include "cpu/amd/model_10xxx/update_microcode.c"
-#endif
-#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "northbridge/amd/amdfam10/early_ht.c"
-#include "spd.h"
-#include <reset.h>
+extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = &sysinfo_car;
- static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0, val;
- msr_t msr;
+ u32 val;
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- /* mov bsp to bus 0xff when > 8 nodes */
- set_bsp_node_CHtExtNodeCfgEn();
- enumerate_ht_chain();
-
- //enable port80 decoding and southbridge poweron init
- sb_Poweron_Init();
- }
post_code(0x30);
- if (bist == 0) {
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
- /* All cores run this but the BSP(node0,core0) is the only core that returns. */
- }
+ agesawrapper_amdinitmmio();
post_code(0x32);
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
- enable_rs780_dev8();
+ enable_rs780_dev8();
sb800_clk_output_48Mhz();
it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -118,139 +78,80 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
- /* Setup sysinfo defaults */
- set_sysinfo_in_ram(0);
-
-#if CONFIG_UPDATE_CPU_MICROCODE
- update_microcode(val);
-#endif
- post_code(0x33);
-
- cpuSetAMDMSR();
- post_code(0x34);
-
- amd_ht_init(sysinfo);
- post_code(0x35);
-
- /* Setup nodes PCI space and start core 0 AP init. */
- finalize_node_setup(sysinfo);
-
- /* Setup any mainboard PCI settings etc. */
- setup_mb_resource_map();
- post_code(0x36);
-
- /* wait for all the APs core0 started by finalize_node_setup. */
- /* FIXME: A bunch of cores are going to start output to serial at once.
- It would be nice to fixup prink spinlocks for ROM XIP mode.
- I think it could be done by putting the spinlock flag in the cache
- of the BSP located right after sysinfo.
- */
- wait_all_core0_started();
+ post_code(0x37);
+ printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
+ val = agesawrapper_amdinitreset();
+ if (val)
+ printk(BIOS_DEBUG, "error level: %x \n", val);
+ else
+ printk(BIOS_DEBUG, "passed.\n");
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x38);
-#if CONFIG_LOGICAL_CPUS
- /* Core0 on each node is configured. Now setup any additional cores. */
- printk(BIOS_DEBUG, "start_other_cores()\n");
- start_other_cores();
- post_code(0x37);
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- post_code(0x38);
-
- /* run _early_setup before soft-reset. */
- rs780_early_setup();
-
-#if CONFIG_SET_FIDVID
- msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
- post_code(0x39);
-
- if (!warm_reset_detect(0)) { // BSP is node 0
- init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
- } else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ //enable port80 decoding and southbridge poweron init
+ post_code(0x3A);
+ sb_Poweron_Init();
}
- post_code(0x3A);
+ post_code(0x3B);
+ rs780_early_setup();
+ printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
+ val = agesawrapper_amdinitearly();
+ if (val)
+ printk(BIOS_DEBUG, "error level: %x \n", val);
+ else
+ printk(BIOS_DEBUG, "passed.\n"); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
- /* show final fid and vid */
- msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
-#endif
- rs780_htinit();
+ rs780_htinit();
- /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
+ distinguish_cpu_resets(0);
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
-
- post_code(0x3B);
-
- /* It's the time to set ctrl in sysinfo now; */
- printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+ post_code(0x39);
post_code(0x40);
+ printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
+ val = agesawrapper_amdinitpost();
+ if (val)
+ printk(BIOS_DEBUG, "error level: %x \n", val);
+ else
+ printk(BIOS_DEBUG, "passed.\n");
-// die("Die Before MCT init.");
-
- printk(BIOS_DEBUG, "raminit_amdmct()\n");
- raminit_amdmct(sysinfo);
post_code(0x41);
+ printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
+ val = agesawrapper_amdinitenv();
+ if (val)
+ printk(BIOS_DEBUG, "error level: %x \n", val);
+ else
+ printk(BIOS_DEBUG, "passed.\n");
+
+ /* Initialize i8259 pic */
+ post_code(0x41);
+ setup_i8259();
-/*
- dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
-*/
+ /* Initialize i8254 timers */
+ post_code(0x42);
+ setup_i8254();
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
+ rs780_before_pci_init();
-// die("After MCT init before CAR disabled.");
+ post_code(0x50);
+ print_debug("Disabling cache as ram ");
+ disable_cache_as_ram();
+ print_debug("done\n");
- rs780_before_pci_init();
+ post_code(0x51);
+ copy_and_run();
- post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ /* We will not return, Should never see this message and post code. */
+ print_debug("should not be here -\n");
+ post_code(0x54);
}
-/**
- * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
- * Description:
- * This routine is called every time a non-coherent chain is processed.
- * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
- * swap list. The first part of the list controls the BUID assignment and the
- * second part of the list provides the device to device linking. Device orientation
- * can be detected automatically, or explicitly. See documentation for more details.
- *
- * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- * based on each device's unit count.
- *
- * Parameters:
- * @param[in] u8 node = The node on which this chain is located
- * @param[in] u8 link = The link on the host for this chain
- * @param[out] u8** list = supply a pointer to a list
- * @param[out] BOOL result = true to use a manual list
- * false to initialize the link automatically
- */
-BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
-{
- static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
- /* If the BUID was adjusted in early_ht we need to do the manual override */
- if ((node == 0) && (link == 0)) { /* BSP SB link */
- *List = swaplist;
- return 1;
- }
-
- return 0;
-}
1
0
New patch to review for coreboot: 0c41c48 Add support for DMP Vortex86EX PCI mainboard.
by Andrew Wu 05 Jul '13
by Andrew Wu 05 Jul '13
05 Jul '13
Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3610
-gerrit
commit 0c41c48350fec7eb3f25a62e5d78c95b2478efa6
Author: Andrew Wu <arw(a)dmp.com.tw>
Date: Fri Jul 5 17:29:41 2013 +0800
Add support for DMP Vortex86EX PCI mainboard.
Change-Id: I8d42f765519e356d8f0cc6ed339d9b74f0a3e4d7
Signed-off-by: Andrew Wu <arw(a)dmp.com.tw>
---
src/mainboard/Kconfig | 3 +
src/mainboard/dmp/Kconfig | 36 +
src/mainboard/dmp/vortex86ex/Kconfig | 1661 ++++++++++++++++++++++++++++
src/mainboard/dmp/vortex86ex/devicetree.cb | 34 +
src/mainboard/dmp/vortex86ex/irq_tables.c | 57 +
src/mainboard/dmp/vortex86ex/mainboard.c | 34 +
src/mainboard/dmp/vortex86ex/romstage.c | 360 ++++++
7 files changed, 2185 insertions(+)
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index 1e5d4bd..d6413c9 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -50,6 +50,8 @@ config VENDOR_COMPAQ
bool "Compaq"
config VENDOR_DIGITALLOGIC
bool "DIGITAL-LOGIC"
+config VENDOR_DMP
+ bool "DMP"
config VENDOR_EAGLELION
bool "EagleLion"
config VENDOR_ECS
@@ -160,6 +162,7 @@ source "src/mainboard/biostar/Kconfig"
source "src/mainboard/broadcom/Kconfig"
source "src/mainboard/compaq/Kconfig"
source "src/mainboard/digitallogic/Kconfig"
+source "src/mainboard/dmp/Kconfig"
source "src/mainboard/eaglelion/Kconfig"
source "src/mainboard/ecs/Kconfig"
source "src/mainboard/emulation/Kconfig"
diff --git a/src/mainboard/dmp/Kconfig b/src/mainboard/dmp/Kconfig
new file mode 100644
index 0000000..c3196d2
--- /dev/null
+++ b/src/mainboard/dmp/Kconfig
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if VENDOR_DMP
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_DMP_EX
+ bool "Vortex86EX"
+
+endchoice
+
+source "src/mainboard/dmp/vortex86ex/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "DMP"
+
+endif # VENDOR_DMP
diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig
new file mode 100644
index 0000000..723a251
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/Kconfig
@@ -0,0 +1,1661 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_DMP_EX
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_DMP_VORTEX86EX
+ select NORTHBRIDGE_DMP_VORTEX86EX
+ select SOUTHBRIDGE_DMP_VORTEX86EX
+ select HAVE_PIRQ_TABLE
+ select BOARD_ROMSIZE_KB_256
+ select ROMCC
+ select DEFAULT_EARLY_CONSOLE
+ select HAVE_DEBUG_RAM_SETUP
+
+config MAINBOARD_DIR
+ string
+ default dmp/vortex86ex
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Vortex86EX"
+
+config IRQ_SLOT_COUNT
+ int
+ default 12
+
+config ID_SECTION_OFFSET
+ # Vortex86 ROM fixed data areas used too big range, we need
+ # to move ID from default address to another place.
+ # 18K below top of ROM should be ok.
+ hex
+ default 0x4800
+
+# ROM Strap PLL config setting :
+
+choice
+ prompt "ROM Strap PLL config"
+ default PLL_300_300_33
+
+config PLL_200_200_33
+ bool "CPU=200Mhz/DRAM=200Mhz/PCI=33Mhz"
+
+config PLL_300_300_33
+ bool "CPU=300Mhz/DRAM=300Mhz/PCI=33Mhz"
+
+config PLL_300_300_100
+ bool "CPU=300Mhz/DRAM=300Mhz/PCI=100Mhz"
+
+config PLL_400_200_33
+ bool "CPU=400Mhz/DRAM=200Mhz/PCI=33Mhz"
+
+config PLL_400_200_100
+ bool "CPU=400Mhz/DRAM=200Mhz/PCI=100Mhz"
+
+config PLL_400_400_33
+ bool "CPU=400Mhz/DRAM=400Mhz/PCI=33Mhz"
+
+config PLL_500_250_33
+ bool "CPU=500Mhz/DRAM=250Mhz/PCI=33Mhz"
+
+config PLL_500_500_33
+ bool "CPU=500Mhz/DRAM=500Mhz/PCI=33Mhz"
+
+config PLL_400_300_33
+ bool "CPU=400Mhz/DRAM=300Mhz/PCI=33Mhz"
+
+config PLL_400_300_100
+ bool "CPU=400Mhz/DRAM=300Mhz/PCI=100Mhz"
+
+config PLL_444_333_33
+ bool "CPU=444Mhz/DRAM=333Mhz/PCI=33Mhz"
+
+config PLL_466_350_33
+ bool "CPU=466Mhz/DRAM=350Mhz/PCI=33Mhz"
+
+config PLL_500_375_33
+ bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz"
+
+endchoice
+
+menu "On-Chip Device Power Down Control"
+
+ config TEMP_POWERDOWN
+ bool "Temperature sensor power-down"
+
+ config SATA_POWERDOWN
+ bool "SATA power-down"
+
+ config ADC_POWERDOWN
+ bool "ADC power-down"
+
+ config PCIE0_POWERDOWN
+ bool "PCIE0 power-down"
+
+ config MAC_POWERDOWN
+ bool "MAC power-down"
+
+ config USB1_POWERDOWN
+ bool "USB2.0 Host Controller 1 power-down"
+
+ config IDE_POWERDOWN
+ bool "IDE power-down"
+
+endmenu
+
+menu "Watchdog Timer setting"
+
+config WDT1_INITIALIZE
+ bool "Initialize WDT1"
+ default n
+
+config WDT1_ENABLE
+ depends on WDT1_INITIALIZE
+ bool "Enable WDT1"
+ default n
+
+choice
+ depends on WDT1_INITIALIZE
+ prompt "WDT1 Signal Select"
+ default WDT1_SIGNAL_RESET
+
+config WDT1_SINGAL_NMI
+ bool "NMI"
+config WDT1_SIGNAL_RESET
+ bool "Reset"
+config WDT1_SIGNAL_SMI
+ bool "SMI"
+
+endchoice
+
+endmenu
+
+menu "IDE controller setting"
+
+choice
+ prompt "Operation Mode"
+ default IDE_NATIVE_MODE
+
+config IDE_NATIVE_MODE
+ bool "Native Mode"
+config IDE_LEGACY_MODE
+ bool "Legacy Mode"
+
+endchoice
+
+config IDE1_ENABLE
+ bool "IDE Primary channel Enable"
+ default y
+
+config IDE2_ENABLE
+ bool "IDE Secondary channel Enable"
+ default y
+
+config IDE_STANDARD_COMPATIBLE
+ bool "Standard IDE Compatible"
+ default n
+ help
+ Built-in IDE controller PCI vendor/device ID is 17F3:1012, which
+ is not recognized by some OSes.
+
+ This option can change IDE controller PCI vendor/device ID to
+ other value for software compatibility.
+
+config IDE_COMPATIBLE_SELECTION
+ depends on IDE_STANDARD_COMPATIBLE
+ hex "IDE Compatible Selection"
+ default 0x808624db
+ help
+ IDE controller PCI vendor/device ID value setting.
+
+ Higher 16-bit is vendor ID, lower 16-bit is device ID.
+
+endmenu
+
+# GPIO setting :
+menu "GPIO setting"
+
+# Begin of GPIO0
+config GPIO_P0_ENABLE
+ bool "GPIO port 0 Enable"
+ default n
+
+config GPIO_P0_DATA_ADDR
+ hex "GPIO port 0 data address"
+ depends on GPIO_P0_ENABLE
+
+config GPIO_P0_DIR_ADDR
+ hex "GPIO port 0 direction address"
+ depends on GPIO_P0_ENABLE
+
+config GPIO_P0_INIT_DIR
+ hex "GPIO port 0 initial direction"
+ default 0x00
+ depends on GPIO_P0_ENABLE
+
+config GPIO_P0_INIT_DATA
+ hex "GPIO port 0 initial data"
+ depends on GPIO_P0_ENABLE
+# end of GPIO0
+
+# Begin of GPIO1
+config GPIO_P1_ENABLE
+ bool "GPIO port 1 Enable"
+ default n
+
+config GPIO_P1_DATA_ADDR
+ hex "GPIO port 1 data address"
+ depends on GPIO_P1_ENABLE
+
+config GPIO_P1_DIR_ADDR
+ hex "GPIO port 1 direction address"
+ depends on GPIO_P1_ENABLE
+
+config GPIO_P1_INIT_DIR
+ hex "GPIO port 1 initial direction"
+ default 0x00
+ depends on GPIO_P1_ENABLE
+
+config GPIO_P1_INIT_DATA
+ hex "GPIO port 1 initial data"
+ depends on GPIO_P1_ENABLE
+# end of GPIO1
+
+# Begin of GPIO2
+config GPIO_P2_ENABLE
+ bool "GPIO port 2 Enable"
+ default n
+
+config GPIO_P2_DATA_ADDR
+ hex "GPIO port 2 data address"
+ depends on GPIO_P2_ENABLE
+
+config GPIO_P2_DIR_ADDR
+ hex "GPIO port 2 direction address"
+ depends on GPIO_P2_ENABLE
+
+config GPIO_P2_INIT_DIR
+ hex "GPIO port 2 initial direction"
+ default 0x00
+ depends on GPIO_P2_ENABLE
+
+config GPIO_P2_INIT_DATA
+ hex "GPIO port 2 initial data"
+ depends on GPIO_P2_ENABLE
+# end of GPIO2
+
+# Begin of GPIO3
+config GPIO_P3_ENABLE
+ bool "GPIO port 3 Enable"
+ default n
+
+config GPIO_P3_DATA_ADDR
+ hex "GPIO port 3 data address"
+ depends on GPIO_P3_ENABLE
+
+config GPIO_P3_DIR_ADDR
+ hex "GPIO port 3 direction address"
+ depends on GPIO_P3_ENABLE
+
+config GPIO_P3_INIT_DIR
+ hex "GPIO port 3 initial direction"
+ default 0x00
+ depends on GPIO_P3_ENABLE
+
+config GPIO_P3_INIT_DATA
+ hex "GPIO port 3 initial data"
+ depends on GPIO_P3_ENABLE
+# end of GPIO3
+
+# Begin of GPIO4
+config GPIO_P4_ENABLE
+ bool "GPIO port 4 Enable"
+ default n
+
+config GPIO_P4_DATA_ADDR
+ hex "GPIO port 4 data address"
+ depends on GPIO_P4_ENABLE
+
+config GPIO_P4_DIR_ADDR
+ hex "GPIO port 4 direction address"
+ depends on GPIO_P4_ENABLE
+
+config GPIO_P4_INIT_DIR
+ hex "GPIO port 4 initial direction"
+ default 0x00
+ depends on GPIO_P4_ENABLE
+
+config GPIO_P4_INIT_DATA
+ hex "GPIO port 4 initial data"
+ depends on GPIO_P4_ENABLE
+# end of GPIO4
+
+# Begin of GPIO5
+config GPIO_P5_ENABLE
+ bool "GPIO port 5 Enable"
+ default n
+
+config GPIO_P5_DATA_ADDR
+ hex "GPIO port 5 data address"
+ depends on GPIO_P5_ENABLE
+
+config GPIO_P5_DIR_ADDR
+ hex "GPIO port 5 direction address"
+ depends on GPIO_P5_ENABLE
+
+config GPIO_P5_INIT_DIR
+ hex "GPIO port 5 initial direction"
+ default 0x00
+ depends on GPIO_P5_ENABLE
+
+config GPIO_P5_INIT_DATA
+ hex "GPIO port 5 initial data"
+ depends on GPIO_P5_ENABLE
+# end of GPIO5
+
+# Begin of GPIO6
+config GPIO_P6_ENABLE
+ bool "GPIO port 6 Enable"
+ default n
+
+config GPIO_P6_DATA_ADDR
+ hex "GPIO port 6 data address"
+ depends on GPIO_P6_ENABLE
+
+config GPIO_P6_DIR_ADDR
+ hex "GPIO port 6 direction address"
+ depends on GPIO_P6_ENABLE
+
+config GPIO_P6_INIT_DIR
+ hex "GPIO port 6 initial direction"
+ default 0x00
+ depends on GPIO_P6_ENABLE
+
+config GPIO_P6_INIT_DATA
+ hex "GPIO port 6 initial data"
+ depends on GPIO_P6_ENABLE
+# end of GPIO6
+
+# Begin of GPIO7
+config GPIO_P7_ENABLE
+ bool "GPIO port 7 Enable"
+ default n
+
+config GPIO_P7_DATA_ADDR
+ hex "GPIO port 7 data address"
+ depends on GPIO_P7_ENABLE
+
+config GPIO_P7_DIR_ADDR
+ hex "GPIO port 7 direction address"
+ depends on GPIO_P7_ENABLE
+
+config GPIO_P7_INIT_DIR
+ hex "GPIO port 7 initial direction"
+ default 0x00
+ depends on GPIO_P7_ENABLE
+
+config GPIO_P7_INIT_DATA
+ hex "GPIO port 7 initial data"
+ depends on GPIO_P7_ENABLE
+# end of GPIO7
+
+# Begin of GPIO8
+config GPIO_P8_ENABLE
+ bool "GPIO port 8 Enable"
+ default n
+
+config GPIO_P8_DATA_ADDR
+ hex "GPIO port 8 data address"
+ depends on GPIO_P8_ENABLE
+
+config GPIO_P8_DIR_ADDR
+ hex "GPIO port 8 direction address"
+ depends on GPIO_P8_ENABLE
+
+config GPIO_P8_INIT_DIR
+ hex "GPIO port 8 initial direction"
+ default 0x00
+ depends on GPIO_P8_ENABLE
+
+config GPIO_P8_INIT_DATA
+ hex "GPIO port 8 initial data"
+ depends on GPIO_P8_ENABLE
+# end of GPIO8
+
+# Begin of GPIO9
+config GPIO_P9_ENABLE
+ bool "GPIO port 9 Enable"
+ default n
+
+config GPIO_P9_DATA_ADDR
+ hex "GPIO port 9 data address"
+ depends on GPIO_P9_ENABLE
+
+config GPIO_P9_DIR_ADDR
+ hex "GPIO port 9 direction address"
+ depends on GPIO_P9_ENABLE
+
+config GPIO_P9_INIT_DIR
+ hex "GPIO port 9 initial direction"
+ default 0x00
+ depends on GPIO_P9_ENABLE
+
+config GPIO_P9_INIT_DATA
+ hex "GPIO port 9 initial data"
+ depends on GPIO_P9_ENABLE
+# end of GPIO9
+
+endmenu
+
+# UART setting :
+menu "UART setting"
+
+# Begin of UART1
+config UART1_ENABLE
+ bool "UART1 Enable"
+ default y
+
+choice
+ prompt "UART1 I/O port"
+ default UART1_IO_PORT_3F8
+ depends on UART1_ENABLE
+
+config UART1_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART1_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART1_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART1_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART1_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART1_IO_PORT_OTHER_INPUT
+ hex "UART1 I/O port"
+ depends on UART1_ENABLE && UART1_IO_PORT_OTHER
+
+config UART1_IO
+ hex
+ depends on UART1_ENABLE
+ default 0x3f8 if UART1_IO_PORT_3F8
+ default 0x2f8 if UART1_IO_PORT_2F8
+ default 0x3e8 if UART1_IO_PORT_3E8
+ default 0x2e8 if UART1_IO_PORT_2E8
+ default UART1_IO_PORT_OTHER_INPUT if UART1_IO_PORT_OTHER
+
+choice
+ prompt "UART1 IRQ"
+ default UART1_IRQ4
+ depends on UART1_ENABLE
+
+config UART1_IRQ_DISABLE
+ bool "Disable"
+config UART1_IRQ3
+ bool "IRQ3, COM2"
+config UART1_IRQ4
+ bool "IRQ4, COM1"
+config UART1_IRQ5
+ bool "IRQ5"
+config UART1_IRQ6
+ bool "IRQ6"
+config UART1_IRQ7
+ bool "IRQ7"
+config UART1_IRQ9
+ bool "IRQ9"
+config UART1_IRQ10
+ bool "IRQ10, COM3"
+config UART1_IRQ11
+ bool "IRQ11, COM4"
+config UART1_IRQ12
+ bool "IRQ12"
+config UART1_IRQ14
+ bool "IRQ14"
+config UART1_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART1_IRQ
+ int
+ depends on UART1_ENABLE
+ default 0 if UART1_IRQ_DISABLE
+ default 3 if UART1_IRQ3
+ default 4 if UART1_IRQ4
+ default 5 if UART1_IRQ5
+ default 6 if UART1_IRQ6
+ default 7 if UART1_IRQ7
+ default 9 if UART1_IRQ9
+ default 10 if UART1_IRQ10
+ default 11 if UART1_IRQ11
+ default 12 if UART1_IRQ12
+ default 14 if UART1_IRQ14
+ default 15 if UART1_IRQ15
+
+choice
+ prompt "UART1 Baud rate"
+ default UART1_BAUD_115200
+ depends on UART1_ENABLE
+
+config UART1_BAUD_115200
+ bool "115200"
+config UART1_BAUD_57600
+ bool "57600"
+config UART1_BAUD_38400
+ bool "38400"
+config UART1_BAUD_19200
+ bool "19200"
+config UART1_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART1_BAUD
+ int
+ depends on UART1_ENABLE
+ default 115200 if UART1_BAUD_115200
+ default 57600 if UART1_BAUD_57600
+ default 38400 if UART1_BAUD_38400
+ default 19200 if UART1_BAUD_19200
+ default 9600 if UART1_BAUD_9600
+# end of UART1
+
+# Begin of UART2
+config UART2_ENABLE
+ bool "UART2 Enable"
+ default y
+
+choice
+ prompt "UART2 I/O port"
+ default UART2_IO_PORT_2F8
+ depends on UART2_ENABLE
+
+config UART2_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART2_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART2_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART2_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART2_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART2_IO_PORT_OTHER_INPUT
+ hex "UART2 I/O port"
+ depends on UART2_ENABLE && UART2_IO_PORT_OTHER
+
+config UART2_IO
+ hex
+ depends on UART2_ENABLE
+ default 0x3f8 if UART2_IO_PORT_3F8
+ default 0x2f8 if UART2_IO_PORT_2F8
+ default 0x3e8 if UART2_IO_PORT_3E8
+ default 0x2e8 if UART2_IO_PORT_2E8
+ default UART2_IO_PORT_OTHER_INPUT if UART2_IO_PORT_OTHER
+
+choice
+ prompt "UART2 IRQ"
+ default UART2_IRQ3
+ depends on UART2_ENABLE
+
+config UART2_IRQ_DISABLE
+ bool "Disable"
+config UART2_IRQ3
+ bool "IRQ3, COM2"
+config UART2_IRQ4
+ bool "IRQ4, COM1"
+config UART2_IRQ5
+ bool "IRQ5"
+config UART2_IRQ6
+ bool "IRQ6"
+config UART2_IRQ7
+ bool "IRQ7"
+config UART2_IRQ9
+ bool "IRQ9"
+config UART2_IRQ10
+ bool "IRQ10, COM3"
+config UART2_IRQ11
+ bool "IRQ11, COM4"
+config UART2_IRQ12
+ bool "IRQ12"
+config UART2_IRQ14
+ bool "IRQ14"
+config UART2_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART2_IRQ
+ int
+ depends on UART2_ENABLE
+ default 0 if UART2_IRQ_DISABLE
+ default 3 if UART2_IRQ3
+ default 4 if UART2_IRQ4
+ default 5 if UART2_IRQ5
+ default 6 if UART2_IRQ6
+ default 7 if UART2_IRQ7
+ default 9 if UART2_IRQ9
+ default 10 if UART2_IRQ10
+ default 11 if UART2_IRQ11
+ default 12 if UART2_IRQ12
+ default 14 if UART2_IRQ14
+ default 15 if UART2_IRQ15
+
+choice
+ prompt "UART2 Baud rate"
+ default UART2_BAUD_115200
+ depends on UART2_ENABLE
+
+config UART2_BAUD_115200
+ bool "115200"
+config UART2_BAUD_57600
+ bool "57600"
+config UART2_BAUD_38400
+ bool "38400"
+config UART2_BAUD_19200
+ bool "19200"
+config UART2_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART2_BAUD
+ int
+ depends on UART2_ENABLE
+ default 115200 if UART2_BAUD_115200
+ default 57600 if UART2_BAUD_57600
+ default 38400 if UART2_BAUD_38400
+ default 19200 if UART2_BAUD_19200
+ default 9600 if UART2_BAUD_9600
+# end of UART2
+
+# Begin of UART3
+config UART3_ENABLE
+ bool "UART3 Enable"
+ default y
+
+choice
+ prompt "UART3 I/O port"
+ default UART3_IO_PORT_3E8
+ depends on UART3_ENABLE
+
+config UART3_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART3_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART3_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART3_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART3_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART3_IO_PORT_OTHER_INPUT
+ hex "UART3 I/O port"
+ depends on UART3_ENABLE && UART3_IO_PORT_OTHER
+
+config UART3_IO
+ hex
+ depends on UART3_ENABLE
+ default 0x3f8 if UART3_IO_PORT_3F8
+ default 0x2f8 if UART3_IO_PORT_2F8
+ default 0x3e8 if UART3_IO_PORT_3E8
+ default 0x2e8 if UART3_IO_PORT_2E8
+ default UART3_IO_PORT_OTHER_INPUT if UART3_IO_PORT_OTHER
+
+choice
+ prompt "UART3 IRQ"
+ default UART3_IRQ10
+ depends on UART3_ENABLE
+
+config UART3_IRQ_DISABLE
+ bool "Disable"
+config UART3_IRQ3
+ bool "IRQ3, COM2"
+config UART3_IRQ4
+ bool "IRQ4, COM1"
+config UART3_IRQ5
+ bool "IRQ5"
+config UART3_IRQ6
+ bool "IRQ6"
+config UART3_IRQ7
+ bool "IRQ7"
+config UART3_IRQ9
+ bool "IRQ9"
+config UART3_IRQ10
+ bool "IRQ10, COM3"
+config UART3_IRQ11
+ bool "IRQ11, COM4"
+config UART3_IRQ12
+ bool "IRQ12"
+config UART3_IRQ14
+ bool "IRQ14"
+config UART3_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART3_IRQ
+ int
+ depends on UART3_ENABLE
+ default 0 if UART3_IRQ_DISABLE
+ default 3 if UART3_IRQ3
+ default 4 if UART3_IRQ4
+ default 5 if UART3_IRQ5
+ default 6 if UART3_IRQ6
+ default 7 if UART3_IRQ7
+ default 9 if UART3_IRQ9
+ default 10 if UART3_IRQ10
+ default 11 if UART3_IRQ11
+ default 12 if UART3_IRQ12
+ default 14 if UART3_IRQ14
+ default 15 if UART3_IRQ15
+
+choice
+ prompt "UART3 Baud rate"
+ default UART3_BAUD_115200
+ depends on UART3_ENABLE
+
+config UART3_BAUD_115200
+ bool "115200"
+config UART3_BAUD_57600
+ bool "57600"
+config UART3_BAUD_38400
+ bool "38400"
+config UART3_BAUD_19200
+ bool "19200"
+config UART3_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART3_BAUD
+ int
+ depends on UART3_ENABLE
+ default 115200 if UART3_BAUD_115200
+ default 57600 if UART3_BAUD_57600
+ default 38400 if UART3_BAUD_38400
+ default 19200 if UART3_BAUD_19200
+ default 9600 if UART3_BAUD_9600
+# end of UART3
+
+# Begin of UART4
+config UART4_ENABLE
+ bool "UART4 Enable"
+ default y
+
+choice
+ prompt "UART4 I/O port"
+ default UART4_IO_PORT_2E8
+ depends on UART4_ENABLE
+
+config UART4_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART4_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART4_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART4_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART4_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART4_IO_PORT_OTHER_INPUT
+ hex "UART4 I/O port"
+ depends on UART4_ENABLE && UART4_IO_PORT_OTHER
+
+config UART4_IO
+ hex
+ depends on UART4_ENABLE
+ default 0x3f8 if UART4_IO_PORT_3F8
+ default 0x2f8 if UART4_IO_PORT_2F8
+ default 0x3e8 if UART4_IO_PORT_3E8
+ default 0x2e8 if UART4_IO_PORT_2E8
+ default UART4_IO_PORT_OTHER_INPUT if UART4_IO_PORT_OTHER
+
+choice
+ prompt "UART4 IRQ"
+ default UART4_IRQ11
+ depends on UART4_ENABLE
+
+config UART4_IRQ_DISABLE
+ bool "Disable"
+config UART4_IRQ3
+ bool "IRQ3, COM2"
+config UART4_IRQ4
+ bool "IRQ4, COM1"
+config UART4_IRQ5
+ bool "IRQ5"
+config UART4_IRQ6
+ bool "IRQ6"
+config UART4_IRQ7
+ bool "IRQ7"
+config UART4_IRQ9
+ bool "IRQ9"
+config UART4_IRQ10
+ bool "IRQ10, COM3"
+config UART4_IRQ11
+ bool "IRQ11, COM4"
+config UART4_IRQ12
+ bool "IRQ12"
+config UART4_IRQ14
+ bool "IRQ14"
+config UART4_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART4_IRQ
+ int
+ depends on UART4_ENABLE
+ default 0 if UART4_IRQ_DISABLE
+ default 3 if UART4_IRQ3
+ default 4 if UART4_IRQ4
+ default 5 if UART4_IRQ5
+ default 6 if UART4_IRQ6
+ default 7 if UART4_IRQ7
+ default 9 if UART4_IRQ9
+ default 10 if UART4_IRQ10
+ default 11 if UART4_IRQ11
+ default 12 if UART4_IRQ12
+ default 14 if UART4_IRQ14
+ default 15 if UART4_IRQ15
+
+choice
+ prompt "UART4 Baud rate"
+ default UART4_BAUD_115200
+ depends on UART4_ENABLE
+
+config UART4_BAUD_115200
+ bool "115200"
+config UART4_BAUD_57600
+ bool "57600"
+config UART4_BAUD_38400
+ bool "38400"
+config UART4_BAUD_19200
+ bool "19200"
+config UART4_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART4_BAUD
+ int
+ depends on UART4_ENABLE
+ default 115200 if UART4_BAUD_115200
+ default 57600 if UART4_BAUD_57600
+ default 38400 if UART4_BAUD_38400
+ default 19200 if UART4_BAUD_19200
+ default 9600 if UART4_BAUD_9600
+# end of UART4
+
+# Begin of UART5
+config UART5_ENABLE
+ bool "UART5 Enable"
+ default n
+
+choice
+ prompt "UART5 I/O port"
+ default UART5_IO_PORT_OTHER
+ depends on UART5_ENABLE
+
+config UART5_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART5_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART5_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART5_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART5_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART5_IO_PORT_OTHER_INPUT
+ hex "UART5 I/O port"
+ depends on UART5_ENABLE && UART5_IO_PORT_OTHER
+
+config UART5_IO
+ hex
+ depends on UART5_ENABLE
+ default 0x3f8 if UART5_IO_PORT_3F8
+ default 0x2f8 if UART5_IO_PORT_2F8
+ default 0x3e8 if UART5_IO_PORT_3E8
+ default 0x2e8 if UART5_IO_PORT_2E8
+ default UART5_IO_PORT_OTHER_INPUT if UART5_IO_PORT_OTHER
+
+choice
+ prompt "UART5 IRQ"
+ default UART5_IRQ_DISABLE
+ depends on UART5_ENABLE
+
+config UART5_IRQ_DISABLE
+ bool "Disable"
+config UART5_IRQ3
+ bool "IRQ3, COM2"
+config UART5_IRQ4
+ bool "IRQ4, COM1"
+config UART5_IRQ5
+ bool "IRQ5"
+config UART5_IRQ6
+ bool "IRQ6"
+config UART5_IRQ7
+ bool "IRQ7"
+config UART5_IRQ9
+ bool "IRQ9"
+config UART5_IRQ10
+ bool "IRQ10, COM3"
+config UART5_IRQ11
+ bool "IRQ11, COM4"
+config UART5_IRQ12
+ bool "IRQ12"
+config UART5_IRQ14
+ bool "IRQ14"
+config UART5_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART5_IRQ
+ int
+ depends on UART5_ENABLE
+ default 0 if UART5_IRQ_DISABLE
+ default 3 if UART5_IRQ3
+ default 4 if UART5_IRQ4
+ default 5 if UART5_IRQ5
+ default 6 if UART5_IRQ6
+ default 7 if UART5_IRQ7
+ default 9 if UART5_IRQ9
+ default 10 if UART5_IRQ10
+ default 11 if UART5_IRQ11
+ default 12 if UART5_IRQ12
+ default 14 if UART5_IRQ14
+ default 15 if UART5_IRQ15
+
+choice
+ prompt "UART5 Baud rate"
+ default UART5_BAUD_115200
+ depends on UART5_ENABLE
+
+config UART5_BAUD_115200
+ bool "115200"
+config UART5_BAUD_57600
+ bool "57600"
+config UART5_BAUD_38400
+ bool "38400"
+config UART5_BAUD_19200
+ bool "19200"
+config UART5_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART5_BAUD
+ int
+ depends on UART5_ENABLE
+ default 115200 if UART5_BAUD_115200
+ default 57600 if UART5_BAUD_57600
+ default 38400 if UART5_BAUD_38400
+ default 19200 if UART5_BAUD_19200
+ default 9600 if UART5_BAUD_9600
+# end of UART5
+
+# Begin of UART6
+config UART6_ENABLE
+ bool "UART6 Enable"
+ default n
+
+choice
+ prompt "UART6 I/O port"
+ default UART6_IO_PORT_OTHER
+ depends on UART6_ENABLE
+
+config UART6_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART6_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART6_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART6_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART6_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART6_IO_PORT_OTHER_INPUT
+ hex "UART6 I/O port"
+ depends on UART6_ENABLE && UART6_IO_PORT_OTHER
+
+config UART6_IO
+ hex
+ depends on UART6_ENABLE
+ default 0x3f8 if UART6_IO_PORT_3F8
+ default 0x2f8 if UART6_IO_PORT_2F8
+ default 0x3e8 if UART6_IO_PORT_3E8
+ default 0x2e8 if UART6_IO_PORT_2E8
+ default UART6_IO_PORT_OTHER_INPUT if UART6_IO_PORT_OTHER
+
+choice
+ prompt "UART6 IRQ"
+ default UART6_IRQ_DISABLE
+ depends on UART6_ENABLE
+
+config UART6_IRQ_DISABLE
+ bool "Disable"
+config UART6_IRQ3
+ bool "IRQ3, COM2"
+config UART6_IRQ4
+ bool "IRQ4, COM1"
+config UART6_IRQ5
+ bool "IRQ5"
+config UART6_IRQ6
+ bool "IRQ6"
+config UART6_IRQ7
+ bool "IRQ7"
+config UART6_IRQ9
+ bool "IRQ9"
+config UART6_IRQ10
+ bool "IRQ10, COM3"
+config UART6_IRQ11
+ bool "IRQ11, COM4"
+config UART6_IRQ12
+ bool "IRQ12"
+config UART6_IRQ14
+ bool "IRQ14"
+config UART6_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART6_IRQ
+ int
+ depends on UART6_ENABLE
+ default 0 if UART6_IRQ_DISABLE
+ default 3 if UART6_IRQ3
+ default 4 if UART6_IRQ4
+ default 5 if UART6_IRQ5
+ default 6 if UART6_IRQ6
+ default 7 if UART6_IRQ7
+ default 9 if UART6_IRQ9
+ default 10 if UART6_IRQ10
+ default 11 if UART6_IRQ11
+ default 12 if UART6_IRQ12
+ default 14 if UART6_IRQ14
+ default 15 if UART6_IRQ15
+
+choice
+ prompt "UART6 Baud rate"
+ default UART6_BAUD_115200
+ depends on UART6_ENABLE
+
+config UART6_BAUD_115200
+ bool "115200"
+config UART6_BAUD_57600
+ bool "57600"
+config UART6_BAUD_38400
+ bool "38400"
+config UART6_BAUD_19200
+ bool "19200"
+config UART6_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART6_BAUD
+ int
+ depends on UART6_ENABLE
+ default 115200 if UART6_BAUD_115200
+ default 57600 if UART6_BAUD_57600
+ default 38400 if UART6_BAUD_38400
+ default 19200 if UART6_BAUD_19200
+ default 9600 if UART6_BAUD_9600
+# end of UART6
+
+# Begin of UART7
+config UART7_ENABLE
+ bool "UART7 Enable"
+ default n
+
+choice
+ prompt "UART7 I/O port"
+ default UART7_IO_PORT_OTHER
+ depends on UART7_ENABLE
+
+config UART7_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART7_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART7_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART7_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART7_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART7_IO_PORT_OTHER_INPUT
+ hex "UART7 I/O port"
+ depends on UART7_ENABLE && UART7_IO_PORT_OTHER
+
+config UART7_IO
+ hex
+ depends on UART7_ENABLE
+ default 0x3f8 if UART7_IO_PORT_3F8
+ default 0x2f8 if UART7_IO_PORT_2F8
+ default 0x3e8 if UART7_IO_PORT_3E8
+ default 0x2e8 if UART7_IO_PORT_2E8
+ default UART7_IO_PORT_OTHER_INPUT if UART7_IO_PORT_OTHER
+
+choice
+ prompt "UART7 IRQ"
+ default UART7_IRQ_DISABLE
+ depends on UART7_ENABLE
+
+config UART7_IRQ_DISABLE
+ bool "Disable"
+config UART7_IRQ3
+ bool "IRQ3, COM2"
+config UART7_IRQ4
+ bool "IRQ4, COM1"
+config UART7_IRQ5
+ bool "IRQ5"
+config UART7_IRQ6
+ bool "IRQ6"
+config UART7_IRQ7
+ bool "IRQ7"
+config UART7_IRQ9
+ bool "IRQ9"
+config UART7_IRQ10
+ bool "IRQ10, COM3"
+config UART7_IRQ11
+ bool "IRQ11, COM4"
+config UART7_IRQ12
+ bool "IRQ12"
+config UART7_IRQ14
+ bool "IRQ14"
+config UART7_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART7_IRQ
+ int
+ depends on UART7_ENABLE
+ default 0 if UART7_IRQ_DISABLE
+ default 3 if UART7_IRQ3
+ default 4 if UART7_IRQ4
+ default 5 if UART7_IRQ5
+ default 6 if UART7_IRQ6
+ default 7 if UART7_IRQ7
+ default 9 if UART7_IRQ9
+ default 10 if UART7_IRQ10
+ default 11 if UART7_IRQ11
+ default 12 if UART7_IRQ12
+ default 14 if UART7_IRQ14
+ default 15 if UART7_IRQ15
+
+choice
+ prompt "UART7 Baud rate"
+ default UART7_BAUD_115200
+ depends on UART7_ENABLE
+
+config UART7_BAUD_115200
+ bool "115200"
+config UART7_BAUD_57600
+ bool "57600"
+config UART7_BAUD_38400
+ bool "38400"
+config UART7_BAUD_19200
+ bool "19200"
+config UART7_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART7_BAUD
+ int
+ depends on UART7_ENABLE
+ default 115200 if UART7_BAUD_115200
+ default 57600 if UART7_BAUD_57600
+ default 38400 if UART7_BAUD_38400
+ default 19200 if UART7_BAUD_19200
+ default 9600 if UART7_BAUD_9600
+# end of UART7
+
+# Begin of UART8
+config UART8_ENABLE
+ bool "UART8 Enable"
+ default n
+
+choice
+ prompt "UART8 I/O port"
+ default UART8_IO_PORT_OTHER
+ depends on UART8_ENABLE
+
+config UART8_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART8_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART8_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART8_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART8_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART8_IO_PORT_OTHER_INPUT
+ hex "UART8 I/O port"
+ depends on UART8_ENABLE && UART8_IO_PORT_OTHER
+
+config UART8_IO
+ hex
+ depends on UART8_ENABLE
+ default 0x3f8 if UART8_IO_PORT_3F8
+ default 0x2f8 if UART8_IO_PORT_2F8
+ default 0x3e8 if UART8_IO_PORT_3E8
+ default 0x2e8 if UART8_IO_PORT_2E8
+ default UART8_IO_PORT_OTHER_INPUT if UART8_IO_PORT_OTHER
+
+choice
+ prompt "UART8 IRQ"
+ default UART8_IRQ_DISABLE
+ depends on UART8_ENABLE
+
+config UART8_IRQ_DISABLE
+ bool "Disable"
+config UART8_IRQ3
+ bool "IRQ3, COM2"
+config UART8_IRQ4
+ bool "IRQ4, COM1"
+config UART8_IRQ5
+ bool "IRQ5"
+config UART8_IRQ6
+ bool "IRQ6"
+config UART8_IRQ7
+ bool "IRQ7"
+config UART8_IRQ9
+ bool "IRQ9"
+config UART8_IRQ10
+ bool "IRQ10, COM3"
+config UART8_IRQ11
+ bool "IRQ11, COM4"
+config UART8_IRQ12
+ bool "IRQ12"
+config UART8_IRQ14
+ bool "IRQ14"
+config UART8_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART8_IRQ
+ int
+ depends on UART8_ENABLE
+ default 0 if UART8_IRQ_DISABLE
+ default 3 if UART8_IRQ3
+ default 4 if UART8_IRQ4
+ default 5 if UART8_IRQ5
+ default 6 if UART8_IRQ6
+ default 7 if UART8_IRQ7
+ default 9 if UART8_IRQ9
+ default 10 if UART8_IRQ10
+ default 11 if UART8_IRQ11
+ default 12 if UART8_IRQ12
+ default 14 if UART8_IRQ14
+ default 15 if UART8_IRQ15
+
+choice
+ prompt "UART8 Baud rate"
+ default UART8_BAUD_115200
+ depends on UART8_ENABLE
+
+config UART8_BAUD_115200
+ bool "115200"
+config UART8_BAUD_57600
+ bool "57600"
+config UART8_BAUD_38400
+ bool "38400"
+config UART8_BAUD_19200
+ bool "19200"
+config UART8_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART8_BAUD
+ int
+ depends on UART8_ENABLE
+ default 115200 if UART8_BAUD_115200
+ default 57600 if UART8_BAUD_57600
+ default 38400 if UART8_BAUD_38400
+ default 19200 if UART8_BAUD_19200
+ default 9600 if UART8_BAUD_9600
+# end of UART8
+
+# Begin of UART9
+config UART9_ENABLE
+ bool "UART9 Enable"
+ default n
+
+choice
+ prompt "UART9 I/O port"
+ default UART9_IO_PORT_OTHER
+ depends on UART9_ENABLE
+
+config UART9_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART9_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART9_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART9_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART9_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART9_IO_PORT_OTHER_INPUT
+ hex "UART9 I/O port"
+ depends on UART9_ENABLE && UART9_IO_PORT_OTHER
+
+config UART9_IO
+ hex
+ depends on UART9_ENABLE
+ default 0x3f8 if UART9_IO_PORT_3F8
+ default 0x2f8 if UART9_IO_PORT_2F8
+ default 0x3e8 if UART9_IO_PORT_3E8
+ default 0x2e8 if UART9_IO_PORT_2E8
+ default UART9_IO_PORT_OTHER_INPUT if UART9_IO_PORT_OTHER
+
+choice
+ prompt "UART9 IRQ"
+ default UART9_IRQ_DISABLE
+ depends on UART9_ENABLE
+
+config UART9_IRQ_DISABLE
+ bool "Disable"
+config UART9_IRQ3
+ bool "IRQ3, COM2"
+config UART9_IRQ4
+ bool "IRQ4, COM1"
+config UART9_IRQ5
+ bool "IRQ5"
+config UART9_IRQ6
+ bool "IRQ6"
+config UART9_IRQ7
+ bool "IRQ7"
+config UART9_IRQ9
+ bool "IRQ9"
+config UART9_IRQ10
+ bool "IRQ10, COM3"
+config UART9_IRQ11
+ bool "IRQ11, COM4"
+config UART9_IRQ12
+ bool "IRQ12"
+config UART9_IRQ14
+ bool "IRQ14"
+config UART9_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART9_IRQ
+ int
+ depends on UART9_ENABLE
+ default 0 if UART9_IRQ_DISABLE
+ default 3 if UART9_IRQ3
+ default 4 if UART9_IRQ4
+ default 5 if UART9_IRQ5
+ default 6 if UART9_IRQ6
+ default 7 if UART9_IRQ7
+ default 9 if UART9_IRQ9
+ default 10 if UART9_IRQ10
+ default 11 if UART9_IRQ11
+ default 12 if UART9_IRQ12
+ default 14 if UART9_IRQ14
+ default 15 if UART9_IRQ15
+
+choice
+ prompt "UART9 Baud rate"
+ default UART9_BAUD_115200
+ depends on UART9_ENABLE
+
+config UART9_BAUD_115200
+ bool "115200"
+config UART9_BAUD_57600
+ bool "57600"
+config UART9_BAUD_38400
+ bool "38400"
+config UART9_BAUD_19200
+ bool "19200"
+config UART9_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART9_BAUD
+ int
+ depends on UART9_ENABLE
+ default 115200 if UART9_BAUD_115200
+ default 57600 if UART9_BAUD_57600
+ default 38400 if UART9_BAUD_38400
+ default 19200 if UART9_BAUD_19200
+ default 9600 if UART9_BAUD_9600
+# end of UART9
+
+# Begin of UART10
+config UART10_ENABLE
+ bool "UART10 Enable"
+ default n
+
+choice
+ prompt "UART10 I/O port"
+ default UART10_IO_PORT_OTHER
+ depends on UART10_ENABLE
+
+config UART10_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART10_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART10_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART10_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART10_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART10_IO_PORT_OTHER_INPUT
+ hex "UART10 I/O port"
+ depends on UART10_ENABLE && UART10_IO_PORT_OTHER
+
+config UART10_IO
+ hex
+ depends on UART10_ENABLE
+ default 0x3f8 if UART10_IO_PORT_3F8
+ default 0x2f8 if UART10_IO_PORT_2F8
+ default 0x3e8 if UART10_IO_PORT_3E8
+ default 0x2e8 if UART10_IO_PORT_2E8
+ default UART10_IO_PORT_OTHER_INPUT if UART10_IO_PORT_OTHER
+
+choice
+ prompt "UART10 IRQ"
+ default UART10_IRQ_DISABLE
+ depends on UART10_ENABLE
+
+config UART10_IRQ_DISABLE
+ bool "Disable"
+config UART10_IRQ3
+ bool "IRQ3, COM2"
+config UART10_IRQ4
+ bool "IRQ4, COM1"
+config UART10_IRQ5
+ bool "IRQ5"
+config UART10_IRQ6
+ bool "IRQ6"
+config UART10_IRQ7
+ bool "IRQ7"
+config UART10_IRQ9
+ bool "IRQ9"
+config UART10_IRQ10
+ bool "IRQ10, COM3"
+config UART10_IRQ11
+ bool "IRQ11, COM4"
+config UART10_IRQ12
+ bool "IRQ12"
+config UART10_IRQ14
+ bool "IRQ14"
+config UART10_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART10_IRQ
+ int
+ depends on UART10_ENABLE
+ default 0 if UART10_IRQ_DISABLE
+ default 3 if UART10_IRQ3
+ default 4 if UART10_IRQ4
+ default 5 if UART10_IRQ5
+ default 6 if UART10_IRQ6
+ default 7 if UART10_IRQ7
+ default 9 if UART10_IRQ9
+ default 10 if UART10_IRQ10
+ default 11 if UART10_IRQ11
+ default 12 if UART10_IRQ12
+ default 14 if UART10_IRQ14
+ default 15 if UART10_IRQ15
+
+choice
+ prompt "UART10 Baud rate"
+ default UART10_BAUD_115200
+ depends on UART10_ENABLE
+
+config UART10_BAUD_115200
+ bool "115200"
+config UART10_BAUD_57600
+ bool "57600"
+config UART10_BAUD_38400
+ bool "38400"
+config UART10_BAUD_19200
+ bool "19200"
+config UART10_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART10_BAUD
+ int
+ depends on UART10_ENABLE
+ default 115200 if UART10_BAUD_115200
+ default 57600 if UART10_BAUD_57600
+ default 38400 if UART10_BAUD_38400
+ default 19200 if UART10_BAUD_19200
+ default 9600 if UART10_BAUD_9600
+# end of UART10
+
+endmenu
+
+# LPT setting :
+menu "LPT setting"
+
+# Begin of LPT
+config LPT_ENABLE
+ bool "LPT Enable"
+ default n
+
+choice
+ prompt "LPT I/O port"
+ default LPT_IO_PORT_278
+ depends on LPT_ENABLE
+
+config LPT_IO_PORT_378
+ bool "0x378, LPT1"
+config LPT_IO_PORT_278
+ bool "0x278, LPT2"
+config LPT_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config LPT_IO_PORT_OTHER_INPUT
+ hex "LPT I/O port"
+ depends on LPT_ENABLE && LPT_IO_PORT_OTHER
+
+config LPT_IO
+ hex
+ depends on LPT_ENABLE
+ default 0x378 if LPT_IO_PORT_378
+ default 0x278 if LPT_IO_PORT_278
+ default LPT_IO_PORT_OTHER_INPUT if LPT_IO_PORT_OTHER
+
+choice
+ prompt "LPT IRQ"
+ default LPT_IRQ_DISABLE
+ depends on LPT_ENABLE
+
+config LPT_IRQ_DISABLE
+ bool "Disable"
+config LPT_IRQ3
+ bool "IRQ3"
+config LPT_IRQ4
+ bool "IRQ4"
+config LPT_IRQ5
+ bool "IRQ5"
+config LPT_IRQ6
+ bool "IRQ6"
+config LPT_IRQ7
+ bool "IRQ7"
+config LPT_IRQ9
+ bool "IRQ9"
+config LPT_IRQ10
+ bool "IRQ10"
+config LPT_IRQ11
+ bool "IRQ11"
+config LPT_IRQ12
+ bool "IRQ12"
+config LPT_IRQ14
+ bool "IRQ14"
+config LPT_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config LPT_IRQ
+ int
+ depends on LPT_ENABLE
+ default 0 if LPT_IRQ_DISABLE
+ default 3 if LPT_IRQ3
+ default 4 if LPT_IRQ4
+ default 5 if LPT_IRQ5
+ default 6 if LPT_IRQ6
+ default 7 if LPT_IRQ7
+ default 9 if LPT_IRQ9
+ default 10 if LPT_IRQ10
+ default 11 if LPT_IRQ11
+ default 12 if LPT_IRQ12
+ default 14 if LPT_IRQ14
+ default 15 if LPT_IRQ15
+
+choice
+ prompt "LPT Mode Setting"
+ default LPT_MODE_SPP
+ depends on LPT_ENABLE
+
+config LPT_MODE_BPP
+ bool "BPP mode"
+config LPT_MODE_EPP_19_AND_SPP
+ bool "EPP 1.9 and SPP mode"
+config LPT_MODE_ECP
+ bool "ECP Mode"
+config LPT_MODE_ECP_AND_EPP_19
+ bool "ECP and EPP 1.9 mode"
+config LPT_MODE_SPP
+ bool "SPP Mode"
+config LPT_MODE_EPP_17_AND_SPP
+ bool "EPP 1.7 and SPP mode"
+config LPT_MODE_ECP_AND_EPP_17
+ bool "ECP and EPP 1.7 mode"
+
+endchoice
+
+# end of LPT
+
+endmenu
+
+endif # BOARD_DMP_EX
diff --git a/src/mainboard/dmp/vortex86ex/devicetree.cb b/src/mainboard/dmp/vortex86ex/devicetree.cb
new file mode 100644
index 0000000..1fbfe7b
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/devicetree.cb
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip northbridge/dmp/vortex86ex # North Bridge
+ device domain 0 on
+ device pci 0.0 on end # Host Bridge
+ chip southbridge/dmp/vortex86ex # South Bridge
+ device pci 7.0 on end # ISA Bridge
+ device pci 8.0 on end # Ethernet
+ device pci a.0 on end # USB 1.1
+ device pci a.1 on end # USB 2.0
+ device pci b.0 on end # USB 1.1
+ device pci b.1 on end # USB 2.0
+ device pci c.0 on end # IDE
+ end
+ end # pci domain 0
+ chip cpu/dmp/vortex86ex end # CPU
+end
diff --git a/src/mainboard/dmp/vortex86ex/irq_tables.c b/src/mainboard/dmp/vortex86ex/irq_tables.c
new file mode 100644
index 0000000..c185c4f
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/irq_tables.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 12, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x07 << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x17f3, /* Vendor */
+ 0x6031, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xa, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x1, 0x0},
+ {0x00, (0x02 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0},
+ {0x00, (0x03 << 3) | 0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x0, 0x0},
+ {0x00, (0x04 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}}, 0x4, 0x0},
+ {0x00, (0x05 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x5, 0x0},
+ {0x00, (0x06 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x6, 0x0},
+ {0x00, (0x08 << 3) | 0x0, {{0x05, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x0a << 3) | 0x0, {{0x07, 0xdef8}, {0x08, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x0b << 3) | 0x0, {{0x09, 0xdef8}, {0x0a, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x0c << 3) | 0x0, {{0x0b, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x0f << 3) | 0x0, {{0x0d, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x0e << 3) | 0x0, {{0x0e, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c
new file mode 100644
index 0000000..dfeb5f4
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/mainboard.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <device/pci_def.h>
+
+static void mainboard_enable(device_t dev)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("DMP VORTEX86EX Mainboard")
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c
new file mode 100644
index 0000000..72fbde0
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/romstage.c
@@ -0,0 +1,360 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Andrew Wu <arw(a)dmp.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "drivers/pc80/i8254.c"
+#include "northbridge/dmp/vortex86ex/northbridge.h"
+#include "southbridge/dmp/vortex86ex/southbridge.h"
+#include "northbridge/dmp/vortex86ex/raminit.c"
+
+#define DMP_CPUID_SX 0x31504d44
+#define DMP_CPUID_DX 0x32504d44
+#define DMP_CPUID_MX 0x33504d44
+#define DMP_CPUID_DX2 0x34504d44
+#define DMP_CPUID_MX_PLUS 0x35504d44
+#define DMP_CPUID_EX 0x37504d44
+
+/* Post codes */
+#define POST_DMP_ID_ERR 0x85
+#define POST_DRAM_TEST_ERR 0x86
+#define POST_DRAM_SIZING_ERR 0x77
+
+static u32 get_dmp_id(void)
+{
+ return pci_read_config32(NB, NB_REG_CID);
+}
+
+/* Indirect access registers for Watch-dog timer, GPIO PORT 0,1
+ * Index port is for I/O port 22h
+ * Index port 13h (00: lock register, C5h: unlock register) for lock/unlock function
+ * Index port 37h, 39h, 3Ah, 3Bh, 3Ch for Watchdog timer
+ * Index port 46h, 47h, 4Ch, 4Dh, 4Eh, 4Fh for GPIO port 0, 1
+ */
+static void write_indirect_reg(u8 index, u8 data)
+{
+ outb(index, 0x22);
+ outb(data, 0x23);
+}
+
+static void lock_indirect_reg(void)
+{
+ write_indirect_reg(0x13, 0x00);
+}
+
+static void unlock_indirect_reg(void)
+{
+ write_indirect_reg(0x13, 0xc5);
+}
+
+static void disable_watchdog(void)
+{
+ unlock_indirect_reg();
+ // disable watchdog timer
+ write_indirect_reg(0x37, 0x0);
+}
+
+void set_ex_powerdown_control(void)
+{
+ u32 powerdown_ctrl;
+ powerdown_ctrl = pci_read_config32(SB, 0xbc);
+#if CONFIG_TEMP_POWERDOWN
+ powerdown_ctrl |= (1 << 31);
+#endif
+#if CONFIG_SATA_POWERDOWN
+ powerdown_ctrl |= (1 << 30);
+#endif
+#if CONFIG_ADC_POWERDOWN
+ powerdown_ctrl |= (1 << 28);
+#endif
+#if CONFIG_PCIE0_POWERDOWN
+ powerdown_ctrl |= (1 << 13);
+#endif
+#if CONFIG_MAC_POWERDOWN
+ powerdown_ctrl |= (1 << 3);
+#endif
+#if CONFIG_USB1_POWERDOWN
+ powerdown_ctrl |= (1 << 1);
+#endif
+#if CONFIG_IDE_POWERDOWN
+ powerdown_ctrl |= (1 << 0);
+#endif
+ pci_write_config32(SB, 0xbc, powerdown_ctrl);
+}
+
+static void set_pci_nb_pmcr(void)
+{
+ u8 pmcr = pci_read_config8(NB, NB_REG_PMCR);
+ /*
+ * Set PCI Master Max Cycle Length (MCL) to 32 PCI clocks.
+ * Set PCI Master Burst Write Length (BL) to Burst length over 3.
+ */
+ pmcr |= 0x0f;
+ pci_write_config8(NB, NB_REG_PMCR, pmcr);
+}
+
+static void set_pci_sb_lpccr(void)
+{
+ u8 lpccr = pci_read_config8(SB, SB_REG_LPCCR);
+ /* Set PCI Soft Reset Control to 1.
+ * (When the CPU soft reset is initialized, PCIRST# will be active.)
+ * Set P92FE to 1. (I/O port 92 Register Write Function Enable.)
+ * Set P92S to 1. (Internal Port 92h Selected.)
+ */
+ lpccr |= 0x16;
+ pci_write_config8(SB, SB_REG_LPCCR, lpccr);
+ /* enable fast ga20 */
+ outb(inb(SYSTEM_CTL_PORT) | 0x02, SYSTEM_CTL_PORT);
+}
+
+static u32 make_uart_config(u16 base, u8 irq)
+{
+ /* Set base IO address only, skip IRQ. IRQ will be setup in
+ * southbridge stage. */
+ u32 cfg = 0;
+ cfg |= 1 << 23; // UE = enabled.
+ cfg |= base; // UIOA.
+ return cfg;
+}
+
+#define SETUP_UART(n) \
+ uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\
+ outl(uart_cfg, 0xc00 + (n - 1) * 4);
+
+static void ex_uart_early_init(void)
+{
+#if CONFIG_TTYS0_BASE
+ u32 uart_cfg = 0;
+ /* Set UART Config I/O base address to 0xc00 */
+ pci_write_config16(SB, 0x60, 0xc01);
+ /* If serial console base address is defined, find out which
+ * UART uses this address, and setup this UART first. */
+#if CONFIG_TTYS0_BASE == CONFIG_UART1_IO
+ SETUP_UART(1)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART2_IO
+ SETUP_UART(2)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART3_IO
+ SETUP_UART(3)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART4_IO
+ SETUP_UART(4)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART5_IO
+ SETUP_UART(5)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART6_IO
+ SETUP_UART(6)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART7_IO
+ SETUP_UART(7)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART8_IO
+ SETUP_UART(8)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART9_IO
+ SETUP_UART(9)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART10_IO
+ SETUP_UART(10)
+#endif
+#endif
+}
+
+static void init_wdt1(void)
+{
+#if CONFIG_WDT1_INITIALIZE
+#if CONFIG_WDT1_ENABLE
+ outb(0x1 << 6, 0xa8);
+#endif
+ u8 wdt1_signal_reg = 0;
+#if CONFIG_WDT1_SINGAL_NMI
+ wdt1_signal_reg = 0x0c << 4;
+#elif CONFIG_WDT1_SIGNAL_RESET
+ wdt1_signal_reg = 0x0d << 4;
+#elif CONFIG_WDT1_SIGNAL_SMI
+ wdt1_signal_reg = 0x0e << 4;
+#endif
+ outb(wdt1_signal_reg, 0xa9);
+#endif
+}
+
+/* Fill 32bit pattern into specified DRAM region. */
+static void fill_dram(u32 * p, u32 pattern, u32 test_len)
+{
+ if (test_len == 0)
+ return;
+#if 0
+ // C version, very slow.
+ for (p = (u32 *) 0; (u32) p < test_len; p++) {
+ *p = pattern;
+ }
+#endif
+ // ASM version, much faster.
+ asm volatile (
+ "cld\n\t"
+ "rep\n\t"
+ "stosl"
+ : /* no output registers */
+ : "c" (test_len / 4), "a" (pattern), "D" (p)
+ );
+}
+
+/* Verify 32bit pattern in specified DRAM region.
+ * Return -1 if ok, failed memory address if error. */
+static int verify_dram(u32 * p, u32 pattern, u32 test_len)
+{
+ if (test_len == 0)
+ return -1;
+#if 0
+ // C version, very slow.
+ for (p = (u32 *) 0; (u32) p < test_len; p++) {
+ if (*p != pattern) {
+ return (int)p;
+ }
+ }
+ return -1;
+#endif
+ u16 flags;
+ int addr;
+ asm volatile (
+ "cld\n\t"
+ "rep\n\t"
+ "scasl\n\t"
+ "lahf\n\t"
+ : "=a" (flags), "=D" (addr)
+ : "c" (test_len / 4), "a" (pattern), "D" (p)
+ );
+ if (flags & (1 << (6 + 8))) // x86 zero flag = bit 6.
+ {
+ return -1; // verify ok
+ }
+ return addr - 4; // verify error, return error address.
+}
+
+static void test_dram_stability(void)
+{
+ u32 test_len = 2048 * 1024;
+ u32 pat = 0x5aa5a55a;
+ u32 ext_mem_start = 0xc0000;
+ u32 base_mem_test_len = test_len > 640 * 1024 ? 640 * 1024 : test_len;
+ u32 ext_mem_test_len = test_len > ext_mem_start ? test_len - ext_mem_start : 0;
+ if (ext_mem_test_len > 0) {
+ /* Enable all shadow RAM region C0000 - FFFFF. */
+ pci_write_config32(NB, NB_REG_MAR, 0x3ffffff0);
+ }
+ int v;
+ fill_dram((u32 *) 0, pat, base_mem_test_len);
+ fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
+ v = verify_dram((u32 *) 0, pat, base_mem_test_len);
+ if (v == -1) {
+ v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
+ }
+ /* Change pattern and test again */
+ if (v == -1) {
+ pat = 0xa55a5aa5;
+ fill_dram((u32 *) 0, pat, base_mem_test_len);
+ fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
+ v = verify_dram((u32 *) 0, pat, base_mem_test_len);
+ if (v == -1) {
+ v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
+ }
+ }
+ if (v != -1) {
+ post_code(POST_DRAM_TEST_ERR);
+ print_emerg("DRAM stablility test error!\nADDR = ");
+ print_emerg_hex32(v);
+ print_emerg(", WRITE = ");
+ print_emerg_hex32(pat);
+ u32 r = *(u32 *) v;
+ print_emerg(", READ = ");
+ print_emerg_hex32(r);
+ print_emerg(", XOR = ");
+ print_emerg_hex32(r ^ pat);
+ print_emerg("\n");
+ die("System halted.\n");
+ }
+ if (ext_mem_test_len > 0) {
+ /* Disable shadow RAM. */
+ pci_write_config32(NB, NB_REG_MAR, 0x0);
+ }
+}
+
+static void enable_l2_cache(void)
+{
+ /*
+ * Enable L2 cache by setting PCI N/B function 1 L2 cache
+ * control register (0xe8) bit 0 (L2_EN) and bit 1 (L2_WB_EN).
+ */
+ u32 reg_nb_f1_e8;
+ reg_nb_f1_e8 = pci_read_config8(NB1, 0xe8);
+ reg_nb_f1_e8 |= 3;
+ pci_write_config8(NB1, 0xe8, reg_nb_f1_e8);
+}
+
+static void main(unsigned long bist)
+{
+ device_t dev;
+ u32 dmp_id;
+
+ dmp_id = get_dmp_id();
+ if (dmp_id != DMP_CPUID_EX) {
+ /* Not DMP Vortex86EX CPU. */
+ post_code(POST_DMP_ID_ERR);
+ while (1)
+ hlt();
+ }
+ disable_watchdog();
+ set_ex_powerdown_control();
+ set_pci_nb_pmcr();
+ set_pci_sb_lpccr();
+ ex_uart_early_init();
+
+ console_init();
+
+ init_wdt1();
+
+ /* Initialize i8254 timers */
+ post_code(0x42);
+ setup_i8254();
+
+ /* Initialize DRAM */
+ u8 reg_nb_f1_cc;
+ /* Setup DDR3 Timing reg 0-3 / Config reg */
+ pci_write_config16(NB, 0x6e, 0x0a2f);
+ pci_write_config32(NB, 0x74, 0x84010200);
+ pci_write_config32(NB, 0x78, 0x33405544);
+ pci_write_config32(NB, 0x7c, 0x2e0f0e0b);
+ /* Disable enhance read push write */
+ reg_nb_f1_cc = pci_read_config8(NB1, 0xcc);
+ reg_nb_f1_cc &= ~(1 << 4);
+ pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);
+ if (detect_ddr3_dram_size()) {
+ post_code(POST_DRAM_SIZING_ERR);
+ die("DRAM sizing error!\n");
+ }
+ /* Reset enhance read push write to default(enable) */
+ reg_nb_f1_cc |= (1 << 4);
+ pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);
+
+ print_ddr3_memory_setup();
+ test_dram_stability();
+
+ /* CPU setup, romcc pukes on invd() */
+ asm volatile ("invd");
+ enable_cache();
+
+ enable_l2_cache();
+}
1
0
Patch set updated for coreboot: bac86cc w83627hf/acpi: Fix logical device power down in ACPI
by Christoph Grenz 04 Jul '13
by Christoph Grenz 04 Jul '13
04 Jul '13
Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3605
-gerrit
commit bac86cc8efa272e1b4a121919c82b04545267b15
Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
Date: Thu Jul 4 03:41:39 2013 +0200
w83627hf/acpi: Fix logical device power down in ACPI
As Nico noticed for the W83627DHG, the power management bits to power down
individual logical devices on Winbond superios are named counterintuitively
and need to be set when the logical device should be powered.
This corrects the power management methods for the W83627HF.
Change-Id: I98bccd550a0513c62bfa9480275f88c566691bc8
Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
---
src/superio/winbond/w83627hf/acpi/superio.asl | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl
index efb7fba..427d63c 100644
--- a/src/superio/winbond/w83627hf/acpi/superio.asl
+++ b/src/superio/winbond/w83627hf/acpi/superio.asl
@@ -242,13 +242,13 @@ Device(SIO) {
/* Disable power saving mode */
Method (_PS0) {
ENCM (0xFF)
- Store (Zero, FDPW)
+ Store (One, FDPW)
EXCM ()
}
/* Enable power saving mode */
Method (_PS1) {
ENCM (0xFF)
- Store (One, FDPW)
+ Store (Zero, FDPW)
EXCM ()
}
@@ -462,12 +462,12 @@ Device(SIO) {
}
Method (_PS0) {
ENCM (0xFF)
- Store (Zero, PRPW)
+ Store (One, PRPW)
EXCM ()
}
Method (_PS1) {
ENCM (0xFF)
- Store (One, PRPW)
+ Store (Zero, PRPW)
EXCM ()
}
@@ -639,12 +639,12 @@ Device(SIO) {
}
Method (_PS0) {
ENCM (0xFF)
- Store (Zero, UAPW)
+ Store (One, UAPW)
EXCM ()
}
Method (_PS1) {
ENCM (0xFF)
- Store (One, UAPW)
+ Store (Zero, UAPW)
EXCM ()
}
@@ -764,12 +764,12 @@ Device(SIO) {
}
Method (_PS0) {
ENCM (0xFF)
- Store (Zero, UBPW)
+ Store (One, UBPW)
EXCM ()
}
Method (_PS1) {
ENCM (0xFF)
- Store (One, UBPW)
+ Store (Zero, UBPW)
EXCM ()
}
@@ -889,12 +889,12 @@ Device(SIO) {
}
Method (_PS0) {
ENCM (0xFF)
- Store (Zero, UBPW)
+ Store (One, UBPW)
EXCM ()
}
Method (_PS1) {
ENCM (0xFF)
- Store (One, UBPW)
+ Store (Zero, UBPW)
EXCM ()
}
@@ -1414,14 +1414,14 @@ Device(SIO) {
Method (_PS0)
{
ENCM (0xFF)
- Store (Zero, HWPW)
+ Store (One, HWPW)
EXCM ()
}
Method (_PS1)
{
ENCM (0xFF)
- Store (One, HWPW)
+ Store (Zero, HWPW)
EXCM ()
}
1
0