coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ea97c26 Redefine pci_bus_default_ops as function
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3608 -gerrit commit ea97c2681bb3fee96cd1d1304f42db5d7742432b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 4 17:17:45 2013 +0300 Redefine pci_bus_default_ops as function Taking device_t as a parameter, this allows to alter the PCI config access handlers. This is useful to add tracing of PCI config writes for devices having problems to initialise correctly. On older AMD platform PCI MMIO may not be able to fully configure all PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due to its atomic nature. So those can be forced to IO config instead. Change-Id: I2162884185bbfe461b036caf737980b45a51e522 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/pci_ops.h | 15 +------------- src/device/pci_ops.c | 41 ++++++++++++++++++++++++++++--------- src/include/device/device.h | 2 +- src/include/device/pci.h | 12 ----------- 4 files changed, 33 insertions(+), 37 deletions(-) diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index fa29317..35b49c6 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -7,19 +7,6 @@ extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_ops_mmconf; #endif -#if CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_bus_default_ops &pci_ops_mmconf -#else -#define pci_bus_default_ops &pci_cf8_conf1 -#endif - -static inline const struct pci_bus_operations *pci_config_default(void) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return &pci_ops_mmconf; -#else - return &pci_cf8_conf1; -#endif -} +extern const struct pci_bus_operations *pci_bus_default_ops(device_t dev); #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index b0281f4..32eb584 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -25,9 +25,30 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +const struct pci_bus_operations *pci_bus_default_ops(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return &pci_ops_mmconf; +#else + return &pci_cf8_conf1; +#endif +} + +static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, device_t dev) +{ + const struct pci_bus_operations *bops; + bops = 0; + if (bus && bus->dev && bus->dev->ops && bus->dev->ops->ops_pci_bus) { + bops = bus->dev->ops->ops_pci_bus(dev); + } + if (!bops) + bops = pci_bus_default_ops(dev); + return bops; +} + /* - * The only consumer of the return value of get_pbus() is ops_pci_bus(). - * ops_pci_bus() can handle being passed NULL and auto-picks working ops. + * The only consumer of the return value of get_pbus() is pci_bus_ops(). + * pci_bus_ops() can handle being passed NULL and auto-picks working ops. */ static struct bus *get_pbus(device_t dev) { @@ -38,10 +59,10 @@ static struct bus *get_pbus(device_t dev) else pbus = dev->bus; - while (pbus && pbus->dev && !ops_pci_bus(pbus)) { + while (pbus && pbus->dev && !pci_bus_ops(pbus, dev)) { if (pbus == pbus->dev->bus) { printk(BIOS_ALERT, "%s in endless loop looking for a " - "parent bus with ops_pci_bus for %s, breaking " + "parent bus with pci_bus_ops for %s, breaking " "out.\n", __func__, dev_path(dev)); break; } @@ -64,42 +85,42 @@ static struct bus *get_pbus(device_t dev) u8 pci_read_config8(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } u16 pci_read_config16(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } u32 pci_read_config32(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } void pci_write_config8(device_t dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config16(device_t dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config32(device_t dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } diff --git a/src/include/device/device.h b/src/include/device/device.h index 9defb19..1eff4a2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -42,7 +42,7 @@ struct device_operations { #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; - const struct pci_bus_operations *ops_pci_bus; + const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); const struct pnp_mode_ops *ops_pnp_mode; }; #endif diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 1f47daf..2dea1cf 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -94,17 +94,5 @@ static inline const struct pci_operations *ops_pci(device_t dev) return pops; } -static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) -{ - const struct pci_bus_operations *bops; - bops = 0; - if (bus && bus->dev && bus->dev->ops) { - bops = bus->dev->ops->ops_pci_bus; - } - if (!bops) - bops = pci_config_default(); - return bops; -} - #endif #endif /* PCI_H */

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Patch set updated for coreboot: ea31bd3 arch/armv7 devicetree: Drop unnecessary PCI headers
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3622 -gerrit commit ea31bd3b695629005422622b7afc658c558e1f9b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 7 12:51:19 2013 +0300 arch/armv7 devicetree: Drop unnecessary PCI headers Including pci.h for arch/armv7 breaks builds and/or uses invalid arch/pci_ops.h. Change-Id: Ib78e7367be400c96ab0f8d6ec25dce241a768abd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/hardwaremain.c | 1 - util/sconfig/main.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 56539cb..28dac5b 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <version.h> #include <device/device.h> -#include <device/pci.h> #include <delay.h> #include <stdlib.h> #include <reset.h> diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 03ba1ef..4161c48 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -634,7 +634,7 @@ int main(int argc, char** argv) { if (scan_mode == STATIC_MODE) { fprintf(autogen, "#include <device/device.h>\n"); - fprintf(autogen, "#include <device/pci.h>\n"); + fprintf(autogen, "#if CONFIG_PCI\n#include <device/pci.h>\n#endif\n"); h = &headers; while (h->next) { h = h->next;

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New patch to review for coreboot: 5f8801a arch/armv7 devicetree: Conditionally have PCI headers
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3622 -gerrit commit 5f8801acc133a7240b9fe95914bc571f9491d99e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 7 12:51:19 2013 +0300 arch/armv7 devicetree: Conditionally have PCI headers Including pci.h for arch/armv7 breaks builds and/or uses invalid arch/pci_ops.h. Change-Id: Ib78e7367be400c96ab0f8d6ec25dce241a768abd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- util/sconfig/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 03ba1ef..4161c48 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -634,7 +634,7 @@ int main(int argc, char** argv) { if (scan_mode == STATIC_MODE) { fprintf(autogen, "#include <device/device.h>\n"); - fprintf(autogen, "#include <device/pci.h>\n"); + fprintf(autogen, "#if CONFIG_PCI\n#include <device/pci.h>\n#endif\n"); h = &headers; while (h->next) { h = h->next;

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Patch set updated for coreboot: b0cca9d arch/armv7: Drop PCI config operations
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3621 -gerrit commit b0cca9d6040c240f2697f70278d5fc30d1de88ba Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 7 11:18:23 2013 +0300 arch/armv7: Drop PCI config operations Leave empty stub file to not break includes. Change-Id: I1c2b47dfccc612e3d342cc3c3083630154869ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/pci_ops.h | 20 +++----------------- 1 file changed, 3 insertions(+), 17 deletions(-) diff --git a/src/arch/armv7/include/arch/pci_ops.h b/src/arch/armv7/include/arch/pci_ops.h index eca9390..1d52bd3 100644 --- a/src/arch/armv7/include/arch/pci_ops.h +++ b/src/arch/armv7/include/arch/pci_ops.h @@ -1,19 +1,5 @@ -#ifndef ARCH_I386_PCI_OPS_H -#define ARCH_I386_PCI_OPS_H +#ifndef ARCH_ARMV7_PCI_OPS_H +#define ARCH_ARMV7_PCI_OPS_H -extern const struct pci_bus_operations pci_cf8_conf1; -#if CONFIG_MMCONF_SUPPORT -extern const struct pci_bus_operations pci_ops_mmconf; -#endif - -static inline const struct pci_bus_operations *pci_config_default(void) -{ - return &pci_cf8_conf1; -} - -static inline void pci_set_method(device_t dev) -{ - dev->ops->ops_pci_bus = pci_config_default(); -} -#endif /* ARCH_I386_PCI_OPS_H */ +#endif /* ARCH_ARMV7_PCI_OPS_H */

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Patch set updated for coreboot: 620aecc Redefine pci_bus_default_ops as function
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3608 -gerrit commit 620aecceb235434ec6e6cde4af42b616bcb26fd2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 4 17:17:45 2013 +0300 Redefine pci_bus_default_ops as function Taking device_t as a parameter, this allows to alter the PCI config access handlers. This is useful to add tracing of PCI config writes for devices having problems to initialise correctly. On older AMD platform PCI MMIO may not be able to fully configure all PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due to its atomic nature. So those can be forced to IO config instead. Change-Id: I2162884185bbfe461b036caf737980b45a51e522 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/pci_ops.h | 15 +------------- src/device/pci_ops.c | 41 ++++++++++++++++++++++++++++--------- src/include/device/device.h | 2 +- src/include/device/pci.h | 12 ----------- 4 files changed, 33 insertions(+), 37 deletions(-) diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index fa29317..35b49c6 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -7,19 +7,6 @@ extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_ops_mmconf; #endif -#if CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_bus_default_ops &pci_ops_mmconf -#else -#define pci_bus_default_ops &pci_cf8_conf1 -#endif - -static inline const struct pci_bus_operations *pci_config_default(void) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return &pci_ops_mmconf; -#else - return &pci_cf8_conf1; -#endif -} +extern const struct pci_bus_operations *pci_bus_default_ops(device_t dev); #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index b0281f4..32eb584 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -25,9 +25,30 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +const struct pci_bus_operations *pci_bus_default_ops(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return &pci_ops_mmconf; +#else + return &pci_cf8_conf1; +#endif +} + +static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, device_t dev) +{ + const struct pci_bus_operations *bops; + bops = 0; + if (bus && bus->dev && bus->dev->ops && bus->dev->ops->ops_pci_bus) { + bops = bus->dev->ops->ops_pci_bus(dev); + } + if (!bops) + bops = pci_bus_default_ops(dev); + return bops; +} + /* - * The only consumer of the return value of get_pbus() is ops_pci_bus(). - * ops_pci_bus() can handle being passed NULL and auto-picks working ops. + * The only consumer of the return value of get_pbus() is pci_bus_ops(). + * pci_bus_ops() can handle being passed NULL and auto-picks working ops. */ static struct bus *get_pbus(device_t dev) { @@ -38,10 +59,10 @@ static struct bus *get_pbus(device_t dev) else pbus = dev->bus; - while (pbus && pbus->dev && !ops_pci_bus(pbus)) { + while (pbus && pbus->dev && !pci_bus_ops(pbus, dev)) { if (pbus == pbus->dev->bus) { printk(BIOS_ALERT, "%s in endless loop looking for a " - "parent bus with ops_pci_bus for %s, breaking " + "parent bus with pci_bus_ops for %s, breaking " "out.\n", __func__, dev_path(dev)); break; } @@ -64,42 +85,42 @@ static struct bus *get_pbus(device_t dev) u8 pci_read_config8(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } u16 pci_read_config16(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } u32 pci_read_config32(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } void pci_write_config8(device_t dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config16(device_t dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config32(device_t dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } diff --git a/src/include/device/device.h b/src/include/device/device.h index 9defb19..1eff4a2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -42,7 +42,7 @@ struct device_operations { #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; - const struct pci_bus_operations *ops_pci_bus; + const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); const struct pnp_mode_ops *ops_pnp_mode; }; #endif diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 1f47daf..2dea1cf 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -94,17 +94,5 @@ static inline const struct pci_operations *ops_pci(device_t dev) return pops; } -static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) -{ - const struct pci_bus_operations *bops; - bops = 0; - if (bus && bus->dev && bus->dev->ops) { - bops = bus->dev->ops->ops_pci_bus; - } - if (!bops) - bops = pci_config_default(); - return bops; -} - #endif #endif /* PCI_H */

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New patch to review for coreboot: a43ecbd arch/armv7: Drop PCI config operations
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3621 -gerrit commit a43ecbdac67b2e888c3cbee6f46ba08d0d801758 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 7 11:18:23 2013 +0300 arch/armv7: Drop PCI config operations Leave empty stub file to not break includes. Change-Id: I1c2b47dfccc612e3d342cc3c3083630154869ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/pci_ops.h | 20 +++----------------- 1 file changed, 3 insertions(+), 17 deletions(-) diff --git a/src/arch/armv7/include/arch/pci_ops.h b/src/arch/armv7/include/arch/pci_ops.h index eca9390..1d52bd3 100644 --- a/src/arch/armv7/include/arch/pci_ops.h +++ b/src/arch/armv7/include/arch/pci_ops.h @@ -1,19 +1,5 @@ -#ifndef ARCH_I386_PCI_OPS_H -#define ARCH_I386_PCI_OPS_H +#ifndef ARCH_ARMV7_PCI_OPS_H +#define ARCH_ARMV7_PCI_OPS_H -extern const struct pci_bus_operations pci_cf8_conf1; -#if CONFIG_MMCONF_SUPPORT -extern const struct pci_bus_operations pci_ops_mmconf; -#endif - -static inline const struct pci_bus_operations *pci_config_default(void) -{ - return &pci_cf8_conf1; -} - -static inline void pci_set_method(device_t dev) -{ - dev->ops->ops_pci_bus = pci_config_default(); -} -#endif /* ARCH_I386_PCI_OPS_H */ +#endif /* ARCH_ARMV7_PCI_OPS_H */

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Patch set updated for coreboot: 70d4adb Redefine pci_bus_default_ops as function
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3608 -gerrit commit 70d4adb8bf2ece4ff7ee44f54be9f9a2835fb63a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 4 17:17:45 2013 +0300 Redefine pci_bus_default_ops as function Taking device_t as a parameter, this allows to alter the PCI config access handlers. This is useful to add tracing of PCI config writes for devices having problems to initialise correctly. On older AMD platform PCI MMIO may not be able to fully configure all PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due to its atomic nature. So those can be forced to IO config instead. Change-Id: I2162884185bbfe461b036caf737980b45a51e522 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/pci_ops.h | 15 +------------- src/device/pci_ops.c | 41 ++++++++++++++++++++++++++++--------- src/include/device/device.h | 2 +- src/include/device/pci.h | 12 ----------- 4 files changed, 33 insertions(+), 37 deletions(-) diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index fa29317..35b49c6 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -7,19 +7,6 @@ extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_ops_mmconf; #endif -#if CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_bus_default_ops &pci_ops_mmconf -#else -#define pci_bus_default_ops &pci_cf8_conf1 -#endif - -static inline const struct pci_bus_operations *pci_config_default(void) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return &pci_ops_mmconf; -#else - return &pci_cf8_conf1; -#endif -} +extern const struct pci_bus_operations *pci_bus_default_ops(device_t dev); #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index b0281f4..32eb584 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -25,9 +25,30 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +const struct pci_bus_operations *pci_bus_default_ops(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return &pci_ops_mmconf; +#else + return &pci_cf8_conf1; +#endif +} + +static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, device_t dev) +{ + const struct pci_bus_operations *bops; + bops = 0; + if (bus && bus->dev && bus->dev->ops && bus->dev->ops->ops_pci_bus) { + bops = bus->dev->ops->ops_pci_bus(dev); + } + if (!bops) + bops = pci_bus_default_ops(dev); + return bops; +} + /* - * The only consumer of the return value of get_pbus() is ops_pci_bus(). - * ops_pci_bus() can handle being passed NULL and auto-picks working ops. + * The only consumer of the return value of get_pbus() is pci_bus_ops(). + * pci_bus_ops() can handle being passed NULL and auto-picks working ops. */ static struct bus *get_pbus(device_t dev) { @@ -38,10 +59,10 @@ static struct bus *get_pbus(device_t dev) else pbus = dev->bus; - while (pbus && pbus->dev && !ops_pci_bus(pbus)) { + while (pbus && pbus->dev && !pci_bus_ops(pbus, dev)) { if (pbus == pbus->dev->bus) { printk(BIOS_ALERT, "%s in endless loop looking for a " - "parent bus with ops_pci_bus for %s, breaking " + "parent bus with pci_bus_ops for %s, breaking " "out.\n", __func__, dev_path(dev)); break; } @@ -64,42 +85,42 @@ static struct bus *get_pbus(device_t dev) u8 pci_read_config8(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } u16 pci_read_config16(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } u32 pci_read_config32(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } void pci_write_config8(device_t dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config16(device_t dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config32(device_t dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } diff --git a/src/include/device/device.h b/src/include/device/device.h index 9defb19..1eff4a2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -42,7 +42,7 @@ struct device_operations { #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; - const struct pci_bus_operations *ops_pci_bus; + const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); const struct pnp_mode_ops *ops_pnp_mode; }; #endif diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 1f47daf..2dea1cf 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -94,17 +94,5 @@ static inline const struct pci_operations *ops_pci(device_t dev) return pops; } -static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) -{ - const struct pci_bus_operations *bops; - bops = 0; - if (bus && bus->dev && bus->dev->ops) { - bops = bus->dev->ops->ops_pci_bus; - } - if (!bops) - bops = pci_config_default(); - return bops; -} - #endif #endif /* PCI_H */

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Patch set updated for coreboot: cf55e3e Redefine pci_bus_default_ops as function
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3608 -gerrit commit cf55e3e5dd27a235e4721addffabdbb77b250134 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 4 17:17:45 2013 +0300 Redefine pci_bus_default_ops as function Taking device_t as a parameter, this allows to alter the PCI config access handlers. This is useful to add tracing of PCI config writes for devices having problems to initialise correctly. On older AMD platform PCI MMIO may not be able to fully configure all PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due to its atomic nature. So those can be forced to IO config instead. Change-Id: I2162884185bbfe461b036caf737980b45a51e522 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/pci_ops.h | 15 +------------- src/device/pci_ops.c | 41 ++++++++++++++++++++++++++++--------- src/include/device/device.h | 2 +- src/include/device/pci.h | 12 ----------- 4 files changed, 33 insertions(+), 37 deletions(-) diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index fa29317..35b49c6 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -7,19 +7,6 @@ extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_ops_mmconf; #endif -#if CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_bus_default_ops &pci_ops_mmconf -#else -#define pci_bus_default_ops &pci_cf8_conf1 -#endif - -static inline const struct pci_bus_operations *pci_config_default(void) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return &pci_ops_mmconf; -#else - return &pci_cf8_conf1; -#endif -} +extern const struct pci_bus_operations *pci_bus_default_ops(device_t dev); #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index b0281f4..32eb584 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -25,9 +25,30 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +const struct pci_bus_operations *pci_bus_default_ops(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return &pci_ops_mmconf; +#else + return &pci_cf8_conf1; +#endif +} + +static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, device_t dev) +{ + const struct pci_bus_operations *bops; + bops = 0; + if (bus && bus->dev && bus->dev->ops && bus->dev->ops->ops_pci_bus) { + bops = bus->dev->ops->ops_pci_bus(dev); + } + if (!bops) + bops = pci_bus_default_ops(dev); + return bops; +} + /* - * The only consumer of the return value of get_pbus() is ops_pci_bus(). - * ops_pci_bus() can handle being passed NULL and auto-picks working ops. + * The only consumer of the return value of get_pbus() is pci_bus_ops(). + * pci_bus_ops() can handle being passed NULL and auto-picks working ops. */ static struct bus *get_pbus(device_t dev) { @@ -38,10 +59,10 @@ static struct bus *get_pbus(device_t dev) else pbus = dev->bus; - while (pbus && pbus->dev && !ops_pci_bus(pbus)) { + while (pbus && pbus->dev && !pci_bus_ops(pbus, dev)) { if (pbus == pbus->dev->bus) { printk(BIOS_ALERT, "%s in endless loop looking for a " - "parent bus with ops_pci_bus for %s, breaking " + "parent bus with pci_bus_ops for %s, breaking " "out.\n", __func__, dev_path(dev)); break; } @@ -64,42 +85,42 @@ static struct bus *get_pbus(device_t dev) u8 pci_read_config8(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } u16 pci_read_config16(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } u32 pci_read_config32(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } void pci_write_config8(device_t dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config16(device_t dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config32(device_t dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } diff --git a/src/include/device/device.h b/src/include/device/device.h index 9defb19..1eff4a2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -42,7 +42,7 @@ struct device_operations { #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; - const struct pci_bus_operations *ops_pci_bus; + const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); const struct pnp_mode_ops *ops_pnp_mode; }; #endif diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 1f47daf..2dea1cf 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -94,17 +94,5 @@ static inline const struct pci_operations *ops_pci(device_t dev) return pops; } -static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) -{ - const struct pci_bus_operations *bops; - bops = 0; - if (bus && bus->dev && bus->dev->ops) { - bops = bus->dev->ops->ops_pci_bus; - } - if (!bops) - bops = pci_config_default(); - return bops; -} - #endif #endif /* PCI_H */

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Patch set updated for coreboot: 93fb53f Add a new and safer bootblock implementation.
by Denis Carikli 06 Jul '13

06 Jul '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3549 -gerrit commit 93fb53fd2340909ab49c25ae9a2a2183c2a0d7dc Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 21 23:32:19 2013 +0200 Add a new and safer bootblock implementation. The drawback is that it requires cooperation from something that is run after coreboot (like the OS or the payload). To understand how to use it, refer to the Kconfig help of that option. Thanks a lot to kmalkki on #coreboot Freenode IRC channel for pointers on how to simplify the implementation. Change-Id: I1109c49c7c84461bb056b36ee5d07391c2392176 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 13 ++++++++++ src/arch/x86/init/bootblock_failboot.c | 47 ++++++++++++++++++++++++++++++++++ src/drivers/pc80/mc146818rtc_early.c | 28 ++++++++++++++++++++ 3 files changed, 88 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 69cdc8a..721a487 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -54,12 +54,25 @@ config X86_BOOTBLOCK_SIMPLE config X86_BOOTBLOCK_NORMAL bool "Switch to normal if CMOS says so" +config X86_BOOTBLOCK_FAILBOOT + bool "Switch to Fallback if it fails to boot" + help + Switch to Fallback after failing to boot. + Coreboot will reset boot_option to Fallback + as early as possible, If the user has + a Fallback and a Normal image in cbfs, + and wants to boot on the Normal image, + he must reset the boot_option to Normal + after successfully booting (like trough the OS + boot scripts that would run something like: + "nvramtool -w boot_option=Normal". endchoice config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if X86_BOOTBLOCK_SIMPLE default "bootblock_normal.c" if X86_BOOTBLOCK_NORMAL + default "bootblock_failboot.c" if X86_BOOTBLOCK_FAILBOOT config UPDATE_IMAGE bool "Update existing coreboot.rom image" diff --git a/src/arch/x86/init/bootblock_failboot.c b/src/arch/x86/init/bootblock_failboot.c new file mode 100644 index 0000000..96c1449 --- /dev/null +++ b/src/arch/x86/init/bootblock_failboot.c @@ -0,0 +1,47 @@ +#include <bootblock_common.h> +#include <pc80/mc146818rtc.h> + +int boot_mode = 0; + +static const char *get_fallback(const char *stagelist) { + while (*stagelist) stagelist++; + return ++stagelist; +} + +static void main(unsigned long bist) +{ + unsigned long entry; + const char *default_filenames = "normal/romstage\0fallback/romstage"; + + /* I hope that the BSP CPU is started first + * and reach this point first... */ + if (boot_cpu()) { + bootblock_mainboard_init(); + +#if CONFIG_USE_OPTION_TABLE + sanitize_cmos(); +#endif + boot_mode = get_and_reset_boot(); + } + + char *filenames = (char *)walkcbfs("coreboot-stages"); + if (!filenames) { + filenames = default_filenames; + } + char *normal_candidate = filenames; + + if (boot_mode) + entry = findstage(normal_candidate); + else + entry = findstage(get_fallback(normal_candidate)); + + if (entry) call(entry, bist); + + /* run fallback if normal can't be found */ + entry = findstage(get_fallback(normal_candidate)); + if (entry) call(entry, bist); + + /* duh. we're stuck */ + asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); +} + diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 0652f27..019e05e 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -49,6 +49,34 @@ static inline int last_boot_normal(void) return (byte & (1 << 1)); } +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline int get_and_reset_boot(void) +{ + unsigned char old_byte, write_byte; + + if (cmos_error() || !cmos_chksum_valid()) { + /* There are no impossible values, no checksums so just + * trust whatever value we have in the the cmos, + * but clear the fallback bit. + */ + write_byte = cmos_read(RTC_BOOT_BYTE); + write_byte &= 0x0c; + cmos_write(write_byte, RTC_BOOT_BYTE); + } + + /* The RTC_BOOT_BYTE is now o.k. see where to go. */ + write_byte = old_byte = cmos_read(RTC_BOOT_BYTE); + + /* Reset boot_option to Fallback */ + write_byte &= ~(1<<0); + + /* Save the boot byte */ + cmos_write(write_byte, RTC_BOOT_BYTE); + + return (old_byte & (1<<0)); +} +#endif + static inline int do_normal_boot(void) { unsigned char byte;

1 0

Patch set updated for coreboot: f0e74c9 Add a new and safer bootblock implementation.
by Denis Carikli 06 Jul '13

06 Jul '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3549 -gerrit commit f0e74c9da36fca760d7355eca064c382102e34cb Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 21 23:32:19 2013 +0200 Add a new and safer bootblock implementation. The drawback is that it requires cooperation from something that is run after coreboot (like the OS or the payload). To understand how to use it, refer to the Kconfig help of that option. Thanks a lot to kmalkki on #coreboot Freenode IRC channel for pointers on how to simplify the implementation. Change-Id: I1109c49c7c84461bb056b36ee5d07391c2392176 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 13 ++++++++++ src/arch/x86/init/bootblock_failboot.c | 46 ++++++++++++++++++++++++++++++++++ src/drivers/pc80/mc146818rtc_early.c | 28 +++++++++++++++++++++ 3 files changed, 87 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 69cdc8a..721a487 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -54,12 +54,25 @@ config X86_BOOTBLOCK_SIMPLE config X86_BOOTBLOCK_NORMAL bool "Switch to normal if CMOS says so" +config X86_BOOTBLOCK_FAILBOOT + bool "Switch to Fallback if it fails to boot" + help + Switch to Fallback after failing to boot. + Coreboot will reset boot_option to Fallback + as early as possible, If the user has + a Fallback and a Normal image in cbfs, + and wants to boot on the Normal image, + he must reset the boot_option to Normal + after successfully booting (like trough the OS + boot scripts that would run something like: + "nvramtool -w boot_option=Normal". endchoice config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if X86_BOOTBLOCK_SIMPLE default "bootblock_normal.c" if X86_BOOTBLOCK_NORMAL + default "bootblock_failboot.c" if X86_BOOTBLOCK_FAILBOOT config UPDATE_IMAGE bool "Update existing coreboot.rom image" diff --git a/src/arch/x86/init/bootblock_failboot.c b/src/arch/x86/init/bootblock_failboot.c new file mode 100644 index 0000000..85d6339 --- /dev/null +++ b/src/arch/x86/init/bootblock_failboot.c @@ -0,0 +1,46 @@ +#include <bootblock_common.h> +#include <pc80/mc146818rtc.h> + +static const char *get_fallback(const char *stagelist) { + while (*stagelist) stagelist++; + return ++stagelist; +} + +static void main(unsigned long bist) +{ + unsigned long entry; + int boot_mode = 0; + const char *default_filenames = "normal/romstage\0fallback/romstage"; + + /* I hope that the BSP CPU is started first + * and reach this point first... */ + if (boot_cpu()) { + bootblock_mainboard_init(); + +#if CONFIG_USE_OPTION_TABLE + sanitize_cmos(); +#endif + boot_mode = get_and_reset_boot(); + } + + char *filenames = (char *)walkcbfs("coreboot-stages"); + if (!filenames) { + filenames = default_filenames; + } + char *normal_candidate = filenames; + + if (boot_mode) + entry = findstage(normal_candidate); + else + entry = findstage(get_fallback(normal_candidate)); + + if (entry) call(entry, bist); + + /* run fallback if normal can't be found */ + entry = findstage(get_fallback(normal_candidate)); + if (entry) call(entry, bist); + + /* duh. we're stuck */ + asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); +} + diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 0652f27..019e05e 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -49,6 +49,34 @@ static inline int last_boot_normal(void) return (byte & (1 << 1)); } +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline int get_and_reset_boot(void) +{ + unsigned char old_byte, write_byte; + + if (cmos_error() || !cmos_chksum_valid()) { + /* There are no impossible values, no checksums so just + * trust whatever value we have in the the cmos, + * but clear the fallback bit. + */ + write_byte = cmos_read(RTC_BOOT_BYTE); + write_byte &= 0x0c; + cmos_write(write_byte, RTC_BOOT_BYTE); + } + + /* The RTC_BOOT_BYTE is now o.k. see where to go. */ + write_byte = old_byte = cmos_read(RTC_BOOT_BYTE); + + /* Reset boot_option to Fallback */ + write_byte &= ~(1<<0); + + /* Save the boot byte */ + cmos_write(write_byte, RTC_BOOT_BYTE); + + return (old_byte & (1<<0)); +} +#endif + static inline int do_normal_boot(void) { unsigned char byte;

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coreboot-gerrit July 2013