coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

1 participants
1030 discussions

Patch set updated for coreboot: c30ac29 usbdebug: Use CAR migration
by Kyösti Mälkki 08 Jul '13

08 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3476 -gerrit commit c30ac2924497289eefc189cf190b26cde2f882c9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jul 6 11:41:21 2013 +0300 usbdebug: Use CAR migration If we already initialized EHCI controller and USB device in romstage, locate active configuration from salvaged CAR_GLOBAL and avoid doing the hardware initialisation again. Change-Id: I7cb3a359488b25abc9de49c96c0197f6563a4a2c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 1 + src/lib/cbmem_info.c | 1 + src/lib/usbdebug.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index efb0f90..f1931a9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -70,6 +70,7 @@ #define CBMEM_ID_ROOT 0xff4007ff #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 +#define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index 65be67c..a60761f 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -48,6 +48,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, + { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, }; void cbmem_print_entry(int n, u32 id, u64 base, u64 size) diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index dd34a07..6ee942d 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -24,6 +24,8 @@ #include <device/pci.h> #include <arch/byteorder.h> #include <cpu/x86/car.h> +#include <cbmem.h> +#include <string.h> #include <usb_ch9.h> #include <ehci.h> @@ -655,6 +657,47 @@ void pci_ehci_read_resources(struct device *dev) pci_dev_read_resources(dev); } + +#if CONFIG_CAR_MIGRATION +static int get_usbdebug_from_cbmem(struct ehci_debug_info *info) +{ + struct ehci_debug_info *dbg_info_cbmem; + + dbg_info_cbmem = cbmem_find(CBMEM_ID_EHCI_DEBUG); + + if (dbg_info_cbmem == NULL) + return -1; + + info->ehci_caps = dbg_info_cbmem->ehci_caps; + info->ehci_regs = dbg_info_cbmem->ehci_regs; + info->ehci_debug = dbg_info_cbmem->ehci_debug; + info->devnum = dbg_info_cbmem->devnum; + info->endpoint_out = dbg_info_cbmem->endpoint_out; + info->endpoint_in = dbg_info_cbmem->endpoint_in; + info->ehci_info = info; + + printk(BIOS_DEBUG, "EHCI debug port found in CBMEM.\n"); + + return 0; +} +#endif +#endif + +#if CONFIG_CAR_MIGRATION && defined(__PRE_RAM__) +static void migrate_ehci_debug(void) +{ + struct ehci_debug_info *dbg_info; + struct ehci_debug_info *dbg_info_cbmem; + + dbg_info = car_get_var_ptr(&glob_dbg_info); + + dbg_info_cbmem = cbmem_add(CBMEM_ID_EHCI_DEBUG, sizeof(*dbg_info)); + if (dbg_info_cbmem == NULL) + return; + + memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info)); +} +CAR_MIGRATE(migrate_ehci_debug); #endif struct ehci_debug_info *dbgp_ehci_info(void) @@ -665,6 +708,11 @@ struct ehci_debug_info *dbgp_ehci_info(void) int usbdebug_init(void) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); + +#if CONFIG_CAR_MIGRATION && !defined(__PRE_RAM__) && !defined(__SMM__) + if (!get_usbdebug_from_cbmem(dbg_info)) + return 0; +#endif #if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); #endif

1 0

Patch set updated for coreboot: 988899f usbdebug: Put ehci_debug_info in CAR_GLOBAL
by Kyösti Mälkki 08 Jul '13

08 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3475 -gerrit commit 988899f086040a9034b6322abb7458ad02dc27cf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jul 6 11:41:09 2013 +0300 usbdebug: Put ehci_debug_info in CAR_GLOBAL Store EHCI Debug Port runtime variables in CAR_GLOBAL. For platforms without CAR_MIGRATION, logging on EHCI Debug Port is temporarily lost when CAR is torn down at end of romstage. On model_2065x and model_206ax ehci_debug_info was overlapping the MRC variable region and additionally migration used incorrect size for the structure. Change-Id: I5e6c613b8a4b1dda43d5b69bd437753108760fca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 5 ----- src/cpu/intel/haswell/cache_as_ram.inc | 9 --------- src/cpu/intel/model_2065x/cache_as_ram.inc | 9 --------- src/cpu/intel/model_206ax/cache_as_ram.inc | 9 --------- src/cpu/intel/model_6ex/cache_as_ram.inc | 5 ----- src/lib/usbdebug.c | 11 +++-------- 6 files changed, 3 insertions(+), 45 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 8a845e9..fe1e29a 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -334,12 +334,7 @@ no_msr_11e: post_code(0x2e) /* Set up the stack pointer. */ -#if CONFIG_USBDEBUG - /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp -#else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp -#endif /* Restore the BIST result. */ movl %ebp, %eax diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 8601f46..2d1e86f 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -190,15 +190,6 @@ before_romstage: post_code(0x2f) - /* Copy global variable space (for USBDEBUG) to memory */ -#if CONFIG_USBDEBUG - cld - movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi - movl $(CONFIG_RAMTOP - 24), %edi - movl $24, %ecx - rep movsb -#endif - post_code(0x30) /* Disable cache. */ diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index db0eaae..ec7335e 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -182,15 +182,6 @@ before_romstage: post_code(0x2f) - /* Copy global variable space (for USBDEBUG) to memory */ -#if CONFIG_USBDEBUG - cld - movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi - movl $(CONFIG_RAMTOP - 24), %edi - movl $24, %ecx - rep movsb -#endif - post_code(0x30) /* Disable cache. */ diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 2652cb7..b4119cc 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -182,15 +182,6 @@ before_romstage: post_code(0x2f) - /* Copy global variable space (for USBDEBUG) to memory */ -#if CONFIG_USBDEBUG - cld - movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi - movl $(CONFIG_RAMTOP - 24), %edi - movl $24, %ecx - rep movsb -#endif - post_code(0x30) /* Disable cache. */ diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 50fab35..ac3c66b 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -126,12 +126,7 @@ clear_mtrrs: movl %eax, %cr0 /* Set up the stack pointer. */ -#if CONFIG_USBDEBUG - /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax -#else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax -#endif movl %eax, %esp /* Restore the BIST result. */ diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 0fea9c6..dd34a07 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/pci.h> #include <arch/byteorder.h> +#include <cpu/x86/car.h> #include <usb_ch9.h> #include <ehci.h> @@ -87,8 +88,8 @@ #define DBGP_MAX_PACKET 8 #define DBGP_LOOPS 1000 +static struct ehci_debug_info glob_dbg_info CAR_GLOBAL; #if !defined(__PRE_RAM__) && !defined(__SMM__) -static struct ehci_debug_info glob_dbg_info; static struct device_operations *ehci_drv_ops; static struct device_operations ehci_dbg_ops; #endif @@ -658,13 +659,7 @@ void pci_ehci_read_resources(struct device *dev) struct ehci_debug_info *dbgp_ehci_info(void) { -#if __PRE_RAM__ - /* "Find" dbg_info structure in Cache */ - return (struct ehci_debug_info *) - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); -#else - return &glob_dbg_info; -#endif + return car_get_var_ptr(&glob_dbg_info); } int usbdebug_init(void)

1 0

Patch merged into coreboot/master: d0b0400 Revert "Radio and dock support in EC on X60 and X201"
by gerrit＠coreboot.org 08 Jul '13

08 Jul '13

the following patch was just integrated into master: commit d0b04003d0a3ebfa11f54128a2d423ca16b6ba8a Author: Peter Stuge <peter(a)stuge.se> Date: Sat Jul 6 20:20:45 2013 +0200 Revert "Radio and dock support in EC on X60 and X201" This reverts commit 7d1ebbff5ad224591a2d1972737611f96a13145c Change-Id: I4a9d0cd31a3df3d1e092193953f334697ca65167 Signed-off-by: Peter Stuge <peter(a)stuge.se> Reviewed-on: http://review.coreboot.org/3616 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3616 for details. -gerrit

1 0

Patch set updated for coreboot: 3848aed Add a new and safer bootblock implementation.
by Denis Carikli 07 Jul '13

07 Jul '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3549 -gerrit commit 3848aedf936040ec0630368a85b67d8fa73cccdc Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 21 23:32:19 2013 +0200 Add a new and safer bootblock implementation. The drawback is that it requires cooperation from something that is run after coreboot (like the OS or the payload). To understand how to use it, refer to the Kconfig help of that option. Thanks a lot to kmalkki on #coreboot Freenode IRC channel for pointers on how to simplify the implementation. Change-Id: I1109c49c7c84461bb056b36ee5d07391c2392176 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 13 +++++++++++++ src/drivers/pc80/mc146818rtc_early.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 69cdc8a..3bb6547 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -54,12 +54,25 @@ config X86_BOOTBLOCK_SIMPLE config X86_BOOTBLOCK_NORMAL bool "Switch to normal if CMOS says so" +config X86_BOOTBLOCK_FAILBOOT + bool "Switch to Fallback if it fails to boot" + help + Switch to Fallback after failing to boot. + Coreboot will reset boot_option to Fallback + as early as possible, If the user has + a Fallback and a Normal image in cbfs, + and wants to boot on the Normal image, + he must reset the boot_option to Normal + after successfully booting (like trough the OS + boot scripts that would run something like: + "nvramtool -w boot_option=Normal". endchoice config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if X86_BOOTBLOCK_SIMPLE default "bootblock_normal.c" if X86_BOOTBLOCK_NORMAL + default "bootblock_normal.c" if X86_BOOTBLOCK_FAILBOOT config UPDATE_IMAGE bool "Update existing coreboot.rom image" diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 0652f27..717c514 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -49,6 +49,39 @@ static inline int last_boot_normal(void) return (byte & (1 << 1)); } +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline int do_normal_boot(void) +{ + unsigned char byte; + + if (cmos_error() || !cmos_chksum_valid()) { + /* There are no impossible values, no checksums so just + * trust whatever value we have in the the cmos, + * but clear the fallback bit. + */ + byte = cmos_read(RTC_BOOT_BYTE); + byte &= 0x0c; + cmos_write(byte, RTC_BOOT_BYTE); + } + + byte = cmos_read(RTC_BOOT_BYTE); + + /* Copy boot_option to last_boot */ + if (byte & (1<<0)) + byte |= (1<<1); + else + byte &= ~(1<<1); + + /* Reset boot_option to Fallback */ + byte &= ~(1<<0); + + /* Write back the modified content to the nvram */ + cmos_write(byte, RTC_BOOT_BYTE); + + /* Return the saved boot_option */ + return (byte & (1<<1)); +} +#else static inline int do_normal_boot(void) { unsigned char byte; @@ -91,6 +124,7 @@ static inline int do_normal_boot(void) return (byte & (1<<1)); } +#endif unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) {

1 0

Patch set updated for coreboot: 8dd28ee Drop some duplicates of PCI-e config functions
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3502 -gerrit commit 8dd28ee25511f0474a1f4bc8f7b3eb095fad40dd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 19 23:05:00 2013 +0300 Drop some duplicates of PCI-e config functions These are not specific to Intel. Further work needs to be done to combine these with MMCONF_SUPPORT in arch/io.h. Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 2 + src/arch/x86/include/arch/pci_mmio_cfg.h | 98 +++++++++++++++++++++++++ src/mainboard/google/stout/mainboard_smi.c | 1 - src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/i945/pcie_config.c | 68 ----------------- src/northbridge/intel/sandybridge/early_init.c | 1 - src/northbridge/intel/sandybridge/finalize.c | 1 - src/northbridge/intel/sandybridge/pcie_config.c | 89 ---------------------- src/northbridge/intel/sch/pcie_config.c | 66 ----------------- src/southbridge/intel/bd82x6x/finalize.c | 1 - src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/bd82x6x/spi.c | 2 +- src/southbridge/intel/i82801dx/smihandler.c | 6 -- src/southbridge/intel/i82801gx/smihandler.c | 2 +- src/southbridge/intel/sch/smihandler.c | 7 -- 17 files changed, 105 insertions(+), 246 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 29c8339..49499b9 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -395,6 +395,8 @@ static inline __attribute__((always_inline)) void pci_write_config32(device_t de #endif } +#include <arch/pci_mmio_cfg.h> + static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) { pci_write_config8(dev, where, pci_read_config8(dev, where) | value); diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h new file mode 100644 index 0000000..dd00d37 --- /dev/null +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PCI_MMIO_CFG_H +#define _PCI_MMIO_CFG_H + +#include <arch/io.h> + +#if CONFIG_MMCONF_SUPPORT +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +static inline __attribute__ ((always_inline)) +u8 pcie_read_config8(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read8(addr); +} + +static inline __attribute__ ((always_inline)) +u16 pcie_read_config16(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read16(addr); +} + +static inline __attribute__ ((always_inline)) +u32 pcie_read_config32(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read32(addr); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config8(device_t dev, unsigned int where, u8 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write8(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config16(device_t dev, unsigned int where, u16 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write16(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config32(device_t dev, unsigned int where, u32 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write32(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pcie_read_config8(dev, where); + pcie_write_config8(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pcie_read_config16(dev, where); + pcie_write_config16(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pcie_read_config32(dev, where); + pcie_write_config32(dev, where, value | ormask); +} + +#endif /* CONFIG_MMCONF_SUPPORT */ +#endif /* _PCI_MMIO_CFG_H */ diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 7981046..8b37da3 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -24,7 +24,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> #include <cpu/intel/model_206ax/model_206ax.h> /* Include romstage serial for SIO helper functions */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index fd9f6b7..946f7aa 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -23,7 +23,6 @@ #include <arch/io.h> #include <device/pci_def.h> #include "i945.h" -#include "pcie_config.c" int i945_silicon_revision(void) { diff --git a/src/northbridge/intel/i945/pcie_config.c b/src/northbridge/intel/i945/pcie_config.c deleted file mode 100644 index 0310d67..0000000 --- a/src/northbridge/intel/i945/pcie_config.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "i945.h" - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 583385b..d688f5b 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -25,7 +25,6 @@ #include <device/pci_def.h> #include <elog.h> #include "sandybridge.h" -#include "pcie_config.c" static void sandybridge_setup_bars(void) { diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 0fa8d1a..9b41cfa 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <stdlib.h> -#include "pcie_config.c" #include "sandybridge.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/sandybridge/pcie_config.c b/src/northbridge/intel/sandybridge/pcie_config.c deleted file mode 100644 index 0677d76..0000000 --- a/src/northbridge/intel/sandybridge/pcie_config.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "sandybridge.h" - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) -{ - u8 value = pcie_read_config8(dev, where); - pcie_write_config8(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) -{ - u16 value = pcie_read_config16(dev, where); - pcie_write_config16(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) -{ - u32 value = pcie_read_config32(dev, where); - pcie_write_config32(dev, where, value | ormask); -} diff --git a/src/northbridge/intel/sch/pcie_config.c b/src/northbridge/intel/sch/pcie_config.c deleted file mode 100644 index ad7d746..0000000 --- a/src/northbridge/intel/sch/pcie_config.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index bcc2f3d..b1d2d34 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <console/post_codes.h> -#include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" #include <spi-generic.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7fdf926..626e61a 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f79adf5..72175d8 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 5913115..9588703 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -37,7 +37,7 @@ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 09169b1..c720afe 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -34,7 +34,7 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 5470890..9b0c235 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -// #include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 2e29acd..e5bdfd8 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -206,7 +206,7 @@ static void dump_tco_status(u32 tco_sts) * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include "../../../northbridge/intel/i945/pcie_config.c" +#include <arch/pci_mmio_cfg.h> int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 2ccbc7f..5074138 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts) } #endif - -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -//#include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { //global_nvs_t *gnvs = (global_nvs_t *)0xc00;

1 0

Patch set updated for coreboot: 4c158fe Unify PCI configuration cycles
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3554 -gerrit commit 4c158fe20af5ca347d9d0e409c87644672c2b45f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 26 08:19:14 2013 +0300 Unify PCI configuration cycles Split PCI IO configuration and MMIO configuration cycles to separate files. Modern hardware does not use IO cycles for PCI configuration after initial setup in bootblock. Note that the pci_mmio_ and pcie_ functions were different in masking the alignment for register address. PCI standard requires that 16-bit and 32-bit configuration register writes do not cross boundaries. Change-Id: Ie6441283e1a033b4b395e972c18c31277f973897 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 183 +------------------------------ src/arch/x86/include/arch/pci_io_cfg.h | 111 +++++++++++++++++++ src/arch/x86/include/arch/pci_mmio_cfg.h | 26 ++++- 3 files changed, 134 insertions(+), 186 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 49499b9..b258dd0 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -213,188 +213,7 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha * Before that We need to use %gs, and leave %fs to other RAM access */ -static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; - return read8(addr); -} -#endif -static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config8(dev, where); -#else - return pci_io_read_config8(dev, where); -#endif -} - -static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); - return read16(addr); -} -#endif - -static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config16(dev, where); -#else - return pci_io_read_config16(dev, where); -#endif -} - - -static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); - return read32(addr); -} -#endif - -static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config32(dev, where); -#else - return pci_io_read_config32(dev, where); -#endif -} - -static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; - write8(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config8(dev, where, value); -#else - pci_io_write_config8(dev, where, value); -#endif -} - - -static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); - write16(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config16(dev, where, value); -#else - pci_io_write_config16(dev, where, value); -#endif -} - - -static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); - write32(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config32(dev, where, value); -#else - pci_io_write_config32(dev, where, value); -#endif -} - +#include <arch/pci_io_cfg.h> #include <arch/pci_mmio_cfg.h> static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h new file mode 100644 index 0000000..fbe83a2 --- /dev/null +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PCI_IO_CFG_H +#define _PCI_IO_CFG_H + +#include <arch/io.h> + +static inline __attribute__((always_inline)) +uint8_t pci_io_read_config8(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inb(0xCFC + (addr & 3)); +} + +static inline __attribute__((always_inline)) +uint16_t pci_io_read_config16(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inw(0xCFC + (addr & 2)); +} + +static inline __attribute__((always_inline)) +uint32_t pci_io_read_config32(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +static inline __attribute__((always_inline)) +void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +static inline __attribute__((always_inline)) +void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); +} + +static inline __attribute__((always_inline)) +void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +#if !CONFIG_MMCONF_SUPPORT_DEFAULT +#define pci_read_config8 pci_io_read_config8 +#define pci_read_config16 pci_io_read_config16 +#define pci_read_config32 pci_io_read_config32 + +#define pci_write_config8 pci_io_write_config8 +#define pci_write_config16 pci_io_write_config16 +#define pci_write_config32 pci_io_write_config32 +#endif + +#endif /* _PCI_IO_CFG_H */ diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index dd00d37..545be23 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -37,7 +37,7 @@ static inline __attribute__ ((always_inline)) u16 pcie_read_config16(device_t dev, unsigned int where) { unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; + addr = DEFAULT_PCIEXBAR | dev | (where & ~1); return read16(addr); } @@ -45,7 +45,7 @@ static inline __attribute__ ((always_inline)) u32 pcie_read_config32(device_t dev, unsigned int where) { unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; + addr = DEFAULT_PCIEXBAR | dev | (where & ~3); return read32(addr); } @@ -61,7 +61,7 @@ static inline __attribute__ ((always_inline)) void pcie_write_config16(device_t dev, unsigned int where, u16 value) { unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; + addr = DEFAULT_PCIEXBAR | dev | (where & ~1); write16(addr, value); } @@ -69,7 +69,7 @@ static inline __attribute__ ((always_inline)) void pcie_write_config32(device_t dev, unsigned int where, u32 value) { unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; + addr = DEFAULT_PCIEXBAR | dev | (where & ~3); write32(addr, value); } @@ -94,5 +94,23 @@ void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) pcie_write_config32(dev, where, value | ormask); } +#define pci_mmio_read_config8 pcie_read_config8 +#define pci_mmio_read_config16 pcie_read_config16 +#define pci_mmio_read_config32 pcie_read_config32 + +#define pci_mmio_write_config8 pcie_write_config8 +#define pci_mmio_write_config16 pcie_write_config16 +#define pci_mmio_write_config32 pcie_write_config32 + +#if CONFIG_MMCONF_SUPPORT_DEFAULT +#define pci_read_config8 pcie_read_config8 +#define pci_read_config16 pcie_read_config16 +#define pci_read_config32 pcie_read_config32 + +#define pci_write_config8 pcie_write_config8 +#define pci_write_config16 pcie_write_config16 +#define pci_write_config32 pcie_write_config32 +#endif + #endif /* CONFIG_MMCONF_SUPPORT */ #endif /* _PCI_MMIO_CFG_H */

1 0

New patch to review for coreboot: 10c97a1 AMD: Kconfig cleanup
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3623 -gerrit commit 10c97a181253b3da494acfb70c460318f840f844 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 7 11:30:48 2013 +0300 AMD: Kconfig cleanup Change-Id: Ie347b32575c26133d52c275622d29d1cd4c6c0c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family12/Kconfig | 12 +++--------- src/cpu/amd/agesa/family14/Kconfig | 14 ++++---------- src/cpu/amd/agesa/family15/Kconfig | 5 ++--- src/cpu/amd/agesa/family15tn/Kconfig | 19 ++++--------------- src/cpu/amd/model_10xxx/Kconfig | 1 + src/cpu/amd/socket_AM2r2/Kconfig | 10 ++++------ src/cpu/amd/socket_AM3/Kconfig | 9 +++------ src/cpu/amd/socket_ASB2/Kconfig | 10 ++++------ src/cpu/amd/socket_C32/Kconfig | 9 +++------ src/cpu/amd/socket_F_1207/Kconfig | 10 ++++------ 10 files changed, 32 insertions(+), 67 deletions(-) diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 1adf5ec..757db9a 100755 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -22,49 +22,43 @@ config CPU_AMD_AGESA_FAMILY12 select PCI_IO_CFG_EXT select X86_AMD_FIXED_MTRRS +if CPU_AMD_AGESA_FAMILY12 + config CPU_ADDR_BITS int default 48 - depends on CPU_AMD_AGESA_FAMILY12 config CPU_SOCKET_TYPE hex default 0x10 - depends on CPU_AMD_AGESA_FAMILY12 # DDR2 and REG config DIMM_SUPPORT hex default 0x0104 - depends on CPU_AMD_AGESA_FAMILY12 config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_AGESA_FAMILY12 config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_AGESA_FAMILY12 config CBB hex default 0x0 - depends on CPU_AMD_AGESA_FAMILY12 config CDB hex default 0x18 - depends on CPU_AMD_AGESA_FAMILY12 config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_AGESA_FAMILY12 config HAVE_INIT_TIMER bool default y - depends on CPU_AMD_AGESA_FAMILY12 +endif diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index dea839e..7acd520 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -22,54 +22,48 @@ config CPU_AMD_AGESA_FAMILY14 select PCI_IO_CFG_EXT select X86_AMD_FIXED_MTRRS +if CPU_AMD_AGESA_FAMILY14 + config CPU_ADDR_BITS int default 36 - depends on CPU_AMD_AGESA_FAMILY14 config CPU_SOCKET_TYPE hex default 0x10 - depends on CPU_AMD_AGESA_FAMILY14 # DDR2 and REG config DIMM_SUPPORT hex default 0x0104 - depends on CPU_AMD_AGESA_FAMILY14 config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_AGESA_FAMILY14 config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_AGESA_FAMILY14 config CBB hex default 0x0 - depends on CPU_AMD_AGESA_FAMILY14 config CDB hex default 0x18 - depends on CPU_AMD_AGESA_FAMILY14 config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_AGESA_FAMILY14 config HAVE_INIT_TIMER bool default y - depends on CPU_AMD_AGESA_FAMILY14 config HIGH_SCRATCH_MEMORY_SIZE hex # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) default 0x71000 - depends on CPU_AMD_AGESA_FAMILY14 + +endif diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index e20cce8..02991a0 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -22,12 +22,11 @@ config CPU_AMD_AGESA_FAMILY15 select PCI_IO_CFG_EXT select X86_AMD_FIXED_MTRRS +if CPU_AMD_AGESA_FAMILY15 + config CPU_ADDR_BITS int default 48 - depends on CPU_AMD_AGESA_FAMILY15 - -if CPU_AMD_AGESA_FAMILY15 config CPU_AMD_SOCKET_G34 bool diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index d2f5a8c..9885570 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -22,59 +22,48 @@ config CPU_AMD_AGESA_FAMILY15_TN select PCI_IO_CFG_EXT select X86_AMD_FIXED_MTRRS +if CPU_AMD_AGESA_FAMILY15_TN + config CPU_ADDR_BITS int default 48 - depends on CPU_AMD_AGESA_FAMILY15_TN config CPU_SOCKET_TYPE hex default 0x10 - depends on CPU_AMD_AGESA_FAMILY15_TN # DDR2 and REG config DIMM_SUPPORT hex default 0x0104 - depends on CPU_AMD_AGESA_FAMILY15_TN config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_AGESA_FAMILY15_TN config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_AGESA_FAMILY15_TN config CBB hex default 0x0 - depends on CPU_AMD_AGESA_FAMILY15_TN config CDB hex default 0x18 - depends on CPU_AMD_AGESA_FAMILY15_TN - -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_AGESA_FAMILY15_TN config XIP_ROM_SIZE hex default 0x100000 - depends on CPU_AMD_AGESA_FAMILY15_TN config HAVE_INIT_TIMER bool default y - depends on CPU_AMD_AGESA_FAMILY15_TN config HIGH_SCRATCH_MEMORY_SIZE hex # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) default 0xA1000 - depends on CPU_AMD_AGESA_FAMILY15_TN + +endif diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 23192f1..e4367f9 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -7,6 +7,7 @@ config CPU_AMD_MODEL_10XXX select UDELAY_LAPIC if CPU_AMD_MODEL_10XXX + config CPU_ADDR_BITS int default 48 diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig index 900bb2b..8379063 100644 --- a/src/cpu/amd/socket_AM2r2/Kconfig +++ b/src/cpu/amd/socket_AM2r2/Kconfig @@ -6,32 +6,30 @@ config CPU_AMD_SOCKET_AM2R2 select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS +if CPU_AMD_SOCKET_AM2R2 + config CPU_SOCKET_TYPE hex default 0x11 - depends on CPU_AMD_SOCKET_AM2R2 config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_SOCKET_AM2R2 config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_SOCKET_AM2R2 config CBB hex default 0x0 - depends on CPU_AMD_SOCKET_AM2R2 config CDB hex default 0x18 - depends on CPU_AMD_SOCKET_AM2R2 config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_SOCKET_AM2R2 + +endif diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig index a0e6593..4069bfd 100644 --- a/src/cpu/amd/socket_AM3/Kconfig +++ b/src/cpu/amd/socket_AM3/Kconfig @@ -6,33 +6,30 @@ config CPU_AMD_SOCKET_AM3 select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS +if CPU_AMD_SOCKET_AM3 + config CPU_SOCKET_TYPE hex default 0x11 - depends on CPU_AMD_SOCKET_AM3 config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_SOCKET_AM3 config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_SOCKET_AM3 config CBB hex default 0x0 - depends on CPU_AMD_SOCKET_AM3 config CDB hex default 0x18 - depends on CPU_AMD_SOCKET_AM3 config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_SOCKET_AM3 +endif diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig index dbd952c..a73a29b 100644 --- a/src/cpu/amd/socket_ASB2/Kconfig +++ b/src/cpu/amd/socket_ASB2/Kconfig @@ -6,32 +6,30 @@ config CPU_AMD_SOCKET_ASB2 select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS +if CPU_AMD_SOCKET_ASB2 + config CPU_SOCKET_TYPE hex default 0x13 - depends on CPU_AMD_SOCKET_ASB2 config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_SOCKET_ASB2 config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_SOCKET_ASB2 config CBB hex default 0x0 - depends on CPU_AMD_SOCKET_ASB2 config CDB hex default 0x18 - depends on CPU_AMD_SOCKET_ASB2 config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_SOCKET_ASB2 + +endif diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig index f8e441f..97b37ee 100644 --- a/src/cpu/amd/socket_C32/Kconfig +++ b/src/cpu/amd/socket_C32/Kconfig @@ -6,33 +6,30 @@ config CPU_AMD_SOCKET_C32_NON_AGESA select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS +if CPU_AMD_SOCKET_C32_NON_AGESA + config CPU_SOCKET_TYPE hex default 0x14 - depends on CPU_AMD_SOCKET_C32_NON_AGESA config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_SOCKET_C32_NON_AGESA config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_SOCKET_C32_NON_AGESA config CBB hex default 0x0 - depends on CPU_AMD_SOCKET_C32_NON_AGESA config CDB hex default 0x18 - depends on CPU_AMD_SOCKET_C32_NON_AGESA config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_SOCKET_C32_NON_AGESA +endif diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig index c80b5ed..c36c33c 100644 --- a/src/cpu/amd/socket_F_1207/Kconfig +++ b/src/cpu/amd/socket_F_1207/Kconfig @@ -5,32 +5,30 @@ config CPU_AMD_SOCKET_F_1207 select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS +if CPU_AMD_SOCKET_F_1207 + config CPU_SOCKET_TYPE hex default 0x10 - depends on CPU_AMD_SOCKET_F_1207 config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_SOCKET_F_1207 config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_SOCKET_F_1207 config CBB hex default 0x0 - depends on CPU_AMD_SOCKET_F_1207 config CDB hex default 0x18 - depends on CPU_AMD_SOCKET_F_1207 config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_SOCKET_F_1207 + +endif

1 0

Patch set updated for coreboot: c8fd7db arch/armv7: Drop PCI config operations
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3621 -gerrit commit c8fd7db869f1ab6a2628d686962ed59f9a076f57 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 7 11:18:23 2013 +0300 arch/armv7: Drop PCI config operations Leave mostly empty stub file to not break includes. Change-Id: I1c2b47dfccc612e3d342cc3c3083630154869ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/pci_ops.h | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/src/arch/armv7/include/arch/pci_ops.h b/src/arch/armv7/include/arch/pci_ops.h index eca9390..3b537cd 100644 --- a/src/arch/armv7/include/arch/pci_ops.h +++ b/src/arch/armv7/include/arch/pci_ops.h @@ -1,19 +1,9 @@ -#ifndef ARCH_I386_PCI_OPS_H -#define ARCH_I386_PCI_OPS_H - -extern const struct pci_bus_operations pci_cf8_conf1; - -#if CONFIG_MMCONF_SUPPORT -extern const struct pci_bus_operations pci_ops_mmconf; -#endif +#ifndef ARCH_ARMV7_PCI_OPS_H +#define ARCH_ARMV7_PCI_OPS_H static inline const struct pci_bus_operations *pci_config_default(void) { - return &pci_cf8_conf1; + return NULL; } -static inline void pci_set_method(device_t dev) -{ - dev->ops->ops_pci_bus = pci_config_default(); -} -#endif /* ARCH_I386_PCI_OPS_H */ +#endif /* ARCH_ARMV7_PCI_OPS_H */

1 0

Patch set updated for coreboot: cb49349 Redefine pci_bus_default_ops as function
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3608 -gerrit commit cb49349d9d87eca52e4e05e5737fb4dd8680681b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 4 17:17:45 2013 +0300 Redefine pci_bus_default_ops as function Taking device_t as a parameter, this allows to alter the PCI config access handlers. This is useful to add tracing of PCI config writes for devices having problems to initialise correctly. On older AMD platform PCI MMIO may not be able to fully configure all PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due to its atomic nature. So those can be forced to IO config instead. Change-Id: I2162884185bbfe461b036caf737980b45a51e522 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/pci_ops.h | 5 +---- src/arch/x86/include/arch/pci_ops.h | 15 +------------ src/device/pci_ops.c | 41 ++++++++++++++++++++++++++--------- src/include/device/device.h | 2 +- src/include/device/pci.h | 12 ---------- 5 files changed, 34 insertions(+), 41 deletions(-) diff --git a/src/arch/armv7/include/arch/pci_ops.h b/src/arch/armv7/include/arch/pci_ops.h index 3b537cd..39be448 100644 --- a/src/arch/armv7/include/arch/pci_ops.h +++ b/src/arch/armv7/include/arch/pci_ops.h @@ -1,9 +1,6 @@ #ifndef ARCH_ARMV7_PCI_OPS_H #define ARCH_ARMV7_PCI_OPS_H -static inline const struct pci_bus_operations *pci_config_default(void) -{ - return NULL; -} +/* Empty stub until PCI includes are properly fixed. */ #endif /* ARCH_ARMV7_PCI_OPS_H */ diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index fa29317..35b49c6 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -7,19 +7,6 @@ extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_ops_mmconf; #endif -#if CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_bus_default_ops &pci_ops_mmconf -#else -#define pci_bus_default_ops &pci_cf8_conf1 -#endif - -static inline const struct pci_bus_operations *pci_config_default(void) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return &pci_ops_mmconf; -#else - return &pci_cf8_conf1; -#endif -} +extern const struct pci_bus_operations *pci_bus_default_ops(device_t dev); #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index b0281f4..32eb584 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -25,9 +25,30 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +const struct pci_bus_operations *pci_bus_default_ops(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return &pci_ops_mmconf; +#else + return &pci_cf8_conf1; +#endif +} + +static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, device_t dev) +{ + const struct pci_bus_operations *bops; + bops = 0; + if (bus && bus->dev && bus->dev->ops && bus->dev->ops->ops_pci_bus) { + bops = bus->dev->ops->ops_pci_bus(dev); + } + if (!bops) + bops = pci_bus_default_ops(dev); + return bops; +} + /* - * The only consumer of the return value of get_pbus() is ops_pci_bus(). - * ops_pci_bus() can handle being passed NULL and auto-picks working ops. + * The only consumer of the return value of get_pbus() is pci_bus_ops(). + * pci_bus_ops() can handle being passed NULL and auto-picks working ops. */ static struct bus *get_pbus(device_t dev) { @@ -38,10 +59,10 @@ static struct bus *get_pbus(device_t dev) else pbus = dev->bus; - while (pbus && pbus->dev && !ops_pci_bus(pbus)) { + while (pbus && pbus->dev && !pci_bus_ops(pbus, dev)) { if (pbus == pbus->dev->bus) { printk(BIOS_ALERT, "%s in endless loop looking for a " - "parent bus with ops_pci_bus for %s, breaking " + "parent bus with pci_bus_ops for %s, breaking " "out.\n", __func__, dev_path(dev)); break; } @@ -64,42 +85,42 @@ static struct bus *get_pbus(device_t dev) u8 pci_read_config8(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } u16 pci_read_config16(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } u32 pci_read_config32(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where); } void pci_write_config8(device_t dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config16(device_t dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config32(device_t dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); - ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } diff --git a/src/include/device/device.h b/src/include/device/device.h index 9defb19..1eff4a2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -42,7 +42,7 @@ struct device_operations { #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; - const struct pci_bus_operations *ops_pci_bus; + const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); const struct pnp_mode_ops *ops_pnp_mode; }; #endif diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 1f47daf..2dea1cf 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -94,17 +94,5 @@ static inline const struct pci_operations *ops_pci(device_t dev) return pops; } -static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) -{ - const struct pci_bus_operations *bops; - bops = 0; - if (bus && bus->dev && bus->dev->ops) { - bops = bus->dev->ops->ops_pci_bus; - } - if (!bops) - bops = pci_config_default(); - return bops; -} - #endif #endif /* PCI_H */

1 0

Patch set updated for coreboot: 015e00e arch/armv7: Drop PCI config operations
by Kyösti Mälkki 07 Jul '13

07 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3621 -gerrit commit 015e00e98260c63a2d979fe91fa78b6b9fcc90ce Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 7 11:18:23 2013 +0300 arch/armv7: Drop PCI config operations Leave empty stub file to not break includes. Change-Id: I1c2b47dfccc612e3d342cc3c3083630154869ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/pci_ops.h | 20 +++----------------- 1 file changed, 3 insertions(+), 17 deletions(-) diff --git a/src/arch/armv7/include/arch/pci_ops.h b/src/arch/armv7/include/arch/pci_ops.h index eca9390..1d52bd3 100644 --- a/src/arch/armv7/include/arch/pci_ops.h +++ b/src/arch/armv7/include/arch/pci_ops.h @@ -1,19 +1,5 @@ -#ifndef ARCH_I386_PCI_OPS_H -#define ARCH_I386_PCI_OPS_H +#ifndef ARCH_ARMV7_PCI_OPS_H +#define ARCH_ARMV7_PCI_OPS_H -extern const struct pci_bus_operations pci_cf8_conf1; -#if CONFIG_MMCONF_SUPPORT -extern const struct pci_bus_operations pci_ops_mmconf; -#endif - -static inline const struct pci_bus_operations *pci_config_default(void) -{ - return &pci_cf8_conf1; -} - -static inline void pci_set_method(device_t dev) -{ - dev->ops->ops_pci_bus = pci_config_default(); -} -#endif /* ARCH_I386_PCI_OPS_H */ +#endif /* ARCH_ARMV7_PCI_OPS_H */

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2013