coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: caaf0bf usbdebug: Support i82801dx/ex southbridge
by gerrit＠coreboot.org 01 Jul '13

01 Jul '13

the following patch was just integrated into master: commit caaf0bf483288ea092d721954df0407930c67fc8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 6 10:21:28 2013 +0300 usbdebug: Support i82801dx/ex southbridge Tested on i82801dx system with board aopen/dxplplusu. Change-Id: I522455ac79c87b9b6fc9cd8c4dc0da3563dfbfad Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3381 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3381 for details. -gerrit

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Patch merged into coreboot/master: 54c586c usbdebug: Unify Intel southbridge builds
by gerrit＠coreboot.org 01 Jul '13

01 Jul '13

the following patch was just integrated into master: commit 54c586c7e76d9e9ec75ccebaf1555b3fde6114e8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 10 11:40:54 2013 +0300 usbdebug: Unify Intel southbridge builds EHCI controller enable is identical on the affected chipsets. Change-Id: I91830b6f5144a70b158ec1ee40e9cba5fab3fbc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3424 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/3424 for details. -gerrit

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Patch merged into coreboot/master: fb387df usbdebug: Drop duplicates of EHCI BAR relocation code
by gerrit＠coreboot.org 01 Jul '13

01 Jul '13

the following patch was just integrated into master: commit fb387dfb920f73abb144183b8a41dc917e2e32da Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 7 22:16:52 2013 +0300 usbdebug: Drop duplicates of EHCI BAR relocation code All the additional work that needs to be done in EHCI BAR relocation is independent of the hardware platform and was functionally identical in all the copies removed. When USBDEBUG is not selected, PCI EHCI controllers use standard pci_dev_read_resources() call. With USBDEBUG selected, PCI EHCI controller's device_operations .read_resources is replaced with pci_ehci_read_resources() call, which in turn will replace the device_operations .set_resources call. The replacement for .set_resources reconfigures usbdebug driver side, and calls the original .set_resources to configure hardware side. Change-Id: I8e136a5da4efedf60b6dd7068c0488153efaaf8e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3412 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3412 for details. -gerrit

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New patch to review for coreboot: 248979a intel/i945: Use MMCONF_SUPPORT_DEFAULT
by Kyösti Mälkki 01 Jul '13

01 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3584 -gerrit commit 248979a18abed70a1a82d802ffc4ba595b474ad5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 1 11:21:53 2013 +0300 intel/i945: Use MMCONF_SUPPORT_DEFAULT Change all PCI configuration accesses to MMIO on all boards with i945 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/getac/p470/Kconfig | 1 - src/mainboard/ibase/mb899/Kconfig | 1 - src/mainboard/intel/d945gclf/Kconfig | 1 - src/mainboard/kontron/986lcd-m/Kconfig | 1 - src/mainboard/lenovo/t60/Kconfig | 1 - src/mainboard/lenovo/x60/Kconfig | 1 - src/mainboard/roda/rk886ex/Kconfig | 1 - src/northbridge/intel/i945/Kconfig | 6 ++++++ src/northbridge/intel/i945/bootblock.c | 24 ++++++++++++++++++++++++ src/northbridge/intel/i945/early_init.c | 1 - 10 files changed, 30 insertions(+), 8 deletions(-) diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index e7f3c95..3fdf6f7 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -36,7 +36,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_SLIC - select MMCONF_SUPPORT select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 select GFXUMA diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 6b3bdfa..36353b3 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_512 select GFXUMA select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index cc9ceb5..0a9de1a 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_512 select GFXUMA select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 0dd28da..e8b7225 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_1024 select GFXUMA select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 952004b..bf24db7 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select MMCONF_SUPPORT select GFXUMA select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 5ecad2f..bcf5e04 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select MMCONF_SUPPORT select GFXUMA select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 84a8543..2113deb 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select MMCONF_SUPPORT select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index fbc9988..135cbe3 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -24,6 +24,8 @@ if NORTHBRIDGE_INTEL_I945 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER @@ -32,6 +34,10 @@ config NORTHBRIDGE_INTEL_SUBTYPE_I945GC config NORTHBRIDGE_INTEL_SUBTYPE_I945GM def_bool n +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/i945/bootblock.c" + config VGA_BIOS_ID string default "8086,27a2" diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c new file mode 100644 index 0000000..4571446 --- /dev/null +++ b/src/northbridge/intel/i945/bootblock.c @@ -0,0 +1,24 @@ +#include <arch/io.h> + +/* Just re-define this instead of including i945.h. It blows up romcc. */ +#define PCIEXBAR 0x48 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d91930f..fd9f6b7 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -173,7 +173,6 @@ static void i945_setup_bars(void) /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);

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Patch set updated for coreboot: 9e67e39 am335x: Make the default media for the bootblock sram instead of NAND flash.
by Gabe Black 01 Jul '13

01 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3583 -gerrit commit 9e67e39e19e99d1df8ffdcb459ef2d8a5fcb714f Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 05:38:45 2013 -0700 am335x: Make the default media for the bootblock sram instead of NAND flash. The SOC's built in ROM loads the bootblock and the ROM stage into the on chip memory before handing over control to the bootblock. To avoid having to add one or more driver to the bootblock so that it can re-load the ROM stage from whatever media Coreboot is stored on, we can just take advantage of the copy that's already there. Loading the RAM stage/payloads won't be so simple, so the ROM stage and the RAM stage will have to have different media drivers. Change-Id: Id74ed4bc3afd2063277a36e666080522af2305dd Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Makefile.inc | 2 +- src/cpu/ti/am335x/bootblock_media.c | 72 +++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index e1220fa..ff00733 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,5 +1,5 @@ bootblock-y += dmtimer.c -bootblock-y += nand.c +bootblock-y += bootblock_media.c bootblock-y += pinmux.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/cpu/ti/am335x/bootblock_media.c new file mode 100644 index 0000000..553fe42 --- /dev/null +++ b/src/cpu/ti/am335x/bootblock_media.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> + +static int dummy_open(struct cbfs_media *media) +{ + return 0; +} + +static int dummy_close(struct cbfs_media *media) +{ + return 0; +} + +static void * on_chip_memory_map(struct cbfs_media *media, size_t offset, + size_t count) +{ + return (void *)((uintptr_t)CONFIG_BOOTBLOCK_BASE + offset); +} + +static void * dummy_unmap(struct cbfs_media *media, const void *address) +{ + return NULL; +} + +static size_t on_chip_memory_read(struct cbfs_media *media, void *dest, + size_t offset, size_t count) +{ + void *ptr = media->map(media, offset, count); + memcpy(dest, ptr, count); + media->unmap(media, ptr); + return count; +} + +int init_default_cbfs_media(struct cbfs_media *media) +{ + struct cbfs_header *header = + (struct cbfs_header *)((uintptr_t)CONFIG_BOOTBLOCK_BASE + + CONFIG_CBFS_HEADER_ROM_OFFSET); + + if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { + printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); + return -1; + } + + media->open = dummy_open; + media->close = dummy_close; + media->map = on_chip_memory_map; + media->unmap = dummy_unmap; + media->read = on_chip_memory_read; + + return 0; +}

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New patch to review for coreboot: fb239b0 am335x: Make the default media for ROM stage sram instead of NAND flash.
by Gabe Black 01 Jul '13

01 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3583 -gerrit commit fb239b09cf6575dbd7b9b90ff0f102771a9ec7fb Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 05:38:45 2013 -0700 am335x: Make the default media for ROM stage sram instead of NAND flash. The SOC's built in ROM loads the bootblock and the ROM stage into the on chip memory before handing over control to the bootblock. To avoid having to add one or more driver to the bootblock so that it can re-load the ROM stage from whatever media Coreboot is stored on, we can just take advantage of the copy that's already there. Loading the RAM stage/payloads won't be so simple, so the ROM stage and the RAM stage will have to have different media drivers. Change-Id: Id74ed4bc3afd2063277a36e666080522af2305dd Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Makefile.inc | 2 +- src/cpu/ti/am335x/bootblock_media.c | 72 +++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index e1220fa..ff00733 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,5 +1,5 @@ bootblock-y += dmtimer.c -bootblock-y += nand.c +bootblock-y += bootblock_media.c bootblock-y += pinmux.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/cpu/ti/am335x/bootblock_media.c new file mode 100644 index 0000000..553fe42 --- /dev/null +++ b/src/cpu/ti/am335x/bootblock_media.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> + +static int dummy_open(struct cbfs_media *media) +{ + return 0; +} + +static int dummy_close(struct cbfs_media *media) +{ + return 0; +} + +static void * on_chip_memory_map(struct cbfs_media *media, size_t offset, + size_t count) +{ + return (void *)((uintptr_t)CONFIG_BOOTBLOCK_BASE + offset); +} + +static void * dummy_unmap(struct cbfs_media *media, const void *address) +{ + return NULL; +} + +static size_t on_chip_memory_read(struct cbfs_media *media, void *dest, + size_t offset, size_t count) +{ + void *ptr = media->map(media, offset, count); + memcpy(dest, ptr, count); + media->unmap(media, ptr); + return count; +} + +int init_default_cbfs_media(struct cbfs_media *media) +{ + struct cbfs_header *header = + (struct cbfs_header *)((uintptr_t)CONFIG_BOOTBLOCK_BASE + + CONFIG_CBFS_HEADER_ROM_OFFSET); + + if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { + printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); + return -1; + } + + media->open = dummy_open; + media->close = dummy_close; + media->map = on_chip_memory_map; + media->unmap = dummy_unmap; + media->read = on_chip_memory_read; + + return 0; +}

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New patch to review for coreboot: ebb251f am335x: Add the config variable ROMSTAGE_BASE to the CPU's Kconfig.
by Gabe Black 01 Jul '13

01 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3582 -gerrit commit ebb251fa7ee8d9256e8c28854bf6ad02af4360c5 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 05:16:19 2013 -0700 am335x: Add the config variable ROMSTAGE_BASE to the CPU's Kconfig. This variable wasn't being defined and was defaulting to zero when used in the ROM stage's linker script. This change defines it as a variable, and gives it a value which is slightly beyond the end of the bootblock. By making the ROM stage request to be loaded slightly farther into memory than it was loaded by the SOC's masked ROM, we ensure that it's moved away from the stage's metadata instead of on top of it. When it moves the other way, it clobbers important values like the entry point vefore the bootblock has had a chance to use them. Change-Id: I027a1365d05f1d79d7fc1e1349965ccb7d4e81b9 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Kconfig | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index 472fbe7..e776fde 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -10,6 +10,17 @@ config BOOTBLOCK_BASE hex default 0x402f0400 +config CBFS_ROM_OFFSET + # Calculated by BL1 + max bootblock size. + default 0x2800 + +# We need to leave a gap between the bootblock and the ROM stage so that when +# it is "loaded" to a slightly different place in on chip memory, it doesn't +# clobber the metadata needed to actually enter it. +config ROMSTAGE_BASE + hex + default 0x402f2d00 + # Stack may reside in either IRAM or DRAM. We will define it to live # at the top of IRAM for now. # @@ -27,11 +38,6 @@ config STACK_SIZE hex default 0x1000 -config CBFS_ROM_OFFSET - # Calculated by BL1 + max bootblock size. - hex "offset of CBFS data in ROM" - default 0x2800 - ## TODO Change this to some better address not overlapping bootblock when ## cbfstool supports creating header in arbitrary location. config CBFS_HEADER_ROM_OFFSET

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New patch to review for coreboot: c15f385 beaglebone: Put some code in romstage.c so we can tell if it ran.
by Gabe Black 01 Jul '13

01 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3581 -gerrit commit c15f385987b921754a2df77fbfdc0a83778d5550 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 05:12:40 2013 -0700 beaglebone: Put some code in romstage.c so we can tell if it ran. The placeholder code in beaglebone's romstage.c didn't do anything, it just immediately tried to load the RAM stage and jump into it. That doesn't currently work, and there's no indication whether you actually successfully got into the ROM stage or not. This change adds a few lines which initialize the console and say "Hi" so that we can tell that the ROM stage is running. Change-Id: I45a0908c3ac65b21e0e5020428696d2e54933d0e Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/ti/beaglebone/romstage.c b/src/mainboard/ti/beaglebone/romstage.c index 74eaaf2..e5e2477 100644 --- a/src/mainboard/ti/beaglebone/romstage.c +++ b/src/mainboard/ti/beaglebone/romstage.c @@ -30,6 +30,9 @@ void main(void) { void *entry; + console_init(); + printk(BIOS_INFO, "Hello from romstage.\n"); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);

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New patch to review for coreboot: 45c5008 ARM: Define custom ELF headers for ARM.
by Gabe Black 01 Jul '13

01 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3580 -gerrit commit 45c50082ca4c68b3bea0fcb7f639279848e52dda Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 05:03:47 2013 -0700 ARM: Define custom ELF headers for ARM. At least when building with the gnu toolchain, the headers the linker automatically generate save space for the actual ELF headers in one of the loadable segments. This creates two problems. First, the data you intended to be at the start of the image doesn't actually show up there, it's actually the ELF headers. Second, the ELF headers are essentially useless for firmware since there's currently nothing to tell you where they are, and even if there was, there isn't much of a reason to look at them. They're useful in userspace for, for instance, the dynamic linker, but not really in firmware. This change adds a PHDRS construct to each of the linker scripts used on ARM which define a single segment called to_load which does not have the flag set which would tell the linker to put headers in it. The first section defined in the script has ": to_load" to tell the linker which segment to put it in, and from that point on the other sections go in there by default. Change-Id: I24b721eb436d17afd234002ae82f9166d2fcf65d Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/bootblock.lds | 7 ++++++- src/arch/armv7/coreboot_ram.ld | 7 ++++++- src/arch/armv7/romstage.ld | 7 ++++++- 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds index 6f6040d..2003ce4 100644 --- a/src/arch/armv7/bootblock.lds +++ b/src/arch/armv7/bootblock.lds @@ -22,6 +22,11 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) +PHDRS +{ + to_load PT_LOAD; +} + TARGET(binary) SECTIONS { @@ -40,7 +45,7 @@ SECTIONS *(.rom.data.*); *(.rodata.*); _erom = .; - } = 0xff + } : to_load = 0xff /DISCARD/ : { *(.comment) diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index 487f610..38eaca3 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -24,6 +24,11 @@ INCLUDE ldoptions ENTRY(stage_entry) +PHDRS +{ + to_load PT_LOAD; +} + SECTIONS { . = CONFIG_SYS_SDRAM_BASE; @@ -38,7 +43,7 @@ SECTIONS *(.text.*); . = ALIGN(16); _etext = .; - } + } : to_load .ctors : { . = ALIGN(0x100); diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 568ac1a..0555fc4 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -30,6 +30,11 @@ OUTPUT_ARCH(arm) ENTRY(stage_entry) +PHDRS +{ + to_load PT_LOAD; +} + SECTIONS { /* TODO make this a configurable option (per chipset). */ @@ -41,7 +46,7 @@ SECTIONS *(.text.stage_entry.armv7); *(.text.startup); *(.text); - } + } : to_load .romdata . : { *(.rodata);

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New patch to review for coreboot: e04ee9d CBFS: Change how the bss is zeroed when loading a stage.
by Gabe Black 01 Jul '13

01 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3579 -gerrit commit e04ee9d8eb326f70ae60f31ea202e2797a584927 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 04:34:29 2013 -0700 CBFS: Change how the bss is zeroed when loading a stage. For reasons explained in a previous CL, it might be necessary to "load" a file from CBFS in place. The loading code in CBFS was, however, zeroing the area of memory the stage was about to be loaded into. When the CBFS data is located elsewhere this works fine, but when it isn't you end up clobbering the data you're trying to load. Also, there's no reason to zero memory we're about to load something into or have just loaded something into. This change makes it so that we only zero out the portion of the memory between what was loaded/decompressed and the final size of the stage in memory. Change-Id: If34df16bd74b2969583e11ef6a26eb4065842f57 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- payloads/libpayload/libcbfs/cbfs.c | 16 ++++++++++------ src/lib/cbfs.c | 6 ++++-- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index 6243473..4dfe30a 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -136,6 +136,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) /* this is a mess. There is no ntohll. */ /* for now, assume compatible byte order until we solve this. */ uint32_t entry; + uint32_t final_size; if (stage == NULL) return (void *) -1; @@ -144,15 +145,18 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) name, (uint32_t) stage->load, stage->memlen, stage->entry); - memset((void *) (uint32_t) stage->load, 0, stage->memlen); - if (!cbfs_decompress(stage->compression, - ((unsigned char *) stage) + - sizeof(struct cbfs_stage), - (void *) (uint32_t) stage->load, - stage->len)) + final_size = cbfs_decompress(stage->compression, + ((unsigned char *) stage) + + sizeof(struct cbfs_stage), + (void *) (uint32_t) stage->load, + stage->len); + if (!final_size) return (void *) -1; + memset((void *)((uintptr_t)stage->load + final_size), 0, + stage->memlen - final_size); + DEBUG("stage loaded.\n"); entry = stage->entry; diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 400b8a5..f48d887 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -268,8 +268,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) name, (uint32_t) stage->load, stage->memlen, stage->entry); - /* Stages rely the below clearing so that the bss is initialized. */ - memset((void *) (uint32_t) stage->load, 0, stage->memlen); final_size = cbfs_decompress(stage->compression, ((unsigned char *) stage) + @@ -279,6 +277,10 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) if (!final_size) return (void *) -1; + /* Stages rely the below clearing so that the bss is initialized. */ + memset((void *)((uintptr_t)stage->load + final_size), 0, + stage->memlen - final_size); + DEBUG("stage loaded.\n"); entry = stage->entry;

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coreboot-gerrit July 2013