coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: edb146e exynos5/5250: Update timer call sites to use monotonic timer API
by David Hendricks 03 May '13

03 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3176 -gerrit commit edb146eb7ae291a2c90a9c3c71a9a6ec5cc8f3bc Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu May 2 14:23:51 2013 -0700 exynos5/5250: Update timer call sites to use monotonic timer API This goes thru various call sites where we used timer_us() and updates them to use the new monotonic timer API. Change-Id: Ie2cc86a4125cf0de12837fd7d337a11aed25715c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 16 +++++++++------- src/cpu/samsung/exynos5-common/timer.c | 13 +++++++------ src/cpu/samsung/exynos5250/Makefile.inc | 2 ++ 3 files changed, 18 insertions(+), 13 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 00ff19e..59e74c0 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,7 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> -#include <time.h> +#include <timer.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -212,8 +212,8 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, struct video_info *video_info) { int timeout = 0; - u32 start, end; struct exynos5_dp *base = dp->base; + struct mono_time start, current, end; s5p_dp_config_video_slave_mode(dp, video_info); @@ -227,18 +227,20 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } - start = timer_us(); - end = start + STREAM_ON_TIMEOUT*1000; + timer_monotonic_get(&start); + end = current = start; + end.microseconds += STREAM_ON_TIMEOUT * 1000; do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { timeout++; break; } - } while (timer_us() < end); + timer_monotonic_get(&current); + } while (current.microseconds < end.microseconds); if (!timeout) { - printk(BIOS_ERR, "Video Clock Not ok after %uus.\n", - timer_us() - start); + printk(BIOS_ERR, "Video Clock Not ok after %ldus.\n", + end.microseconds - start.microseconds); return -ERR_VIDEO_CLOCK_BAD; } diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index ca15501..8736300 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -25,7 +25,7 @@ #include <common.h> #include <arch/io.h> -#include <time.h> +#include <timer.h> #include <console/console.h> #include <cpu/samsung/exynos5-common/pwm.h> #include <cpu/samsung/exynos5-common/clk.h> @@ -121,16 +121,17 @@ unsigned long timer_get_us(void) /* delay x useconds */ void udelay(unsigned long usec) { - unsigned long start; + struct mono_time start, current; - start = timer_us(); - if ((start + usec) < start){ + timer_monotonic_get(&start); + if ((start.microseconds + usec) < start.microseconds) { printk(BIOS_EMERG, "udelay: %08lx is impossibly large\n", usec); usec = 1000000; } - while ((timer_us() - start) < usec) - ; + current = start; + while (current.microseconds < start.microseconds + usec) + timer_monotonic_get(&current); } /* diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 73fc292..2cd3428 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += pinmux.c mct.c power.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c +bootblock-$(CONFIG_EARLY_CONSOLE) += monotonic_timer.c bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c @@ -17,6 +18,7 @@ romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c +romstage-y += monotonic_timer.c romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c

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New patch to review for coreboot: 1625f61 exynos5250: monotonic timer implementation (using MCT)
by David Hendricks 03 May '13

03 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3175 -gerrit commit 1625f612052c714620f1e244bc80ca9298128193 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu May 2 13:23:08 2013 -0700 exynos5250: monotonic timer implementation (using MCT) This implements the new monotonic timer API using the global multi-core timer (MCT). Change-Id: Id56249ff5d3e0f85808f5754954c83c0bc75f1c1 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 1 + src/cpu/samsung/exynos5250/clk.h | 2 + src/cpu/samsung/exynos5250/mct.c | 5 +-- src/cpu/samsung/exynos5250/monotonic_timer.c | 58 ++++++++++++++++++++++++++++ 4 files changed, 63 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 403c198..73fc292 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -30,6 +30,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c ramstage-y += exynos5250-tmu.c ramstage-y += mct.c +ramstage-y += monotonic_timer.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index 4785894..1894c00 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -585,4 +585,6 @@ int clock_get_mem_selection(enum ddr_mode *mem_type, unsigned *frequency_mhz, unsigned *arm_freq, enum mem_manuf *mem_manuf); +uint64_t mct_raw_value(void); + #endif diff --git a/src/cpu/samsung/exynos5250/mct.c b/src/cpu/samsung/exynos5250/mct.c index ddabbf7..4216643 100644 --- a/src/cpu/samsung/exynos5250/mct.c +++ b/src/cpu/samsung/exynos5250/mct.c @@ -88,7 +88,7 @@ static int enabled = 0; static struct mct_regs *const mct = (struct mct_regs *)MCT_ADDRESS; -static uint64_t timer_raw_value(void) +uint64_t mct_raw_value(void) { if (!enabled) { writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); @@ -109,9 +109,8 @@ void timer_start(void) u32 timer_us(void) { - uint64_t raw = timer_raw_value(); + uint64_t raw = mct_raw_value(); static uint32_t ticks_per_microsecond = MCT_HZ/1000000; uint32_t usec = raw / ticks_per_microsecond; return usec; } - diff --git a/src/cpu/samsung/exynos5250/monotonic_timer.c b/src/cpu/samsung/exynos5250/monotonic_timer.c new file mode 100644 index 0000000..f0444ce --- /dev/null +++ b/src/cpu/samsung/exynos5250/monotonic_timer.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <delay.h> +#include <timer.h> +#include <time.h> /* TODO: deprecate in favor of monotonic timer stuff */ + +#include "clk.h" + +static struct monotonic_counter { + int initialized; + struct mono_time time; + uint64_t last_value; +} mono_counter; + +static uint32_t clocks_per_usec = MCT_HZ/1000000; + +void timer_monotonic_get(struct mono_time *mt) +{ + uint64_t current_tick; + uint64_t usecs_elapsed; + + if (!mono_counter.initialized) { + init_timer(); + mono_counter.last_value = mct_raw_value(); + mono_counter.initialized = 1; + } + + current_tick = mct_raw_value(); + usecs_elapsed = (current_tick - mono_counter.last_value) / + clocks_per_usec; + + /* Update current time and tick values only if a full tick occurred. */ + if (usecs_elapsed) { + mono_time_add_usecs(&mono_counter.time, usecs_elapsed); + mono_counter.last_value = current_tick; + } + + /* Save result. */ + *mt = mono_counter.time; +}

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New patch to review for coreboot: a596d2a mainboard/asus/f2a85-m and mainboard/amd/thatcher: move UDELAY_LAPIC to cpu/amd/agesa/family15tn
by David Hubbard 03 May '13

03 May '13

David Hubbard (david.c.hubbard+coreboot(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3174 -gerrit commit a596d2ab79be2bd09010320f2c8643de1af13c06 Author: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Date: Thu May 2 17:25:02 2013 -0600 mainboard/asus/f2a85-m and mainboard/amd/thatcher: move UDELAY_LAPIC to cpu/amd/agesa/family15tn Stefan Reinauer suggested 'select UDELAY_LAPIC' did not belong in f2a85-m/Kconfig. It got there via copy-paste from thatcher/Kconfig so this commit removes the 'select UDELAY_LAPIC' from both of those and puts it in cpu/amd/agesa/family15tn/Kconfig Since f2a85-m is the only Thatcher board coreboot supports right now, this should not break any other boards. Change-Id: I5e25bafc437e69c22e8323a8d41459a258bfbc0a Signed-off-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> --- src/cpu/amd/agesa/family15tn/Kconfig | 1 + src/mainboard/amd/thatcher/Kconfig | 1 - src/mainboard/asus/f2a85-m/Kconfig | 1 - 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index d2f5a8c..57045cd 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -21,6 +21,7 @@ config CPU_AMD_AGESA_FAMILY15_TN bool select PCI_IO_CFG_EXT select X86_AMD_FIXED_MTRRS + select UDELAY_LAPIC config CPU_ADDR_BITS int diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 384390c..5a18e61 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -39,7 +39,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_SMSC_LPC47N217 select BOARD_ROMSIZE_KB_4096 select GFXUMA - select UDELAY_LAPIC config MAINBOARD_DIR string diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index e8f573e..20d79ec 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -40,7 +40,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_ITE_IT8712F select BOARD_ROMSIZE_KB_8192 select GFXUMA - select UDELAY_LAPIC choice prompt "DDR3 memory voltage"

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New patch to review for coreboot: 7f1362c src/cpu/amd/agesa/Kconfig: Use tabs instead of spaces for alignment
by Paul Menzel 02 May '13

02 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3173 -gerrit commit 7f1362c575b7122f60c20a6bbc55fe8b033796f8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu May 2 10:34:49 2013 +0200 src/cpu/amd/agesa/Kconfig: Use tabs instead of spaces for alignment Some entries still used spaces while others used tabulators. Convert spaces to tabs to uniformly use tabs. Change-Id: Iee80ad4a90e95b925afbb0c6adc563fa3a6503cf Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/agesa/Kconfig | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 5e99c7b..c660470 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -18,13 +18,13 @@ # config CPU_AMD_AGESA - bool - default y if CPU_AMD_AGESA_FAMILY10 - default y if CPU_AMD_AGESA_FAMILY12 - default y if CPU_AMD_AGESA_FAMILY14 - default y if CPU_AMD_AGESA_FAMILY15 - default y if CPU_AMD_AGESA_FAMILY15_TN - default n + bool + default y if CPU_AMD_AGESA_FAMILY10 + default y if CPU_AMD_AGESA_FAMILY12 + default y if CPU_AMD_AGESA_FAMILY14 + default y if CPU_AMD_AGESA_FAMILY15 + default y if CPU_AMD_AGESA_FAMILY15_TN + default n select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER

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New patch to review for coreboot: 4f37f6e cpu/amd/agesa/Kconfig: Select LAPIC_MONOTONIC_TIMER
by Paul Menzel 02 May '13

02 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3172 -gerrit commit 4f37f6e03f4b401625139ddef97c67051d488a71 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed May 1 16:36:56 2013 +0200 cpu/amd/agesa/Kconfig: Select LAPIC_MONOTONIC_TIMER Thanks to Aaron Durbin coreboot provides monotonic timers. Select the LAPIC monotonic timer for the AMD AGESA CPUs. The following is an excerpt from serial log of the ASRock E350M1. $ grep usec seriallog-20130502_100902.log 01.016: Root Device init 1578 usecs 01.029: CPU_CLUSTER: 0 init 112415 usecs 01.029: PCI: 00:00.0 init 3240 usecs 01.088: PCI: 00:01.0 init 104572 usecs 01.088: PCI: 00:01.1 init 1663 usecs 01.088: PCI: 00:11.0 init 1662 usecs 01.088: PCI: 00:14.0 init 1662 usecs 01.088: PCI: 00:14.3 init 8665 usecs 01.088: PCI: 00:14.4 init 1665 usecs 01.088: PCI: 00:18.0 init 1662 usecs 01.088: PCI: 00:18.1 init 1663 usecs 01.088: PCI: 00:18.2 init 1663 usecs 01.088: PCI: 00:18.3 init 1663 usecs 01.088: PCI: 00:18.4 init 1663 usecs 01.088: PCI: 00:18.5 init 1665 usecs 01.088: PCI: 00:18.6 init 1664 usecs 01.088: PCI: 00:18.7 init 1663 usecs 01.088: PNP: 002e.2 init 1576 usecs 01.088: PNP: 002e.5 init 1577 usecs 01.088: PNP: 002e.a init 1590 usecs 01.088: PNP: 002e.b init 30144 usecs 01.088: PCI: 03:00.0 init 1663 usecs So the graphics device needs around 100 ms for being initialized. The full serial log is in the Gerrit comments. Change-Id: Ia7b3012e51fcf94b0f22290cdef2b4424295ad6d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/agesa/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 7b2f2eb..5e99c7b 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,6 +27,7 @@ config CPU_AMD_AGESA default n select TSC_SYNC_LFENCE select UDELAY_LAPIC + select LAPIC_MONOTONIC_TIMER if CPU_AMD_AGESA

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Patch merged into coreboot/master: 3f39cd2 armv7: invalidate TLB entries as they are added/modified
by gerrit＠coreboot.org 01 May '13

01 May '13

the following patch was just integrated into master: commit 3f39cd2920ccc3286cda152f7abc08590ae49f66 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Apr 30 16:01:50 2013 -0700 armv7: invalidate TLB entries as they are added/modified The old approach was to invalidate the entire TLB every time we set up a table entry. This worked because we didn't turn the MMU on until after we had set everything up. This patch uses the TLBIMVAA wrapper to invalidate each entry as it's added/modified. Change-Id: I27654a543a2015574d910e15d48b3d3845fdb6d1 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3166 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Wed May 1 23:56:58 2013, giving +1 See http://review.coreboot.org/3166 for details. -gerrit

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Patch merged into coreboot/master: 5c2025c AMD Hudson A55E: Remove GEC firmware blob kconfig prompt
by gerrit＠coreboot.org 01 May '13

01 May '13

the following patch was just integrated into master: commit 5c2025c40f747c383e6106799f06c4a92cd07201 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Apr 23 14:31:55 2013 -0600 AMD Hudson A55E: Remove GEC firmware blob kconfig prompt The "gigabit ethernet controller" (GEC) block was added to AMD Hudson A55E to integrate ethernet capabilities into an AMD southbridge. The GEC is designed to work with B50610 and B50610M gigabit PHY chips from Broadcom. These parts may not be generally available in small quantities for embedded development. The GEC block requires an opaque firmware blob to function. The GEC blob is controlled by AMD and Broadcom and is not available from coreboot.org. This change removes GEC support from AMD Parmer and AMD Thatcher mainboards since these boards do not have the Broadcom PHY. AMD has requested that the GEC be hidden for Hudson FCH since the PHY parts are not generally available. This Kconfig option can make it appear that this is a viable and supported way to add Ethernet to an embedded board. It is possible to use the Hudson GEC block with other PHYs, but this requires development of a custom GEC blob and a custom Ethernet driver. A custom GEC blob has been developed for a Micrel PHY, but there is no accompanying driver. Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3127 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Build-Tested: build bot (Jenkins) at Fri Apr 26 08:03:17 2013, giving +1 Reviewed-By: Martin Roth <martin.roth(a)se-eng.com> at Wed May 1 23:49:05 2013, giving +2 See http://review.coreboot.org/3127 for details. -gerrit

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New patch to review for coreboot: b285a0f x86: harden tsc udelay() function
by Aaron Durbin 01 May '13

01 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3171 -gerrit commit b285a0fb0f72b6d4b8e7e39050c44e72d741ca96 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:55:14 2013 -0500 x86: harden tsc udelay() function Since the TSC udelay() fucntion can be used in SMM that means the TSC can count up to whatever value. The current loop was not handling TSC rollover properly. In most cases this should not matter as the TSC typically starts ticking at value 0, and it would take a very long time to roll it over. However, it is my understanding that this behavior is not guaranteed. Theoretically the TSC could start or be be written to with a large value that would cause the rollover. Change-Id: I2f11a5bc4f27d5543e74f8224811fa91e4a55484 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/tsc/delay_tsc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 0540496..0e2a9c0 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -172,18 +172,18 @@ static inline unsigned long get_clocks_per_usec(void) void udelay(unsigned us) { - unsigned long long count; - unsigned long long stop; - unsigned long long clocks; + unsigned long long start; + unsigned long long current; + unsigned long long clocks; + start = rdtscll(); clocks = us; clocks *= get_clocks_per_usec(); - count = rdtscll(); - stop = clocks + count; - while(stop > count) { + current = rdtscll(); + while((current - start) < clocks) { cpu_relax(); - count = rdtscll(); - } + current = rdtscll(); + } } #if CONFIG_TSC_MONOTONIC_TIMER && !defined(__PRE_RAM__) && !defined(__SMM__)

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Patch set updated for coreboot: f905c26 Asus F2A85-M Enable the SD controller for F2A85-M
by Rudolf Marek 01 May '13

01 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3167 -gerrit commit f905c26abf0673694be887271ef1326e791d9cfb Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Wed May 1 22:29:13 2013 +0200 Asus F2A85-M Enable the SD controller for F2A85-M If the SD controller is "off" hudson.c won't disable that because, there is no code for this yet. The PCI device is still visible and PCI BAR will be allocated by Linux. Unfortunately it may happen that the particular address is used by non-standard BAR for SPI controller. Change-Id: Ied7c581727541e2c81b0b1c2b70fd32de0014730 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 8272964..0014381 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -102,7 +102,8 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. device pci 14.5 on end # USB 2 device pci 14.6 off end # Gec - device pci 14.7 off end + # SD, make it on so the BAR is assigned (if proper hudson on/off handling is implemented this may go away) + device pci 14.7 on end device pci 15.0 on end # PCIe 0 - onboard PCIe 1x device pci 15.1 on end # PCIe 1 onboard gigabit device pci 15.2 off end # unused

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Patch set updated for coreboot: 0d9fe82 haswell: use tsc for udelay()
by Aaron Durbin 01 May '13

01 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3169 -gerrit commit 0d9fe82d753b3960b8105c9c7d9590330852f50f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:39:28 2013 -0500 haswell: use tsc for udelay() Instead of using the local apic timer for udelay() use the tsc. That way SMM, romstage, and ramstage all use the same delay functionality. Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 3 +- src/cpu/intel/haswell/Makefile.inc | 3 ++ src/cpu/intel/haswell/tsc_freq.c | 31 +++++++++++++++ src/northbridge/intel/haswell/Makefile.inc | 1 - src/northbridge/intel/haswell/udelay.c | 63 ------------------------------ 5 files changed, 36 insertions(+), 65 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 13861f9..152059f 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE select SMM_TSEG select SMM_MODULES select RELOCATABLE_MODULES diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 90ffd66..60c061d 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,7 +1,9 @@ ramstage-y += haswell_init.c subdirs-y += ../../x86/name ramstage-y += mp_init.c +ramstage-y += tsc_freq.c romstage-y += romstage.c +romstage-y += tsc_freq.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c @@ -10,6 +12,7 @@ ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc diff --git a/src/cpu/intel/haswell/tsc_freq.c b/src/cpu/intel/haswell/tsc_freq.c new file mode 100644 index 0000000..0a78053 --- /dev/null +++ b/src/cpu/intel/haswell/tsc_freq.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include "cpu/intel/haswell/haswell.h" + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff); +} diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 896360d..b2ac85e 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail diff --git a/src/northbridge/intel/haswell/udelay.c b/src/northbridge/intel/haswell/udelay.c deleted file mode 100644 index f5d541e..0000000 --- a/src/northbridge/intel/haswell/udelay.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include "cpu/intel/haswell/haswell.h" - -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_PLATFORM_INFO); - divisor = (msr.lo >> 8) & 0xff; - - d = HASWELL_BCLK * divisor; - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); -}

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coreboot-gerrit May 2013