coreboot-gerrit May 2013

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Patch set updated for coreboot: bfce376 x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c`
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3184 -gerrit commit bfce37648fb41c84f8f5cc785136fbabaec0533c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:49:41 2013 +0200 x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c` Moving the code from the southbridges to `src/arch/x86/lib/ioapic.c` all boards using the function `set_ioapic_id()` get the debug feature. Change-Id: Ic59c4c2213ed97bdf3798b3dc6e7cecc30e135d8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/lib/ioapic.c | 6 ++++++ src/southbridge/intel/bd82x6x/lpc.c | 6 ------ src/southbridge/intel/i82801gx/lpc.c | 7 ------- src/southbridge/intel/lynxpoint/lpc.c | 6 ------ 4 files changed, 6 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 8528dd8..cc35ae3 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -90,6 +90,12 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | (ioapic_id << 24)); } + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); + } static void load_vectors(u32 ioapic_base) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 181d36c..70a41a4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -60,7 +60,6 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -69,11 +68,6 @@ static void i82801gx_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index afd9a33..6785456 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -60,15 +60,8 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; - set_ioapic_id(IO_APIC_ADDR, 0x02); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 72347dc..5808222 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -64,7 +64,6 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -73,11 +72,6 @@ static void i82801gx_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ }

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Patch set updated for coreboot: 795e282 Intel 82801Gx: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3181 -gerrit commit 795e28281bd2ba9cf2282ea2bd032c1321965f01 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:40:23 2013 +0200 Intel 82801Gx: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 58 +++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 777a6d7..afd9a33 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -39,37 +39,38 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static void i82801gx_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) { - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ + /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} - *ioapic_index = 0; - *ioapic_data = (2 << 24); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) +{ + int i; - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + set_ioapic_id(IO_APIC_ADDR, 0x02); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); + + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void i82801gx_enable_serial_irqs(struct device *dev) @@ -421,8 +422,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + i82801gx_enable_acpi(dev); + /* IO APIC initialization. */ - i82801gx_enable_apic(dev); + i82801gx_enable_ioapic(dev); i82801gx_enable_serial_irqs(dev);

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Patch set updated for coreboot: 5e3a352 x86 I/O APIC: Make functions `io_apic_{read, write}()` public
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3180 -gerrit commit 5e3a35270f9263e5d8e41944ac115a990437594b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:34:43 2013 +0200 x86 I/O APIC: Make functions `io_apic_{read,write}()` public Some LPC initialiation can save some lines of code when being able to use the functions `io_apic_read()` and `io_apic_write()`. Change-Id: Id600007573ff011576967339cc66e6c883a2ed5a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/include/arch/ioapic.h | 2 ++ src/arch/x86/lib/ioapic.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index b989e52..8463269 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -39,6 +39,8 @@ #define SMI (2 << 8) #define INT (1 << 8) +void io_apic_read(u32 ioapic_base, u32 reg); +void io_apic_write(u32 ioapic_base, u32 reg, u32 value); void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 389c48c..8528dd8 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -22,13 +22,13 @@ #include <console/console.h> #include <cpu/x86/lapic.h> -static u32 io_apic_read(u32 ioapic_base, u32 reg) +void u32 io_apic_read(u32 ioapic_base, u32 reg) { write32(ioapic_base, reg); return read32(ioapic_base + 0x10); } -static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) +void io_apic_write(u32 ioapic_base, u32 reg, u32 value) { write32(ioapic_base, reg); write32(ioapic_base + 0x10, value);

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Patch set updated for coreboot: 0e845c3 Intel BD82x6x: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3183 -gerrit commit 0e845c38d0d9d2ae118afe61e4ca1c78af3b2a66 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:23:39 2013 +0200 Intel BD82x6x: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/bd82x6x/lpc.c | 65 +++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7bcadc9..181d36c 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -39,43 +39,43 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -537,8 +537,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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Patch set updated for coreboot: f9d8986 Intel Lynx Point: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3182 -gerrit commit f9d8986298462630b7ad15097dd7e13d85cbc18d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:17:02 2013 +0200 Intel Lynx Point: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/lpc.c | 65 ++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 40e0468..72347dc 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -43,43 +43,43 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -546,8 +546,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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New patch to review for coreboot: 79e074b Lenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM console
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3187 -gerrit commit 79e074b31e47dfd5e90e32e78a35f467860d301f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Apr 29 23:21:07 2013 +0200 Lenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM console Add code to support `EARLY_CBMEM_INIT` needed for CBMEM console support by copying GNUtoo’s commit for the Lenovo ThinkPad X60. commit 4560ca5003fe38a066616e8de1a8a414284750fd Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Apr 26 12:21:41 2013 +0200 Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support. Reviewed-on: http://review.coreboot.org/3142 Change-Id: I0c4ca5a5e60f4bb3b91653a133ec71039fcca6ab Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/t60/Kconfig | 1 + src/mainboard/lenovo/t60/romstage.c | 16 ++++++++++------ 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 379d1ec..952004b 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + select EARLY_CBMEM_INIT config MAINBOARD_DIR string default lenovo/t60 diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 5e11613..16971fc 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -29,6 +29,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -203,12 +204,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0, dock_err; + int cbmem_was_initted; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; if (bist == 0) @@ -314,14 +314,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; -#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + cbmem_was_initted = !cbmem_initialize(); +#if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption @@ -336,4 +335,9 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif + +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif }

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New patch to review for coreboot: 2fbcf17 nvramtool: Use CMOS_SIZE for cmos size
by Patrick Georgi 03 May '13

03 May '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3186 -gerrit commit 2fbcf176a67756b73a2de2564c7279f5a9787582 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 11 12:32:32 2013 +0200 nvramtool: Use CMOS_SIZE for cmos size We write CMOS data to 128 byte files, which is a problem when using them later-on (eg. as part of a coreboot image) where nvramtool assumes them to be 256 byte, and so data corruption occurs. Change-Id: Ibc919c95f6d522866b21fd313ceb023e73d09fb9 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- util/nvramtool/cli/nvramtool.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index 76d5cbb..d5acc58 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -162,8 +162,8 @@ int main(int argc, char *argv[]) exit(1); } - if (fd_stat.st_size < 128) { - lseek(fd, 127, SEEK_SET); + if (fd_stat.st_size < CMOS_SIZE) { + lseek(fd, CMOS_SIZE - 1, SEEK_SET); if (write(fd, "\0", 1) != 1) { fprintf(stderr, "Unable to extended '%s' to its full size.\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param); @@ -176,7 +176,7 @@ int main(int argc, char *argv[]) #endif } - cmos_default = mmap(NULL, 128, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + cmos_default = mmap(NULL, CMOS_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); if (cmos_default == MAP_FAILED) { fprintf(stderr, "Couldn't map '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param); exit(1);

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New patch to review for coreboot: 17fd84e Lenovo ThinkPad X60: Clean up `romstage.c`
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3185 -gerrit commit 17fd84e40ca80e8dd2a989fc1c4ecaa16ef0b983 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Apr 29 23:05:44 2013 +0200 Lenovo ThinkPad X60: Clean up `romstage.c` 1. Move comment for console init to correct place. 2. Start output with capital letter and add full stop at the end. 3. Add missing »)« at the end of description of GPIO 10. 4. Use tabulators instead of spaces. 5. Indent the code automatically using GNU indent [1] with the `-sc` switch adding stars in front of comment blocks as the good indent manual documents. $ indent -linux -sc src/mainboard/lenovo/x60/romstage.c Leave the numbers left aligned as it is more beneficial to be able to run indent without adapting the result afterward. [1] http://www.coreboot.org/Development_Guidelines#Coding_Style Change-Id: I2fa018ec28ff19d23d68754b565c13a7d7a57355 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/romstage.c | 68 ++++++++++++++++++++----------------- 1 file changed, 36 insertions(+), 32 deletions(-) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 0acf3a2..222b999 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -43,28 +43,28 @@ void setup_ich7_gpios(void) printk(BIOS_DEBUG, " GPIOS..."); /* X60 GPIO: - 1: HDD_PRESENCE# - 6: Unknown (Pulled high by R215 to VCC3B) - 7: BDC_PRESENCE# - 8: H8_WAKE# - 9: RTC_BAT_IN# - 10: Unknown (Pulled high by R700 to VCC3M - 12: H8SCI# - 13: SLICE_ON_3M# - 14: Unknown (Pulled high by R321 to VCC3) - 15: Unknown (Pulled high by R258 to VCC3) - 19: Unknown (Pulled low by R594) - 21: Unknown (Pulled high by R145 to VCC3) - 22: FWH_WP# - 25: MDC_KILL# - 33: HDD_PRESENCE_2# - 35: CLKREQ_SATA# - 36: PLANARID0 - 37: PLANARID1 - 38: PLANARID2 - 39: PLANARID3 - 48: FWH_TBL# - */ + * 1: HDD_PRESENCE# + * 6: Unknown (Pulled high by R215 to VCC3B) + * 7: BDC_PRESENCE# + * 8: H8_WAKE# + * 9: RTC_BAT_IN# + * 10: Unknown (Pulled high by R700 to VCC3M) + * 12: H8SCI# + * 13: SLICE_ON_3M# + * 14: Unknown (Pulled high by R321 to VCC3) + * 15: Unknown (Pulled high by R258 to VCC3) + * 19: Unknown (Pulled low by R594) + * 21: Unknown (Pulled high by R145 to VCC3) + * 22: FWH_WP# + * 25: MDC_KILL# + * 33: HDD_PRESENCE_2# + * 35: CLKREQ_SATA# + * 36: PLANARID0 + * 37: PLANARID1 + * 38: PLANARID2 + * 39: PLANARID3 + * 48: FWH_TBL# + */ outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ @@ -107,7 +107,7 @@ static void early_superio_config(void) pnp_write_config(dev, 0x29, 0x06); - while(!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) + while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) udelay(1000); /* Enable COM1 */ @@ -146,7 +146,7 @@ static void rcba_config(void) /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD; - RCBA32(0x3418) |= (1 << 0); // Required. + RCBA32(0x3418) |= (1 << 0); // Required. /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ RCBA32(0x1e84) = 0x00020001; @@ -236,18 +236,20 @@ void main(unsigned long bist) if (dock_present()) { dock_connect(); early_superio_config(); - /* Set up the console */ } + /* Set up the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + printk(BIOS_DEBUG, + "Soft reset detected, rebooting properly.\n"); outb(0x6, 0xcf9); - while (1) asm("hlt"); + while (1) + asm("hlt"); } /* Perform some early chipset initialization required @@ -302,7 +304,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); @@ -329,15 +331,17 @@ void main(unsigned long bist) * day. */ if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, + HIGH_MEMORY_SAVE); /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, + SKPAD_ACPI_S3_MAGIC); } #endif #if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); + /* Keep this the last thing this function does. */ + cbmemc_reinit(); #endif }

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Patch set updated for coreboot: a5f2c6f x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c`
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3184 -gerrit commit a5f2c6f0b981237b5e0a713829b220a31abbdbc4 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:49:41 2013 +0200 x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c` Moving the code from the southbridges to `src/arch/x86/lib/ioapic.c` all boards using the function `set_ioapic_id()` get the debug feature. Change-Id: Ic59c4c2213ed97bdf3798b3dc6e7cecc30e135d8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/lib/ioapic.c | 6 ++++++ src/southbridge/intel/bd82x6x/lpc.c | 6 ------ src/southbridge/intel/i82801gx/lpc.c | 7 ------- src/southbridge/intel/lynxpoint/lpc.c | 6 ------ 4 files changed, 6 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 8528dd8..cc35ae3 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -90,6 +90,12 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | (ioapic_id << 24)); } + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); + } static void load_vectors(u32 ioapic_base) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 181d36c..70a41a4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -60,7 +60,6 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -69,11 +68,6 @@ static void i82801gx_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index afd9a33..6785456 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -60,15 +60,8 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; - set_ioapic_id(IO_APIC_ADDR, 0x02); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 72347dc..5808222 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -64,7 +64,6 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -73,11 +72,6 @@ static void i82801gx_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ }

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Patch set updated for coreboot: 4de2804 Intel 82801Gx: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3181 -gerrit commit 4de2804ce6936ccb4efa3ab9ad9b2061380acefe Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:40:23 2013 +0200 Intel 82801Gx: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 58 +++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 777a6d7..afd9a33 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -39,37 +39,38 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static void i82801gx_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) { - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ + /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} - *ioapic_index = 0; - *ioapic_data = (2 << 24); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) +{ + int i; - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + set_ioapic_id(IO_APIC_ADDR, 0x02); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); + + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void i82801gx_enable_serial_irqs(struct device *dev) @@ -421,8 +422,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + i82801gx_enable_acpi(dev); + /* IO APIC initialization. */ - i82801gx_enable_apic(dev); + i82801gx_enable_ioapic(dev); i82801gx_enable_serial_irqs(dev);

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coreboot-gerrit May 2013