coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 255a75e Asus F2A85-M Verb Table for ALC887-VD
by Rudolf Marek 03 May '13

03 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3170 -gerrit commit 255a75edb7053f4ff81279193521942c367356b4 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue Apr 2 20:51:15 2013 +0200 Asus F2A85-M Verb Table for ALC887-VD Verbs taken from /sys/class/sound/hwC1D0/init_pin_configs Change-Id: I17fa2d4ab1e1a6bfd84de94e9e4a91bd67b6a0c0 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 38 +++++++++++++++---------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index f976001..050a8cc 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -63,29 +63,29 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /** - * AMD Thatcher Platform ALC272 Verb Table + * Verb Table for ALC887-VD, listed from /sys/class/sound/hwC1D0/init_pin_configs */ -const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, - {0x12, 0x411111F0}, - {0x13, 0x411111F0}, - {0x14, 0x411111F0}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x17, 0x411111F0}, - {0x18, 0x01a19840}, - {0x19, 0x411111F0}, - {0x1a, 0x01813030}, - {0x1b, 0x411111F0}, - {0x1d, 0x40130605}, - {0x1e, 0x01441120}, - {0x21, 0x01211010}, +const CODEC_ENTRY alc887_VerbTbl[] = { + {0x11, 0x99430140}, + {0x12, 0x411111f0}, + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01012014}, + {0x18, 0x01a19850}, + {0x19, 0x02a19c60}, + {0x1a, 0x0181305f}, + {0x1b, 0x02214c20}, + {0x1c, 0x411111f0}, + {0x1d, 0x4005e601}, + {0x1e, 0x01456130}, + {0x1f, 0x411111f0}, {0xff, 0xffffffff} }; -const CODEC_TBL_LIST ThatcherCodecTableList[] = +static const CODEC_TBL_LIST CodecTableList[] = { - {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, + {0x10ec0887, (CODEC_ENTRY*)&alc887_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} }; @@ -110,7 +110,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); /* Azalia Controller Front Panel OEM Table Pointer */ FchParams_env->Imc.ImcEnable = FALSE; FchParams_env->Hwm.HwMonitorEnable = FALSE;

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New patch to review for coreboot: 3b74afe Asus F2A85-M Cleanup the PCIe config
by Rudolf Marek 03 May '13

03 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3194 -gerrit commit 3b74afe4b80e19ee62e3791bdffc539114b52f13 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat May 4 00:08:34 2013 +0200 Asus F2A85-M Cleanup the PCIe config Document the lane assignment from BKDG datasheet. Assign the lanes correctly to the physical slots on the motherboard. UMI is connected to SB via 4x PCIe bridge 8 blue x16 slot is not shared with DDI and is routed through PCIe bridge 2 black x86 slot is fact x4 slot and uses all 4 GPP from CPU Assume that DDI is on out-of-PCIe-band lanes. Change sizeof(type) * 6 to sizeof(variable). I think the cleanup part may be applied to other boards. Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR? Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 133 ++++++++++----------- .../asus/f2a85-m/PlatformGnbPcieComplex.h | 40 ------- 2 files changed, 65 insertions(+), 108 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 8ee6707..e47c7bf 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -26,58 +26,75 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE +/* + +From fam15h BKDG: Table 45: Lane Id Mapping + +Lane Id +0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 +1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 +2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 +3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 +4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 +5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 +6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 +7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 +8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI +9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI +10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI +11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI +12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI +13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI +14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI +15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI +16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI +17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI +18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI +19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI +20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI +21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI +22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI +23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI +24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) +25 DP0_TX[P,N]1 +26 DP0_TX[P,N]2 +27 DP0_TX[P,N]3 +28 DP1_TX[P,N]0 +29 DP1_TX[P,N]1 +30 DP1_TX[P,N]2 +31 DP1_TX[P,N]3 +32 DP2_TX[P,N]0 +33 DP2_TX[P,N]1 +34 DP2_TX[P,N]2 +35 DP2_TX[P,N]3 +36 DP2_TX[P,N]4 +37 DP2_TX[P,N]5 +38 DP2_TX[P,N]6 +*/ + PCIe_PORT_DESCRIPTOR PortList [] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + /* PCIe port, Lanes 8:23, PCI Device Number 2 blue x16 slot */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 16:23, PCI Device Number 3 */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ + /* PCIe port, Lanes 4, PCI Device Number 4, black x16 slot (in fact x4) */ { 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - - /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/ - { - 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - -#if 1 - /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 4 UMI link to SB, PCI Device Number 8 */ { DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, -#endif }; + /* this is not known if it is completely correct VGA/DVI works, HDMI untested */ + PCIe_DDI_DESCRIPTOR DdiList [] = { // DP0 to HDMI0/DP { @@ -94,29 +111,9 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { // DP2 to HDMI1/DP { 0, -// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38), PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) }, - // GFX Lane 15-12 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) - }, - // GFX Lane 11-8 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) - }, - // GFX Lane 7-4 - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) - } }; PCIe_COMPLEX_DESCRIPTOR Trinity = { @@ -159,9 +156,9 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + AllocHeapParams.RequestedBufferSize = sizeof (Trinity) + + sizeof (DdiList) + + sizeof (PortList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -174,33 +171,33 @@ OemCustomizeInitEarly ( TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof (Trinity); TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + AllocHeapParams.BufferPtr += sizeof (PortList); TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (TrinityPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof (Trinity), &InitEarly->StdHeader); LibAmdMemFill (TrinityPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 7, + sizeof (PortList), &InitEarly->StdHeader); LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 6, + sizeof (DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (Trinity), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PortList), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (DdiList), &InitEarly->StdHeader); - ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; } diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h index 3f14805..b3c69cf 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h @@ -24,46 +24,6 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly

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Patch merged into coreboot/master: a98d306 nvramtool: Use CMOS_SIZE for cmos size
by gerrit＠coreboot.org 03 May '13

03 May '13

the following patch was just integrated into master: commit a98d3061e9e85be2f924850860e76f07cfc5af37 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 11 12:32:32 2013 +0200 nvramtool: Use CMOS_SIZE for cmos size We write CMOS data to 128 byte files, which is a problem when using them later-on (eg. as part of a coreboot image) where nvramtool assumes them to be 256 byte, and so data corruption occurs. Change-Id: Ibc919c95f6d522866b21fd313ceb023e73d09fb9 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/3186 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri May 3 16:38:17 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sat May 4 00:14:09 2013, giving +2 See http://review.coreboot.org/3186 for details. -gerrit

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New patch to review for coreboot: 386b7cb cooperative multitasking example
by Aaron Durbin 03 May '13

03 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3193 -gerrit commit 386b7cbf3b6211492f8c3d67cf36f657d149aef7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 3 16:13:28 2013 -0500 cooperative multitasking example Change-Id: I68c60f2cfd45f53bc1cd6b7b05d438762bc8f691 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/hardwaremain.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 9f16e06..36eed75 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -496,3 +496,22 @@ void hardwaremain(int boot_complete) die("Boot state machine failure.\n"); } +static void test_thread(void *id) +{ + const char *str = id; + int i = 10; + + while (i != 0) { + printk(BIOS_DEBUG, "mark from %s\n", str); + mdelay(5); + i--; + } +} + + +BOOT_STATE_INIT_ENTRIES(tests_threads) = { + BOOT_STATE_INIT_ENTRY_RAMSTAGE_EXIT(BS_PRE_DEVICE, BS_ON_ENTRY, + test_thread, (void *)"thread 0"), + BOOT_STATE_INIT_ENTRY_RAMSTAGE_EXIT(BS_PRE_DEVICE, BS_ON_ENTRY, + test_thread, (void *)"thread 1"), +};

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New patch to review for coreboot: dfdfae8 x86: implement cooperative multi-tasking
by Aaron Durbin 03 May '13

03 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3192 -gerrit commit dfdfae88ec05b81c9c43185e3b0ec22a0f8948a9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 3 16:03:20 2013 -0500 x86: implement cooperative multi-tasking The cooperative multitasking support allows for callbacks and the boostate machine to be ran cooperatively. There is a concept of threads, but they aren't threads in the traditional sense. They are really a container for execution context by way of the stack. A configurable number of threads are available to the system. The cooperative scheduling works by using udelay() as an exit point to start resume another thread of execution. The "main thread" never yields unless running timers or new threads. The main thread is the initial thread running on the boot cpu. In this manner it is possible to still write serialized code sequences without having to hand-write a state machine using the existing callbacks. Change-Id: I9e73495a1814a0b8a8dfc9f265cd83c29a305f13 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 16 ++ src/arch/x86/include/arch/cpu.h | 5 + src/arch/x86/lib/Makefile.inc | 2 + src/arch/x86/lib/c_start.S | 9 + src/arch/x86/lib/thread.c | 330 +++++++++++++++++++++++++++++++++++++ src/arch/x86/lib/thread_switch.S | 58 +++++++ src/cpu/intel/haswell/mp_init.c | 2 + src/cpu/x86/lapic/apic_timer.c | 4 + src/cpu/x86/lapic/lapic_cpu_init.c | 2 + src/cpu/x86/tsc/delay_tsc.c | 4 + src/include/thread.h | 60 +++++++ src/lib/hardwaremain.c | 14 +- src/lib/timer_queue.c | 10 +- 13 files changed, 512 insertions(+), 4 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index ce7f400..9fde0e4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -324,6 +324,22 @@ config TIMER_QUEUE help Provide a timer queue for performing time-based callbacks. +config COOP_MULTITASKING + def_bool n + depends on TIMER_QUEUE && ARCH_X86 + help + Cooperative multitasking allows callbacks to be multiplexed on the + main thread of ramstage. With this enabled it allows for multiple + execution paths to take place when they have udelay() calls within + their code. + +config NUM_THREADS + int + default 4 + depends on COOP_MULTITASKING + help + How many execution threads to cooperatively multitask with. + config HIGH_SCRATCH_MEMORY_SIZE hex default 0x0 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index a3555d8..4a31088 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -164,9 +164,14 @@ struct cpu_driver *find_cpu_driver(struct device *cpu); #include <arch/io.h> #endif +struct thread; + struct cpu_info { device_t cpu; unsigned int index; +#if CONFIG_COOP_MULTITASKING + struct thread *thread; +#endif }; static inline struct cpu_info *cpu_info(void) diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 82f4e62..7cdd3c6 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -9,6 +9,8 @@ ramstage-y += memset.c ramstage-y += memcpy.c ramstage-y += ebda.c ramstage-y += rom_media.c +ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c +ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S romstage-$(CONFIG_EARLY_CONSOLE) += romstage_console.c romstage-y += cbfs_and_run.c diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index 32af0cc..e9d072f 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -10,6 +10,11 @@ _stack: .space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE _estack: +#if CONFIG_COOP_MULTITASKING +.global thread_stacks +thread_stacks: +.space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS +#endif .section ".textfirst", "ax", @progbits .code32 @@ -45,6 +50,10 @@ _start: /* set new stack */ movl $_estack, %esp +#if CONFIG_COOP_MULTITASKING + /* Push the thread pointer. */ + pushl $0 +#endif /* Push the cpu index and struct cpu */ pushl $0 pushl $0 diff --git a/src/arch/x86/lib/thread.c b/src/arch/x86/lib/thread.c new file mode 100644 index 0000000..bcc297c --- /dev/null +++ b/src/arch/x86/lib/thread.c @@ -0,0 +1,330 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stddef.h> +#include <stdint.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <thread.h> + +#define TOTAL_NUM_THREADS (CONFIG_NUM_THREADS + 1) +extern void asmlinkage switch_to_thread(uintptr_t new_stack, + uintptr_t *saved_stack); +extern char thread_stacks[CONFIG_NUM_THREADS*CONFIG_STACK_SIZE]; + +struct thread { + int id; + uintptr_t saved_stack; + char *stack_top; + struct thread *next; + struct timeout_callback tocb; + void (*entry)(void *); + void *entry_arg; + int can_yield; +}; + +struct pushad_regs { + uint32_t edi; + uint32_t esi; + uint32_t ebp; + uint32_t esp; + uint32_t ebx; + uint32_t edx; + uint32_t ecx; + uint32_t eax; +}; + +static struct thread *runnable_threads; +static struct thread *free_threads; +static struct thread all_threads[TOTAL_NUM_THREADS]; + +static inline struct cpu_info *thread_cpu_info(const struct thread *t) +{ + return (void *)(t->stack_top - sizeof(struct cpu_info)); +} + +static inline int cpu_info_can_switch(const struct cpu_info *ci) +{ + return (ci->thread != NULL); +} + +static inline int thread_is_main(const struct thread *t) +{ + return t->id == 0; +} + +/* Assumes current cpu info can switch. */ +static struct thread *cpu_info_to_thread(const struct cpu_info *ci) +{ + return ci->thread; +} + +static inline struct thread *get_main_thread(void) +{ + return &all_threads[0]; +} + +static inline struct thread *current_thread(void) +{ + return cpu_info_to_thread(cpu_info()); +} + +static inline int thread_list_empty(struct thread **list) +{ + return *list == NULL; +} + +static inline struct thread *pop_thread(struct thread **list) +{ + struct thread *t; + + t = *list; + *list = t->next; + t->next = NULL; + return t; +} + +static inline void push_thread(struct thread **list, struct thread *t) +{ + t->next = *list; + *list = t; +} + +static inline struct thread *get_free_thread(void) +{ + struct thread *t; + struct cpu_info *ci; + struct cpu_info *new_ci; + + if (thread_list_empty(&free_threads)) + return NULL; + + t = pop_thread(&free_threads); + + ci = cpu_info(); + + /* The BSP is the only one that can switch threads. Therefore, only + * initialize the device_t and thread pointer. */ + new_ci = thread_cpu_info(t); + new_ci->cpu = ci->cpu; + new_ci->thread = t; + + return t; +} + +static inline void free_thread(struct thread *t) +{ + push_thread(&free_threads, t); +} + +void threads_initialize(void) +{ + int i; + struct thread *t; + char *stack_top; + struct cpu_info *ci; + + /* Initialize the BSP thread first. */ + t = &all_threads[0]; + ci = cpu_info(); + ci->thread = t; + t->stack_top = (void *)&ci[1]; + t->id = 0; + + stack_top = &thread_stacks[CONFIG_STACK_SIZE]; + for (i = 1; i < TOTAL_NUM_THREADS; i++) { + t = &all_threads[i]; + t->stack_top = stack_top; + t->id = i; + stack_top += CONFIG_STACK_SIZE; + free_thread(t); + } +} + +#if 0 +static void debug_thread_dump(const char *str, const struct thread *t, + uintptr_t stack_start) +{ + printk(BIOS_DEBUG, "%s: thread[%d] stack @%x -> %p\n", str, t->id, + stack_start, t->stack_top); + + int i; + uint32_t *slot; + uint32_t *end; + + slot = (void *)t->stack_top; + slot--; + end = (void *)stack_start; + end--; + i = (uintptr_t)t->stack_top - stack_start; + i -= sizeof(slot); + + while (slot != end) { + printk(BIOS_DEBUG, "%04x: %08x\n", i, *slot); + slot--; + i -= sizeof(*slot); + } +} +#endif + +static void schedule(struct thread *t) +{ + struct thread *current; + + current = current_thread(); + + /* If t is NULL need to find new runnable thread. */ + if (t == NULL) { + if (thread_list_empty(&runnable_threads)) + die("Runnable thread list is empty!\n"); + t = pop_thread(&runnable_threads); + switch_to_thread(t->saved_stack, &current->saved_stack); + } else { + push_thread(&runnable_threads, current); + switch_to_thread(t->saved_stack, &current->saved_stack); + } +} + +static void terminate_thread(struct thread *t) +{ + free_thread(t); + schedule(NULL); +} + +static void asmlinkage call_wrapper(struct thread *t) +{ + t->entry(t->entry_arg); + terminate_thread(t); +} + +static inline uintptr_t push_stack(uintptr_t cur_stack, uintptr_t value) +{ + uintptr_t *addr; + + cur_stack -= sizeof(value); + addr = (uintptr_t *)cur_stack; + *addr = value; + return cur_stack; +} + +static uintptr_t prepare_thread(struct thread *t, void *func, void *arg) +{ + uintptr_t stack; + + stack = (uintptr_t)thread_cpu_info(t); + + /* Stash the function and argument to run. */ + t->entry = func; + t->entry_arg = arg; + + /* All new threads can yield by default. */ + t->can_yield = 1; + + /* Imitate call_wrapper(t) with return address of 0. call_wrapper() + * will never return through the stack as it will call + * terminate_thread().*/ + stack = push_stack(stack, (uintptr_t)t); + stack = push_stack(stack, (uintptr_t)0); + stack = push_stack(stack, (uintptr_t)call_wrapper); + /* Make room for the registers. Ignore intial values. */ + stack -= sizeof(struct pushad_regs); + + return stack; +} + +int thread_run(void (*func)(void *), void *arg) +{ + struct thread *current; + struct cpu_info *ci; + struct thread *t; + + ci = cpu_info(); + + if (!cpu_info_can_switch(ci)) { + printk(BIOS_ERR, "thread_run(): non-switchable cpu: %d\n", + ci->index); + return -1; + } + + current = cpu_info_to_thread(ci); + t = get_free_thread(); + + if (t == NULL) { + printk(BIOS_ERR, "thread_run() No more threads!\n"); + return -1; + } + + t->saved_stack = prepare_thread(t, func, arg); + schedule(t); + + return 0; +} + +void thread_resume(struct timeout_callback *tocb) +{ + struct thread *to; + struct thread *current; + + current = current_thread(); + to = tocb->priv; + schedule(to); +} + +int thread_yield_for(unsigned microsecs) +{ + struct thread *current; + struct cpu_info *ci; + + ci = cpu_info(); + + if (!cpu_info_can_switch(ci)) + return -1; + current = cpu_info_to_thread(ci); + + /* By default thread_yield_for() will not yield the main thread. */ + if (thread_is_main(current) || !current->can_yield) + return -1; + + current->tocb.priv = current; + current->tocb.callback = thread_resume; + + if (timer_sched_callback(&current->tocb, microsecs)) + return -1; + + schedule(NULL); + + return 0; +} + +void thread_cooperate(void) +{ + struct thread *current; + + current = current_thread(); + + current->can_yield = 1; +} + +void thread_prevent_coop(void) +{ + struct thread *current; + + current = current_thread(); + + current->can_yield = 0; +} diff --git a/src/arch/x86/lib/thread_switch.S b/src/arch/x86/lib/thread_switch.S new file mode 100644 index 0000000..8de1948 --- /dev/null +++ b/src/arch/x86/lib/thread_switch.S @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +.code32 +.text + +/* + * stack layout after pushad: + * +------------+ + * | save stack | <-- esp + 0x28 + * +------------+ + * | new stack | <-- esp + 0x24 + * +------------+ + * | ret addr | <-- esp + 0x20 + * +------------+ + * | eax | <-- esp + 0x1c + * +------------+ + * | ecx | <-- esp + 0x18 + * +------------+ + * | edx | <-- esp + 0x14 + * +------------+ + * | ebx | <-- esp + 0x10 + * +------------+ + * | orig esp | <-- esp + 0x0c + * +------------+ + * | ebp | <-- esp + 0x08 + * +------------+ + * | esi | <-- esp + 0x04 + * +------------+ + * | edi | <-- esp + 0x00 + * +------------+ + */ +.globl switch_to_thread +switch_to_thread: + pusha + /* Save the current stack */ + movl 0x28(%esp), %ebx + movl %esp, (%ebx) + /* Switch to the new stack. */ + movl 0x24(%esp), %eax + movl %eax, %esp + popa + ret diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index ddcff6c..f7623db 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -36,6 +36,7 @@ #include <lib.h> #include <smp/atomic.h> #include <smp/spinlock.h> +#include <thread.h> #include "haswell.h" /* This needs to match the layout in the .module_parametrs section. */ @@ -164,6 +165,7 @@ ap_init(unsigned int cpu, void *microcode_ptr) info = cpu_info(); info->index = cpu; info->cpu = cpu_devs[cpu]; + thread_init_cpu_info_non_bsp(info); apic_id_table[info->index] = lapicid(); info->cpu->path.apic.apic_id = apic_id_table[info->index]; diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 749fef0..954e324 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <console/console.h> #include <delay.h> +#include <thread.h> #include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/car.h> @@ -95,6 +96,9 @@ void udelay(u32 usecs) { u32 start, value, ticks; + if (!thread_yield_for(usecs)) + return; + if (!timer_fsb || (lapic_read(LAPIC_LVTT) & (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) != (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 69430d5..fbc8aa4 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -32,6 +32,7 @@ #include <smp/spinlock.h> #include <cpu/cpu.h> #include <cpu/intel/speedstep.h> +#include <thread.h> #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 /* This is a lot more paranoid now, since Linux can NOT handle @@ -292,6 +293,7 @@ int start_cpu(device_t cpu) info = (struct cpu_info *)stack_end; info->index = index; info->cpu = cpu; + thread_init_cpu_info_non_bsp(info); /* Advertise the new stack and index to start_cpu */ secondary_stack = stack_end; diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 0e2a9c0..c648119 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -4,6 +4,7 @@ #include <cpu/x86/tsc.h> #include <smp/spinlock.h> #include <delay.h> +#include <thread.h> #if !defined(__PRE_RAM__) @@ -176,6 +177,9 @@ void udelay(unsigned us) unsigned long long current; unsigned long long clocks; + if (!thread_yield_for(us)) + return; + start = rdtscll(); clocks = us; clocks *= get_clocks_per_usec(); diff --git a/src/include/thread.h b/src/include/thread.h new file mode 100644 index 0000000..7dfe4e7 --- /dev/null +++ b/src/include/thread.h @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef THREAD_H_ +#define THREAD_H_ + +#include <stddef.h> +#include <timer.h> +#include <arch/cpu.h> + +#if CONFIG_COOP_MULTITASKING && !defined(__SMM__) && !defined(__PRE_RAM__) +void threads_initialize(void); +/* Return 0 on success, < 0 on failure. */ +int thread_run(void (*func)(void *), void *arg); +/* Return 0 on success, < 0 on failure. */ +int thread_yield_for(unsigned microsecs); +/* thread_resume() is exposed only to be used by the timer code. */ +void thread_resume(struct timeout_callback *tocb); + +static inline int tocb_is_resume(const struct timeout_callback *tocb) +{ + return tocb->callback == thread_resume; +} + +void thread_cooperate(void); +void thread_prevent_coop(void); + +static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) +{ + ci->thread = NULL; +} +#else +static inline void threads_initialize(void) {} +static inline int thread_run(void (*func)(void *), void *arg) { return -1; } +static inline int thread_yield_for(unsigned microsecs) { return -1; } +static inline int tocb_is_resume(const struct timeout_callback *tocb) +{ + return 0; +} +static inline void thread_cooperate(void) {} +static inline void thread_prevent_coop(void) {} +static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { } +#endif + +#endif /* THREAD_H_ */ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index a4d2fc9..9f16e06 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -39,6 +39,7 @@ #endif #include <timer.h> #include <timestamp.h> +#include <thread.h> #if BOOT_STATE_DEBUG #define BS_DEBUG_LVL BIOS_DEBUG @@ -327,7 +328,8 @@ static void bs_call_callbacks(struct boot_state *state, printk(BS_DEBUG_LVL, "BS: callback (%p) @ %s.\n", bscb, bscb->location); #endif - bs_call_callback(bscb); + if (thread_run((void *)bs_call_callback, bscb)) + bs_call_callback(bscb); continue; } @@ -476,13 +478,21 @@ void hardwaremain(int boot_complete) hard_reset(); } + threads_initialize(); + /* Schedule the static boot state entries. */ boot_state_schedule_static_entries(); /* FIXME: Is there a better way to handle this? */ init_timer(); - bs_walk_state_machine(BS_PRE_DEVICE); + if (thread_run((void *)bs_walk_state_machine, (void *)BS_PRE_DEVICE)) + bs_walk_state_machine(BS_PRE_DEVICE); + + while (1) { + bs_run_timers(1); + } + die("Boot state machine failure.\n"); } diff --git a/src/lib/timer_queue.c b/src/lib/timer_queue.c index 8d11f10..7426c3c 100644 --- a/src/lib/timer_queue.c +++ b/src/lib/timer_queue.c @@ -18,6 +18,7 @@ */ #include <stddef.h> #include <timer.h> +#include <thread.h> #define MAX_TIMER_QUEUE_ENTRIES 64 @@ -191,8 +192,13 @@ int timers_run(void) timer_monotonic_get(&current_time); tocb = timer_queue_expired(&global_timer_queue, &current_time); - if (tocb != NULL) - tocb->callback(tocb); + if (tocb != NULL) { + /* If we are resuming a thread or cannot schedule a new + * thread run the callback in this execution context. */ + if (tocb_is_resume(tocb) || + thread_run((void *)tocb->callback, tocb) < 0) + tocb->callback(tocb); + } return !timer_queue_empty(&global_timer_queue); }

1 0

New patch to review for coreboot: 38e17f2 boot state: add notion of blocking transitions
by Aaron Durbin 03 May '13

03 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3191 -gerrit commit 38e17f27794e25e517a7df798c05b9a8c582b97d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 3 12:53:22 2013 -0500 boot state: add notion of blocking transitions There are 3 phases of a state: entry, running, and exit. During the entry and exit phases callbacks can be run. In order to prevent states from transitioning the introduction of a completion deadline is made. As the callbacks are currently called synchronously by the main thread the result is a nop in comparison to not having completion deadlines for callbacks. Change-Id: I188b262873df4469163000c979293c442e21cb31 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootstate.h | 74 +++++++++++++++++++++++++++++++++++++++++++------ src/lib/hardwaremain.c | 67 ++++++++++++++++++++++++++++++++++++++------ 2 files changed, 123 insertions(+), 18 deletions(-) diff --git a/src/include/bootstate.h b/src/include/bootstate.h index f732d1e..bfb3481 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -110,11 +110,27 @@ typedef enum { BS_ON_EXIT } boot_state_sequence_t; +/* The boot_state_completion sturcture is used inernally to the state machine + * to indicate that a call back needs to complete by the provided sequence + * in the boot state machine. */ +struct boot_state_completion { + boot_state_t state; + boot_state_sequence_t when; +}; + +/* The BS_RAMSTAGE_EXIT is a special purpose encoding of a state to indicate + * when a callback should be completed. The completion state of + * BS_RAMSTAGE_EXIT indicates that a callback needs to be completed prior + * to leaving ramstage. i.e. BS_OS_RESUME and BS_PAYLOAD_BOOT. */ +#define BS_RAMSTAGE_EXIT -1 + struct boot_state_callback { void *arg; void (*callback)(void *arg); - /* For use internal to the boot state machine. */ + /* Everything below this comment should be considered private and + * controlled by the boot state machine. */ struct boot_state_callback *next; + struct boot_state_completion deadline; #if BOOT_STATE_DEBUG const char *location; #endif @@ -130,14 +146,18 @@ struct boot_state_callback { #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) #endif -#define BOOT_STATE_CALLBACK_INIT(func_, arg_) \ - { \ - .arg = arg_, \ - .callback = func_, \ - .next = NULL, \ - BOOT_STATE_CALLBACK_INIT_DEBUG \ +#define BOOT_STATE_CALLBACK_INIT_DEADLINE(func_, arg_, state_, seq_) \ + { \ + .arg = arg_, \ + .callback = func_, \ + .next = NULL, \ + .deadline = { state_, seq_ }, \ + BOOT_STATE_CALLBACK_INIT_DEBUG \ } +#define BOOT_STATE_CALLBACK_INIT(func_, arg_) \ + BOOT_STATE_CALLBACK_INIT_DEADLINE(func_, arg_, -2, -2) + #define BOOT_STATE_CALLBACK(name_, func_, arg_) \ struct boot_state_callback name_ = BOOT_STATE_CALLBACK_INIT(func_, arg_) @@ -147,6 +167,32 @@ struct boot_state_callback { bscb_->callback = func_; \ bscb_->arg = arg_ +/* The boot_state_complete_by_(entry|exit) functions can be called on + * a boot state callback prior to being scheduled. The completion deadline + * is just like the start state and sequence. The boot state machine will + * not proceed past the state until the callback is complete. */ +static inline void +boot_state_complete_by_entry(struct boot_state_callback *bscb, + boot_state_t state) +{ + bscb->deadline.state = state; + bscb->deadline.when = BS_ON_ENTRY; +} + +static inline void +boot_state_complete_by_exit(struct boot_state_callback *bscb, + boot_state_t state) +{ + bscb->deadline.state = state; + bscb->deadline.when = BS_ON_EXIT; +} + +static inline void +boot_state_complete_by_ramstage_exit(struct boot_state_callback *bscb) +{ + bscb->deadline.state = BS_RAMSTAGE_EXIT; +} + /* The following 2 functions schedule a callback to be called on entry/exit * to a given state. Note that thare are no ordering guarantees between the * individual callbacks on a given state. 0 is returned on success < 0 on @@ -173,11 +219,21 @@ struct boot_state_init_entry { #define BOOT_STATE_INIT_ENTRIES(name_) \ static struct boot_state_init_entry name_[] BOOT_STATE_INIT_ATTR -#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ +#define BOOT_STATE_INIT_ENTRY_DEADLINE(state_, when_, func_, arg_, end_state_, end_when_) \ { \ .state = state_, \ .when = when_, \ - .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ + .bscb = BOOT_STATE_CALLBACK_INIT_DEADLINE(func_, arg_, end_state_, end_when_), \ } +/* By default the callback needs to run to completion at the same step the + * callback is called. */ +#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ + BOOT_STATE_INIT_ENTRY_DEADLINE(state_, when_, func_, arg_,\ + state_, when_) + +#define BOOT_STATE_INIT_ENTRY_RAMSTAGE_EXIT(state_, when_, func_, arg_) \ + BOOT_STATE_INIT_ENTRY_DEADLINE(state_, when_, func_, arg_, \ + BS_RAMSTAGE_EXIT, 0) + #endif /* BOOTSTATE_H */ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 8e5481e..a4d2fc9 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -72,10 +72,12 @@ struct boot_state_times { struct mono_time samples[MAX_TIME_SAMPLES]; }; + struct boot_state { const char *name; boot_state_t id; struct boot_state_callback *seq_callbacks[2]; + int seq_blocked[2]; boot_state_t (*run_state)(void *arg); void *arg; int complete : 1; @@ -90,6 +92,7 @@ struct boot_state { .name = #state_, \ .id = state_, \ .seq_callbacks = { NULL, NULL }, \ + .seq_blocked = { 0, 0 }, \ .run_state = run_func_, \ .arg = NULL, \ .complete = 0, \ @@ -296,22 +299,41 @@ static void bs_run_timers(int drain) static void bs_run_timers(int drain) {} #endif +static void bs_call_callback(struct boot_state_callback *bscb) +{ + bscb->callback(bscb->arg); + + if (bscb->deadline.state == BS_RAMSTAGE_EXIT) { + boot_states[BS_OS_RESUME].seq_blocked[BS_ON_ENTRY]--; + boot_states[BS_PAYLOAD_BOOT].seq_blocked[BS_ON_ENTRY]--; + return; + } + boot_states[bscb->deadline.state].seq_blocked[bscb->deadline.when]--; +} + static void bs_call_callbacks(struct boot_state *state, boot_state_sequence_t seq) { - while (state->seq_callbacks[seq] != NULL) { - struct boot_state_callback *bscb; + while (state->seq_blocked[seq] != 0) { + if (state->seq_callbacks[seq] != NULL) { + struct boot_state_callback *bscb; - /* Remove the first callback. */ - bscb = state->seq_callbacks[seq]; - state->seq_callbacks[seq] = bscb->next; - bscb->next = NULL; + /* Remove the first callback. */ + bscb = state->seq_callbacks[seq]; + state->seq_callbacks[seq] = bscb->next; + bscb->next = NULL; #if BOOT_STATE_DEBUG - printk(BS_DEBUG_LVL, "BS: callback (%p) @ %s.\n", - bscb, bscb->location); + printk(BS_DEBUG_LVL, "BS: callback (%p) @ %s.\n", + bscb, bscb->location); #endif - bscb->callback(bscb->arg); + bs_call_callback(bscb); + continue; + } + + /* Run the timers to make forward progress if a timeout callback + * is blocking this state transition. */ + bs_run_timers(0); } } @@ -355,6 +377,31 @@ static void bs_walk_state_machine(boot_state_t current_state_id) } } +static void boot_state_sched_completion(struct boot_state *start_state, + struct boot_state_callback *bscb, + boot_state_sequence_t seq) +{ + if (bscb->deadline.state == BS_RAMSTAGE_EXIT) { + boot_states[BS_OS_RESUME].seq_blocked[BS_ON_ENTRY]++; + boot_states[BS_PAYLOAD_BOOT].seq_blocked[BS_ON_ENTRY]++; + return; + } + + /* Handle unitialized completion deadline or a completion deadline + * for a state beforeteh current scheduled one. In both cases the + * deadline is the start state and sequence. */ + if (bscb->deadline.state < start_state->id || + (bscb->deadline.state == start_state->id && + bscb->deadline.when < seq)) { + bscb->deadline.state = start_state->id; + bscb->deadline.when = seq; + start_state->seq_blocked[seq]++; + return; + } + + boot_states[bscb->deadline.state].seq_blocked[bscb->deadline.when]++; +} + static int boot_state_sched_callback(struct boot_state *state, struct boot_state_callback *bscb, boot_state_sequence_t seq) @@ -370,6 +417,8 @@ static int boot_state_sched_callback(struct boot_state *state, bscb->next = state->seq_callbacks[seq]; state->seq_callbacks[seq] = bscb; + boot_state_sched_completion(state, bscb, seq); + return 0; }

1 0

Patch set updated for coreboot: 0a9d52b haswell: use tsc for udelay()
by Aaron Durbin 03 May '13

03 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3169 -gerrit commit 0a9d52b69d7f0498ab3f89b33fa575416ff57df9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:39:28 2013 -0500 haswell: use tsc for udelay() Instead of using the local apic timer for udelay() use the tsc. That way SMM, romstage, and ramstage all use the same delay functionality. Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 3 +- src/cpu/intel/haswell/Makefile.inc | 3 ++ src/cpu/intel/haswell/tsc_freq.c | 31 +++++++++++++++ src/northbridge/intel/haswell/Makefile.inc | 1 - src/northbridge/intel/haswell/udelay.c | 63 ------------------------------ 5 files changed, 36 insertions(+), 65 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 13861f9..152059f 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE select SMM_TSEG select SMM_MODULES select RELOCATABLE_MODULES diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 90ffd66..60c061d 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,7 +1,9 @@ ramstage-y += haswell_init.c subdirs-y += ../../x86/name ramstage-y += mp_init.c +ramstage-y += tsc_freq.c romstage-y += romstage.c +romstage-y += tsc_freq.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c @@ -10,6 +12,7 @@ ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc diff --git a/src/cpu/intel/haswell/tsc_freq.c b/src/cpu/intel/haswell/tsc_freq.c new file mode 100644 index 0000000..0a78053 --- /dev/null +++ b/src/cpu/intel/haswell/tsc_freq.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include "cpu/intel/haswell/haswell.h" + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff); +} diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 896360d..b2ac85e 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail diff --git a/src/northbridge/intel/haswell/udelay.c b/src/northbridge/intel/haswell/udelay.c deleted file mode 100644 index f5d541e..0000000 --- a/src/northbridge/intel/haswell/udelay.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include "cpu/intel/haswell/haswell.h" - -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_PLATFORM_INFO); - divisor = (msr.lo >> 8) & 0xff; - - d = HASWELL_BCLK * divisor; - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); -}

1 0

Patch set updated for coreboot: a5a317b x86: add TSC_CONSTANT_RATE option
by Aaron Durbin 03 May '13

03 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3168 -gerrit commit a5a317bd47de7ce5c0dbba3df0c874cca819f2c1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:27:09 2013 -0500 x86: add TSC_CONSTANT_RATE option Some boards use the local apic for udelay(), but they also provide their own implementation of udelay() for SMM. The reason for using the local apic for udelay() in ramstage is to not have to pay the penalty of calibrating the TSC frequency. Therefore provide a TSC_CONSTANT_RATE option to indicate that TSC calibration is not needed. Instead rely on the presence of a tsc_freq_mhz() function provided by the cpu/board. Additionally, assume that if TSC_CONSTANT_RATE is selected the udelay() function in SMM will be the tsc. Change-Id: I1629c2fbe3431772b4e80495160584fb6f599e9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 7 +++++++ src/cpu/x86/tsc/Makefile.inc | 4 ++++ src/cpu/x86/tsc/delay_tsc.c | 27 ++++++++++++++++++++++++--- src/include/cpu/x86/tsc.h | 4 ++++ 4 files changed, 39 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5cf40fa..c64a8e4 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -25,6 +25,13 @@ config UDELAY_TSC bool default n +config TSC_CONSTANT_RATE + def_bool n + depends on UDELAY_TSC + help + This option asserts that the TSC ticks at a known constant rate. + Therefore, no TSC calibration is required. + config TSC_MONOTONIC_TIMER def_bool n depends on UDELAY_TSC diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 44bfe85..3bbae84 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,2 +1,6 @@ ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) +smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +endif diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index e4993d0..0540496 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -5,8 +5,16 @@ #include <smp/spinlock.h> #include <delay.h> +#if !defined(__PRE_RAM__) + static unsigned long clocks_per_usec; +#if CONFIG_TSC_CONSTANT_RATE +static unsigned long calibrate_tsc(void) +{ + return tsc_freq_mhz(); +} +#else /* CONFIG_TSC_CONSTANT_RATE */ #if !CONFIG_TSC_CALIBRATE_WITH_IO #define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ @@ -139,6 +147,7 @@ static unsigned long long calibrate_tsc(void) #endif /* CONFIG_TSC_CALIBRATE_WITH_IO */ +#endif /* CONFIG_TSC_CONSTANT_RATE */ void init_timer(void) { @@ -148,15 +157,27 @@ void init_timer(void) } } +static inline unsigned long get_clocks_per_usec(void) +{ + init_timer(); + return clocks_per_usec; +} +#else /* !defined(__PRE_RAM__) */ +/* romstage calls into cpu/board specific function every time. */ +static inline unsigned long get_clocks_per_usec(void) +{ + return tsc_freq_mhz(); +} +#endif /* !defined(__PRE_RAM__) */ + void udelay(unsigned us) { unsigned long long count; unsigned long long stop; unsigned long long clocks; - init_timer(); clocks = us; - clocks *= clocks_per_usec; + clocks *= get_clocks_per_usec(); count = rdtscll(); stop = clocks + count; while(stop > count) { @@ -165,7 +186,7 @@ void udelay(unsigned us) } } -#if CONFIG_TSC_MONOTONIC_TIMER +#if CONFIG_TSC_MONOTONIC_TIMER && !defined(__PRE_RAM__) && !defined(__SMM__) #include <timer.h> static struct monotonic_counter { diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 6ce7f5f..8e49a66 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -40,4 +40,8 @@ static inline unsigned long long rdtscll(void) } #endif +#if CONFIG_TSC_CONSTANT_RATE +unsigned long tsc_freq_mhz(void); +#endif + #endif /* CPU_X86_TSC_H */

1 0

Patch set updated for coreboot: 1d97d25 x86: harden tsc udelay() function
by Aaron Durbin 03 May '13

03 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3171 -gerrit commit 1d97d25d3f455c9fd99bec7a4036d14716561c48 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:55:14 2013 -0500 x86: harden tsc udelay() function Since the TSC udelay() fucntion can be used in SMM that means the TSC can count up to whatever value. The current loop was not handling TSC rollover properly. In most cases this should not matter as the TSC typically starts ticking at value 0, and it would take a very long time to roll it over. However, it is my understanding that this behavior is not guaranteed. Theoretically the TSC could start or be be written to with a large value that would cause the rollover. Change-Id: I2f11a5bc4f27d5543e74f8224811fa91e4a55484 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/tsc/delay_tsc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 0540496..0e2a9c0 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -172,18 +172,18 @@ static inline unsigned long get_clocks_per_usec(void) void udelay(unsigned us) { - unsigned long long count; - unsigned long long stop; - unsigned long long clocks; + unsigned long long start; + unsigned long long current; + unsigned long long clocks; + start = rdtscll(); clocks = us; clocks *= get_clocks_per_usec(); - count = rdtscll(); - stop = clocks + count; - while(stop > count) { + current = rdtscll(); + while((current - start) < clocks) { cpu_relax(); - count = rdtscll(); - } + current = rdtscll(); + } } #if CONFIG_TSC_MONOTONIC_TIMER && !defined(__PRE_RAM__) && !defined(__SMM__)

1 0

Patch set updated for coreboot: a0091c7 haswell: use tsc for udelay()
by Aaron Durbin 03 May '13

03 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3169 -gerrit commit a0091c7d53d74b70a6915dce0841a13cf2e9d7e6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:39:28 2013 -0500 haswell: use tsc for udelay() Instead of using the local apic timer for udelay() use the tsc. That way SMM, romstage, and ramstage all use the same delay functionality. Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 3 +- src/cpu/intel/haswell/Makefile.inc | 3 ++ src/cpu/intel/haswell/tsc_freq.c | 31 +++++++++++++++ src/northbridge/intel/haswell/Makefile.inc | 1 - src/northbridge/intel/haswell/udelay.c | 63 ------------------------------ 5 files changed, 36 insertions(+), 65 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 13861f9..152059f 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE select SMM_TSEG select SMM_MODULES select RELOCATABLE_MODULES diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 90ffd66..60c061d 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,7 +1,9 @@ ramstage-y += haswell_init.c subdirs-y += ../../x86/name ramstage-y += mp_init.c +ramstage-y += tsc_freq.c romstage-y += romstage.c +romstage-y += tsc_freq.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c @@ -10,6 +12,7 @@ ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc diff --git a/src/cpu/intel/haswell/tsc_freq.c b/src/cpu/intel/haswell/tsc_freq.c new file mode 100644 index 0000000..0a78053 --- /dev/null +++ b/src/cpu/intel/haswell/tsc_freq.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include "cpu/intel/haswell/haswell.h" + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff); +} diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 896360d..b2ac85e 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail diff --git a/src/northbridge/intel/haswell/udelay.c b/src/northbridge/intel/haswell/udelay.c deleted file mode 100644 index f5d541e..0000000 --- a/src/northbridge/intel/haswell/udelay.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include "cpu/intel/haswell/haswell.h" - -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_PLATFORM_INFO); - divisor = (msr.lo >> 8) & 0xff; - - d = HASWELL_BCLK * divisor; - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); -}

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coreboot-gerrit May 2013