coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 0bb875b exynos5/5250: Update timer call sites to use monotonic timer API
by gerrit＠coreboot.org 05 May '13

05 May '13

the following patch was just integrated into master: commit 0bb875be5e575b6eceb081d1a92da467b87aa96b Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu May 2 14:23:51 2013 -0700 exynos5/5250: Update timer call sites to use monotonic timer API This goes thru various call sites where we used timer_us() and updates them to use the new monotonic timer API. udelay() changed substantially and now gracefully handles wraparound. Change-Id: Ie2cc86a4125cf0de12837fd7d337a11aed25715c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3176 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Sat May 4 14:39:39 2013, giving +1 See http://review.coreboot.org/3176 for details. -gerrit

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Patch merged into coreboot/master: c2f1777 Lenovo ThinkPad X60: Clean up `romstage.c`
by gerrit＠coreboot.org 04 May '13

04 May '13

the following patch was just integrated into master: commit c2f177737bb2ae1836b3badeb90daf6bdcc2134f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Apr 29 23:05:44 2013 +0200 Lenovo ThinkPad X60: Clean up `romstage.c` 1. Move comment for console init to correct place. 2. Start output with capital letter and add full stop at the end. 3. Add missing »)« at the end of description of GPIO 10. 4. Use tabulators instead of spaces. 5. Indent the code automatically using GNU indent [1] with the `-sc` switch adding stars in front of comment blocks as the good indent manual documents. $ indent -linux -sc src/mainboard/lenovo/x60/romstage.c Leave the numbers left aligned as it is more beneficial to be able to run indent without adapting the result afterward. [1] http://www.coreboot.org/Development_Guidelines#Coding_Style Change-Id: I2fa018ec28ff19d23d68754b565c13a7d7a57355 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3185 Tested-by: build bot (Jenkins) Reviewed-by: Denis Carikli <GNUtoo(a)no-log.org> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri May 3 16:04:36 2013, giving +1 Reviewed-By: Denis Carikli <GNUtoo(a)no-log.org> at Sat May 4 21:24:17 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat May 4 22:20:04 2013, giving +2 See http://review.coreboot.org/3185 for details. -gerrit

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Patch set updated for coreboot: 936af9c x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c`
by Paul Menzel 04 May '13

04 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3184 -gerrit commit 936af9c274ea1141823f816180ae1ba1f2a735cd Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:49:41 2013 +0200 x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c` Moving the code from the southbridges to `src/arch/x86/lib/ioapic.c` all boards using the function `set_ioapic_id()` get the debug feature. Change-Id: Ic59c4c2213ed97bdf3798b3dc6e7cecc30e135d8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/lib/ioapic.c | 7 +++++++ src/southbridge/intel/bd82x6x/lpc.c | 6 ------ src/southbridge/intel/i82801gx/lpc.c | 7 ------- src/southbridge/intel/lynxpoint/lpc.c | 6 ------ 4 files changed, 7 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 4964af6..7fb25ba 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -77,6 +77,7 @@ void clear_ioapic(u32 ioapic_base) void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) { u32 bsp_lapicid = lapicid(); + int i; printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); @@ -90,6 +91,12 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | (ioapic_id << 24)); } + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); + } static void load_vectors(u32 ioapic_base) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 3e5b653..bb47dc6 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -60,7 +60,6 @@ static void pch_enable_acpi(struct device *dev) */ static void pch_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -69,11 +68,6 @@ static void pch_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9d6224b..9285080 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -46,18 +46,11 @@ typedef struct southbridge_intel_i82801gx_config config_t; */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; - /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); set_ioapic_id(IO_APIC_ADDR, 0x02); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 2d1bd5e..35181ae 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -64,7 +64,6 @@ static void pch_enable_acpi(struct device *dev) */ static void pch_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -73,11 +72,6 @@ static void pch_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ }

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Patch set updated for coreboot: 73a748a Intel 82801Gx: LPC: Unify I/O APIC setup
by Paul Menzel 04 May '13

04 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3181 -gerrit commit 73a748ae8430fd14102940d1293dfd06e8913160 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:40:23 2013 +0200 Intel 82801Gx: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. As commented by Aaron Durbin, a separate `i82801gx_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 45 +++++++++++++++--------------------- 1 file changed, 19 insertions(+), 26 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 777a6d7..9d6224b 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -39,37 +39,30 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static void i82801gx_enable_apic(struct device *dev) +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) { int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ + /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - *ioapic_index = 0; - *ioapic_data = (2 << 24); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + set_ioapic_id(IO_APIC_ADDR, 0x02); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void i82801gx_enable_serial_irqs(struct device *dev) @@ -422,7 +415,7 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ - i82801gx_enable_apic(dev); + i82801gx_enable_ioapic(dev); i82801gx_enable_serial_irqs(dev);

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Patch set updated for coreboot: 0597e10 x86 I/O APIC: Make functions `io_apic_{read, write}()` public
by Paul Menzel 04 May '13

04 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3180 -gerrit commit 0597e1047dbe160d946e227639919bba68c1afdc Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:34:43 2013 +0200 x86 I/O APIC: Make functions `io_apic_{read,write}()` public Some LPC initialiation can save some lines of code when being able to use the functions `io_apic_read()` and `io_apic_write()`. As these two functions are now public, remove them from the generic driver as otherwise we get a build errors like the following. […] Building roda/rk9; i386: ok, using i386-elf-gcc Using payload /srv/jenkins/payloads/seabios/bios.bin.elf Creating config file... (blobs, ccache) ok; Compiling image on 4 cpus in parallel .. FAILED after 12s! Log excerpt: coreboot-builds/roda_rk9/arch/x86/lib/ramstage.o: In function `io_apic_write': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/arch/x86/lib/ioapic.c:32: multiple definition of `io_apic_write' coreboot-builds/roda_rk9/drivers/generic/ioapic/ramstage.o:/srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/drivers/generic/ioapic/ioapic.c:22: first defined here collect2: error: ld returned 1 exit status make: *** [coreboot-builds/roda_rk9/generated/coreboot_ram.o] Error 1 make: *** Waiting for unfinished jobs.... […] Change-Id: Id600007573ff011576967339cc66e6c883a2ed5a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/include/arch/ioapic.h | 2 ++ src/arch/x86/lib/ioapic.c | 4 ++-- src/drivers/generic/ioapic/ioapic.c | 12 ------------ 3 files changed, 4 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index b989e52..7ff47bb 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -39,6 +39,8 @@ #define SMI (2 << 8) #define INT (1 << 8) +u32 io_apic_read(u32 ioapic_base, u32 reg); +void io_apic_write(u32 ioapic_base, u32 reg, u32 value); void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 389c48c..4964af6 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -22,13 +22,13 @@ #include <console/console.h> #include <cpu/x86/lapic.h> -static u32 io_apic_read(u32 ioapic_base, u32 reg) +u32 io_apic_read(u32 ioapic_base, u32 reg) { write32(ioapic_base, reg); return read32(ioapic_base + 0x10); } -static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) +void io_apic_write(u32 ioapic_base, u32 reg, u32 value) { write32(ioapic_base, reg); write32(ioapic_base + 0x10, value); diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 9a93c78..42b2f07 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -12,18 +12,6 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> -static u32 io_apic_read(u32 ioapic_base, u32 reg) -{ - write32(ioapic_base, reg); - return read32(ioapic_base + 0x10); -} - -static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) -{ - write32(ioapic_base, reg); - write32(ioapic_base + 0x10, value); -} - static void ioapic_init(device_t dev) { struct drivers_generic_ioapic_config *config = dev->chip_info;

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Patch set updated for coreboot: d031123 Intel BD82x6x: LPC: Unify I/O APIC setup
by Paul Menzel 04 May '13

04 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3183 -gerrit commit d031123fde227631273822748b28788463c8fe8b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:23:39 2013 +0200 Intel BD82x6x: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/bd82x6x/lpc.c | 65 +++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7bcadc9..3e5b653 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -39,43 +39,43 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void pch_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void pch_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -537,8 +537,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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Patch set updated for coreboot: 59acd76 Intel Lynx Point: LPC: Unify I/O APIC setup
by Paul Menzel 04 May '13

04 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3182 -gerrit commit 59acd76f8c585660c2bf6f4e9b2e6eeb536c4f0b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:17:02 2013 +0200 Intel Lynx Point: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/lpc.c | 65 ++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 40e0468..2d1bd5e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -43,43 +43,43 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void pch_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void pch_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -546,8 +546,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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Patch set updated for coreboot: 029078c Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary.
by Ronald G. Minnich 04 May '13

04 May '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3188 -gerrit commit 029078c6420cd9e8aaf7bf9f837f0dd534646396 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri May 3 18:25:27 2013 +0200 Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary. This option has never had much if any use. It solved a problem over 10 years ago that resulted from an argument over the value or lack thereof of including all the debug strings in a coreboot image. The answer is in: it's a good idea to maintain the capabilty to print all messages, for many reasons. This option is also misleading people, as in a recent discussion, to believe that log messges are controlled at build time in a way they are not. For the record, from this day forward, we can print messages at all log levels and the default log level is set at boot time, as directed by DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and if you are having trouble override it in CMOS and get more messages. Besides, a quick glance shows it's always set to max (9 in this case) in the very few cases (1) in which it is set. Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- documentation/LinuxBIOS-AMD64.tex | 5 --- src/console/Kconfig | 79 ---------------------------------- src/include/console/console.h | 10 +---- src/mainboard/msi/ms9652_fam10/Kconfig | 4 -- util/abuild/abuild | 2 - 5 files changed, 2 insertions(+), 98 deletions(-) diff --git a/documentation/LinuxBIOS-AMD64.tex b/documentation/LinuxBIOS-AMD64.tex index 19a6f59..5847dab 100644 --- a/documentation/LinuxBIOS-AMD64.tex +++ b/documentation/LinuxBIOS-AMD64.tex @@ -408,11 +408,6 @@ machine. Use new \textit{chip\_configure} method for configuring (nonpci) devices. Set to \texttt{1} for all AMD64 mainboards. -\item \begin{verbatim}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL\end{verbatim} - -Errors or log messages up to this level can be printed. Default is -\texttt{8}, minimum is \texttt{0}, maximum is \texttt{10}. - \item \begin{verbatim}CONFIG_DEFAULT_CONSOLE_LOGLEVEL\end{verbatim} Console will log at this level unless changed. Default is \texttt{7}, diff --git a/src/console/Kconfig b/src/console/Kconfig index 6251589..a613477 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -250,119 +250,40 @@ config CONSOLE_CAR_BUFFER_SIZE in the DCACHE based RAM to keep console output before it can be saved in a CBMEM buffer. 3K bytes should be enough even for the BIOS_SPEW level. - - -choice - prompt "Maximum console log level" - default MAXIMUM_CONSOLE_LOGLEVEL_8 - -config MAXIMUM_CONSOLE_LOGLEVEL_8 - bool "8: SPEW" - help - Way too many details. -config MAXIMUM_CONSOLE_LOGLEVEL_7 - bool "7: DEBUG" - help - Debug-level messages. -config MAXIMUM_CONSOLE_LOGLEVEL_6 - bool "6: INFO" - help - Informational messages. -config MAXIMUM_CONSOLE_LOGLEVEL_5 - bool "5: NOTICE" - help - Normal but significant conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_4 - bool "4: WARNING" - help - Warning conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_3 - bool "3: ERR" - help - Error conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_2 - bool "2: CRIT" - help - Critical conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_1 - bool "1: ALERT" - help - Action must be taken immediately. -config MAXIMUM_CONSOLE_LOGLEVEL_0 - bool "0: EMERG" - help - System is unusable. - -endchoice - -config MAXIMUM_CONSOLE_LOGLEVEL - int - default 0 if MAXIMUM_CONSOLE_LOGLEVEL_0 - default 1 if MAXIMUM_CONSOLE_LOGLEVEL_1 - default 2 if MAXIMUM_CONSOLE_LOGLEVEL_2 - default 3 if MAXIMUM_CONSOLE_LOGLEVEL_3 - default 4 if MAXIMUM_CONSOLE_LOGLEVEL_4 - default 5 if MAXIMUM_CONSOLE_LOGLEVEL_5 - default 6 if MAXIMUM_CONSOLE_LOGLEVEL_6 - default 7 if MAXIMUM_CONSOLE_LOGLEVEL_7 - default 8 if MAXIMUM_CONSOLE_LOGLEVEL_8 - help - Map the log level config names to an integer. - choice prompt "Default console log level" default DEFAULT_CONSOLE_LOGLEVEL_8 config DEFAULT_CONSOLE_LOGLEVEL_8 bool "8: SPEW" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8) help Way too many details. config DEFAULT_CONSOLE_LOGLEVEL_7 bool "7: DEBUG" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7) help Debug-level messages. config DEFAULT_CONSOLE_LOGLEVEL_6 bool "6: INFO" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6) help Informational messages. config DEFAULT_CONSOLE_LOGLEVEL_5 bool "5: NOTICE" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5) help Normal but significant conditions. config DEFAULT_CONSOLE_LOGLEVEL_4 bool "4: WARNING" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4) help Warning conditions. config DEFAULT_CONSOLE_LOGLEVEL_3 bool "3: ERR" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4 || MAXIMUM_CONSOLE_LOGLEVEL_3) help Error conditions. config DEFAULT_CONSOLE_LOGLEVEL_2 bool "2: CRIT" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4 || MAXIMUM_CONSOLE_LOGLEVEL_3 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_2) help Critical conditions. config DEFAULT_CONSOLE_LOGLEVEL_1 bool "1: ALERT" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4 || MAXIMUM_CONSOLE_LOGLEVEL_3 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_2 || MAXIMUM_CONSOLE_LOGLEVEL_1) help Action must be taken immediately. config DEFAULT_CONSOLE_LOGLEVEL_0 diff --git a/src/include/console/console.h b/src/include/console/console.h index d320093..031c25d 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -104,20 +104,14 @@ static inline void printk(int LEVEL, const char *fmt, ...) { #define printk(LEVEL, fmt, args...) \ do { \ - if (CONFIG_MAXIMUM_CONSOLE_LOGLEVEL >= LEVEL) { \ - do_printk(LEVEL, fmt, ##args); \ - } \ + do_printk(LEVEL, fmt, ##args); \ } while(0) #else #define printk(LEVEL, fmt, args...) \ do { \ - if (CONFIG_MAXIMUM_CONSOLE_LOGLEVEL >= LEVEL) { \ - do_printk(LEVEL, fmt, ##args); \ - } else { \ - do_printk(BIOS_NEVER, fmt, ##args); \ - } \ + do_printk(LEVEL, fmt, ##args); \ } while(0) #endif diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 852efd4..58cafa2 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -97,10 +97,6 @@ config DEFAULT_CONSOLE_LOGLEVEL int default 9 -config MAXIMUM_CONSOLE_LOGLEVEL - int - default 9 - config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default y diff --git a/util/abuild/abuild b/util/abuild/abuild index 1c69eec..aad066c 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -596,8 +596,6 @@ while true ; do -C|--config) shift; configureonly=1;; -l|--loglevel) shift customizing="${customizing}, loglevel $1" - configoptions="${configoptions}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$1=y\n" - configoptions="${configoptions}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$1\n" configoptions="${configoptions}CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$1=y\n" configoptions="${configoptions}CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$1\n" shift;;

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New patch to review for coreboot: 440d4f1 AMD Fam15tn boards: BiosCallOuts.c: Remove board name from `CodecTableList`
by Paul Menzel 04 May '13

04 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3199 -gerrit commit 440d4f18835be93c0615ba4918123ccd798335df Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat May 4 18:41:54 2013 +0200 AMD Fam15tn boards: BiosCallOuts.c: Remove board name from `CodecTableList` The board name in that variable name is not necessary, as it is not board dependent, that means using the file as a template for making a new coreboot port for another motherboard the variable does not need to be changed, and just increases the code differences between AMD Parmer, AMD Thather and ASUS F2A85-M. So use a generic name. The same was done for AMD Persimmon (and inherited by the LiPPERT FrontRunner/Toucan-AF) in the following commit. commit 5e70766f14253f53190ddd49a544460c6bc1e528 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 26 15:56:11 2013 +0100 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt Reviewed-on: http://review.coreboot.org/2529 The board name is *not* removed from the `CODEC_ENTRY` variable name as the verb table not only depends on the codec but also on the board [1]. Having the board name in the variable name is a good indicator that the contents also needs to be adapted when taking this file as a template for a new port. [1] Unfortunately I was not able to find Jens’ comment in my mail archive and in the Gerrit Web interface. Not sure where it is, but I am sure he made that comment. Change-Id: I440a306cf4ff0a5b1b61d1983d70c66d129904d0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/parmer/BiosCallOuts.c | 4 ++-- src/mainboard/amd/thatcher/BiosCallOuts.c | 4 ++-- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 9592c9d..58bcd02 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -83,7 +83,7 @@ static const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = { {0xff, 0xffffffff} }; -static const CODEC_TBL_LIST ParmerCodecTableList[] = +static const CODEC_TBL_LIST CodecTableList[] = { {0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} @@ -287,7 +287,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ParmerCodecTableList[0]); + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); /* Azalia Controller Front Panel OEM Table Pointer */ /* Fan Control */ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 6979522..60a33ed 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -83,7 +83,7 @@ static const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { {0xff, 0xffffffff} }; -static const CODEC_TBL_LIST ThatcherCodecTableList[] = +static const CODEC_TBL_LIST CodecTableList[] = { {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} @@ -287,7 +287,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); /* Azalia Controller Front Panel OEM Table Pointer */ /* Fan Control */ diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index e913896..0a13208 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -83,7 +83,7 @@ static const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { {0xff, 0xffffffff} }; -static const CODEC_TBL_LIST ThatcherCodecTableList[] = +static const CODEC_TBL_LIST CodecTableList[] = { {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} @@ -110,7 +110,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); /* Azalia Controller Front Panel OEM Table Pointer */ FchParams_env->Imc.ImcEnable = FALSE; FchParams_env->Hwm.HwMonitorEnable = FALSE;

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Patch set updated for coreboot: 18835b6 ASUS F2A85-M: Provide HD Audio verb table for Realtek ALC887-VD
by Paul Menzel 04 May '13

04 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3170 -gerrit commit 18835b6dcd08caa1d4b3fc1ea0adbdf81156d908 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue Apr 2 20:51:15 2013 +0200 ASUS F2A85-M: Provide HD Audio verb table for Realtek ALC887-VD Use the same HD Audio [1] verb table for the Realtek ALC887-VD audio chip as the one set up by the proprietary vendor BIOS. Linux’ ALSA exposes this pin configuration under the virtual filesystem sysfs. /sys/class/sound/hwC1D0/init_pin_configs The script `alsa-info.sh` [2][3] is able to decode the table. Only one channel audio playback (rear connectors) is tested [4], which worked already before. [1] http://en.wikipedia.org/wiki/Intel_High_Definition_Audio [2] http://mailman.alsa-project.org/pipermail/alsa-devel/2013-March/060717.html [3] http://alsa-project.org/main/index.php/Help_To_Debug [4] http://review.coreboot.org/#/c/3170/2//COMMIT_MSG Change-Id: I17fa2d4ab1e1a6bfd84de94e9e4a91bd67b6a0c0 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 37 +++++++++++++++++-------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 0a13208..9e7b30e 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -63,29 +63,32 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /** - * AMD Thatcher Platform ALC272 Verb Table + * ASUS F2A85-M board ALC887-VD Verb Table + * + * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running + * the vendor BIOS. */ -static const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, - {0x12, 0x411111F0}, - {0x13, 0x411111F0}, - {0x14, 0x411111F0}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x17, 0x411111F0}, - {0x18, 0x01a19840}, - {0x19, 0x411111F0}, - {0x1a, 0x01813030}, - {0x1b, 0x411111F0}, - {0x1d, 0x40130605}, - {0x1e, 0x01441120}, - {0x21, 0x01211010}, +const CODEC_ENTRY f2a85-m_alc887_VerbTbl[] = { + {0x11, 0x99430140}, + {0x12, 0x411111f0}, + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01012014}, + {0x18, 0x01a19850}, + {0x19, 0x02a19c60}, + {0x1a, 0x0181305f}, + {0x1b, 0x02214c20}, + {0x1c, 0x411111f0}, + {0x1d, 0x4005e601}, + {0x1e, 0x01456130}, + {0x1f, 0x411111f0}, {0xff, 0xffffffff} }; static const CODEC_TBL_LIST CodecTableList[] = { - {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, + {0x10ec0887, (CODEC_ENTRY*)&alc887_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} };

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coreboot-gerrit May 2013