coreboot-gerrit May 2013

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Patch set updated for coreboot: f5f888e ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
by Paul Menzel 06 May '13

06 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3200 -gerrit commit f5f888eed08b39ff9a553cf24e5355360ab0ebec Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun May 5 12:09:16 2013 +0200 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case Currently the code in the if statement if (!byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); only gets executed if `byte == 0x0`, that means only in the default case where RAM voltage is 1.5 Volts. But the RAM voltage should be changed when configured for the non-default case. So negate the predicate to alter the RAM voltage for the non-default cases. To prevent the build error OBJCOPY cbfs/fallback/coreboot_ram.elf coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 add `southbridge/amd/agesa/hudson/smbus.c` providing the function `do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can actually be used after the needed header files are included in a previous commit. Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6 Reported-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/f2a85-m/romstage.c | 3 ++- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index c2fc75e..a8c8ba0 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -101,7 +101,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* set DDR3 voltage */ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - if (!byte) + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index da029a0..7802600 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -1,3 +1,4 @@ +romstage-y += smbus.c ramstage-y += hudson.c ramstage-y += usb.c ramstage-y += lpc.c

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Patch set updated for coreboot: db1785d ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
by Paul Menzel 06 May '13

06 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3200 -gerrit commit db1785d3bfc96d475bbe3090a6bbeabb4b899df1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun May 5 12:09:16 2013 +0200 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case Currently the if statement if (!byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); only gets executed if `byte == 0x0`, that means only in the default case where RAM voltage is 1.5 Volts. But the RAM voltage should be changed when configured for the non-default case. So change the predicament to alter the RAM voltage for the non-default cases. To prevent the build error OBJCOPY cbfs/fallback/coreboot_ram.elf coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 add `southbridge/amd/agesa/hudson/smbus.c` providing the function `do_smbus_write_byte` to ROM stage in `Makefile.inc`. Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6 Reported-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/f2a85-m/romstage.c | 3 ++- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/smbus.c | 2 ++ src/southbridge/amd/agesa/hudson/smbus.h | 2 +- 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index c2fc75e..a8c8ba0 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -101,7 +101,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* set DDR3 voltage */ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - if (!byte) + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index da029a0..7802600 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -1,3 +1,4 @@ +romstage-y += smbus.c ramstage-y += hudson.c ramstage-y += usb.c ramstage-y += lpc.c diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index 682b86d..e428d43 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -20,6 +20,8 @@ #ifndef _HUDSON_SMBUS_C_ #define _HUDSON_SMBUS_C_ +#include <io.h> +#include <stdint.h> #include "smbus.h" static inline void smbus_delay(void) diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index b194aae..53cc0e6 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -20,7 +20,7 @@ #ifndef HUDSON_SMBUS_H #define HUDSON_SMBUS_H -//#include <stdint.h> +#include <stdint.h> #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1

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Patch set updated for coreboot: 0a63cfe ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
by Paul Menzel 06 May '13

06 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3200 -gerrit commit 0a63cfe1ff9f81029ee9937023d09a8941150868 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun May 5 12:09:16 2013 +0200 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case Currently the if statement if (!byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); only gets executed if `byte == 0x0`, that means only in the default case where RAM voltage is 1.5 Volts. But the RAM voltage should be changed when configured for the non-default case. So change the predicament to alter the RAM voltage for the non-default cases. To prevent the build error OBJCOPY cbfs/fallback/coreboot_ram.elf coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 add `southbridge/amd/agesa/hudson/smbus.c` providing the function `do_smbus_write_byte` to ROM stage in `Makefile.inc`. Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6 Reported-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/f2a85-m/romstage.c | 3 ++- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/smbus.c | 1 + src/southbridge/amd/agesa/hudson/smbus.h | 2 +- 4 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index c2fc75e..a8c8ba0 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -101,7 +101,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* set DDR3 voltage */ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - if (!byte) + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index da029a0..7802600 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -1,3 +1,4 @@ +romstage-y += smbus.c ramstage-y += hudson.c ramstage-y += usb.c ramstage-y += lpc.c diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index 682b86d..d13032e 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -20,6 +20,7 @@ #ifndef _HUDSON_SMBUS_C_ #define _HUDSON_SMBUS_C_ +#include <stdint.h> #include "smbus.h" static inline void smbus_delay(void) diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index b194aae..53cc0e6 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -20,7 +20,7 @@ #ifndef HUDSON_SMBUS_H #define HUDSON_SMBUS_H -//#include <stdint.h> +#include <stdint.h> #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1

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Patch set updated for coreboot: 72990ab ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
by Paul Menzel 06 May '13

06 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3200 -gerrit commit 72990ab172de053bc9b92c7f01649d0e52ba0b54 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun May 5 12:09:16 2013 +0200 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case Currently the if statement if (!byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); only gets executed if `byte == 0x0`, that means only in the default case where RAM voltage is 1.5 Volts. But the RAM voltage should be changed when configured for the non-default case. So change the predicament to alter the RAM voltage for the non-default cases. To prevent the build error OBJCOPY cbfs/fallback/coreboot_ram.elf coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 add `southbridge/amd/agesa/hudson/smbus.c` providing the function `do_smbus_write_byte` to ROM stage in `Makefile.inc`. Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6 Reported-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/f2a85-m/romstage.c | 3 ++- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index c2fc75e..a8c8ba0 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -101,7 +101,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* set DDR3 voltage */ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - if (!byte) + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index da029a0..7802600 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -1,3 +1,4 @@ +romstage-y += smbus.c ramstage-y += hudson.c ramstage-y += usb.c ramstage-y += lpc.c

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Patch set updated for coreboot: ff7d593 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
by Paul Menzel 06 May '13

06 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3200 -gerrit commit ff7d593c7663edd0aaa7b5b1a543063d78150c97 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun May 5 12:09:16 2013 +0200 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case Currently the if statement if (!byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); only gets executed if `byte == 0x0`, that means only in the default case where RAM voltage is 1.5 Volts. But the RAM voltage should be changed when configured for the non-default case. So change the predicament to alter the RAM voltage for the non-default cases. To prevent the build error OBJCOPY cbfs/fallback/coreboot_ram.elf coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 `southbridge/amd/agesa/hudson/hudson.c` providing the function `do_smbus_write_byte` needs to be added to ROM stage. Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6 Reported-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/f2a85-m/romstage.c | 3 ++- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index c2fc75e..a8c8ba0 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -101,7 +101,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* set DDR3 voltage */ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - if (!byte) + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index da029a0..f5b1a2c 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -1,3 +1,4 @@ +romstage-y += hudson.c ramstage-y += hudson.c ramstage-y += usb.c ramstage-y += lpc.c

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Patch set updated for coreboot: 4714c8d ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
by Paul Menzel 06 May '13

06 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3200 -gerrit commit 4714c8d4718c5e60f7a4a4ba8d689812a77f03f6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun May 5 12:09:16 2013 +0200 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case Currently the if statement if (!byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); only gets executed if `byte == 0x0`, that means only in the default case where RAM voltage is 1.5 Volts. But the RAM voltage should be changed when configured for the non-default case. So change the predicament to alter the RAM voltage for the non-default cases. To prevent the build error OBJCOPY cbfs/fallback/coreboot_ram.elf coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 `southbridge/amd/agesa/hudson/hudson.c` providing the function `do_smbus_write_byte` needs to be added to ROM stage. Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6 Reported-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/f2a85-m/romstage.c | 3 ++- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index c2fc75e..a8c8ba0 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -101,7 +101,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* set DDR3 voltage */ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - if (!byte) + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index da029a0..f5b1a2c 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -1,3 +1,4 @@ +romstage-y += hudson.c ramstage-y += hudson.c ramstage-y += usb.c ramstage-y += lpc.c

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Patch set updated for coreboot: 6c1bc8a sconfig: Refuse devicetree with leaf "chip"s
by David Hendricks 06 May '13

06 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3189 -gerrit commit 6c1bc8a9378d7e1364bf386c8ab8ebc959a1db1a Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri May 3 20:31:56 2013 +0200 sconfig: Refuse devicetree with leaf "chip"s It doesn't make sense to have a chip without any containing device in the device tree, and it creates lots of funny issues when trying to make use of such a tree (ask Ron). Since the right thing is to refuse such devicetrees, this change makes them a syntax error. Change-Id: Ia35b518bd4acd631e78bdf63c4424c0fa6a81229 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/sconfig/sconfig.tab.c_shipped | 122 +++++++++++++++++++------------------ util/sconfig/sconfig.y | 2 +- 2 files changed, 63 insertions(+), 61 deletions(-) diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 3a56ac8..1347b89 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -387,16 +387,16 @@ union yyalloc /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 37 +#define YYLAST 48 /* YYNTOKENS -- Number of terminals. */ #define YYNTOKENS 28 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 13 /* YYNRULES -- Number of rules. */ -#define YYNRULES 22 +#define YYNRULES 24 /* YYNRULES -- Number of states. */ -#define YYNSTATES 41 +#define YYNSTATES 46 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ #define YYUNDEFTOK 2 @@ -444,30 +444,30 @@ static const yytype_uint8 yytranslate[] = YYRHS. */ static const yytype_uint8 yyprhs[] = { - 0, 0, 3, 4, 7, 10, 13, 16, 17, 20, - 23, 26, 29, 32, 33, 34, 40, 41, 49, 54, - 59, 63, 68 + 0, 0, 3, 4, 7, 10, 12, 15, 18, 21, + 24, 27, 30, 33, 36, 39, 40, 41, 47, 48, + 56, 61, 66, 70, 75 }; /* YYRHS -- A `-1'-separated list of the rules' RHS. */ static const yytype_int8 yyrhs[] = { 29, 0, -1, -1, 30, 33, -1, 31, 35, -1, - 31, 33, -1, 31, 38, -1, -1, 32, 35, -1, - 32, 33, -1, 32, 37, -1, 32, 39, -1, 32, - 40, -1, -1, -1, 3, 12, 34, 31, 9, -1, - -1, 4, 7, 22, 6, 36, 32, 9, -1, 8, - 22, 10, 22, -1, 5, 12, 10, 12, -1, 23, - 22, 22, -1, 23, 22, 22, 24, -1, 25, 22, - 27, 22, -1 + 35, -1, 31, 33, -1, 31, 38, -1, 38, 31, + -1, 33, 31, -1, 32, 35, -1, 32, 33, -1, + 32, 37, -1, 32, 39, -1, 32, 40, -1, -1, + -1, 3, 12, 34, 31, 9, -1, -1, 4, 7, + 22, 6, 36, 32, 9, -1, 8, 22, 10, 22, + -1, 5, 12, 10, 12, -1, 23, 22, 22, -1, + 23, 22, 22, 24, -1, 25, 22, 27, 22, -1 }; /* YYRLINE[YYN] -- source line where rule number YYN was defined. */ static const yytype_uint8 yyrline[] = { - 0, 35, 35, 35, 37, 37, 37, 37, 39, 39, - 39, 39, 39, 39, 41, 41, 51, 51, 63, 66, - 69, 72, 75 + 0, 35, 35, 35, 37, 37, 37, 37, 37, 37, + 39, 39, 39, 39, 39, 39, 41, 41, 51, 51, + 63, 66, 69, 72, 75 }; #endif @@ -499,17 +499,17 @@ static const yytype_uint16 yytoknum[] = /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 28, 30, 29, 31, 31, 31, 31, 32, 32, - 32, 32, 32, 32, 34, 33, 36, 35, 37, 38, - 39, 39, 40 + 0, 28, 30, 29, 31, 31, 31, 31, 31, 31, + 32, 32, 32, 32, 32, 32, 34, 33, 36, 35, + 37, 38, 39, 39, 40 }; /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ static const yytype_uint8 yyr2[] = { - 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, - 2, 2, 2, 0, 0, 5, 0, 7, 4, 4, - 3, 4, 4 + 0, 2, 0, 2, 2, 1, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 0, 0, 5, 0, 7, + 4, 4, 3, 4, 4 }; /* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM. @@ -517,37 +517,37 @@ static const yytype_uint8 yyr2[] = means the default is an error. */ static const yytype_uint8 yydefact[] = { - 2, 0, 0, 1, 0, 3, 14, 7, 0, 0, - 0, 15, 5, 4, 6, 0, 0, 0, 0, 16, - 19, 13, 0, 0, 17, 0, 0, 9, 8, 10, - 11, 12, 0, 0, 0, 0, 20, 0, 18, 21, - 22 + 2, 0, 0, 1, 0, 3, 16, 0, 0, 0, + 0, 0, 5, 0, 0, 0, 17, 6, 4, 7, + 9, 8, 0, 0, 18, 21, 15, 0, 0, 19, + 0, 0, 11, 10, 12, 13, 14, 0, 0, 0, + 0, 22, 0, 20, 23, 24 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { - -1, 1, 2, 8, 22, 5, 7, 13, 21, 29, - 14, 30, 31 + -1, 1, 2, 10, 27, 11, 7, 12, 26, 34, + 13, 35, 36 }; /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing STATE-NUM. */ -#define YYPACT_NINF -9 +#define YYPACT_NINF -10 static const yytype_int8 yypact[] = { - -9, 3, 1, -9, -2, -9, -9, -9, 4, 5, - -1, -9, -9, -9, -9, -8, 7, 9, 6, -9, - -9, -9, -3, 2, -9, 8, 10, -9, -9, -9, - -9, -9, 11, 12, -4, 13, -5, 14, -9, -9, - -9 + -10, 2, 3, -10, -5, -10, -10, 24, 15, 11, + 12, 24, -10, 24, 9, 23, -10, -10, -10, -10, + 24, 24, 28, 25, -10, -10, -10, 1, 13, -10, + 14, 16, -10, -10, -10, -10, -10, 29, 18, 17, + 20, 21, 26, -10, -10, -10 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -9, -9, -9, -9, -9, -6, -9, 15, -9, -9, - -9, -9, -9 + -10, -10, -10, 19, -10, -2, -10, -7, -10, -10, + -9, -10, -10 }; /* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If @@ -556,35 +556,37 @@ static const yytype_int8 yypgoto[] = #define YYTABLE_NINF -1 static const yytype_uint8 yytable[] = { - 4, 9, 12, 3, 4, 23, 24, 4, 9, 10, - 6, 16, 15, 11, 17, 19, 27, 18, 20, 39, - 25, 35, 26, 37, 32, 0, 0, 0, 0, 0, - 33, 0, 34, 0, 36, 38, 40, 28 + 5, 19, 3, 18, 4, 8, 4, 6, 17, 28, + 29, 19, 19, 18, 18, 4, 8, 9, 17, 17, + 33, 16, 14, 15, 30, 32, 31, 4, 8, 9, + 20, 22, 21, 23, 24, 37, 38, 25, 39, 40, + 41, 0, 43, 0, 42, 44, 0, 0, 45 }; #define yypact_value_is_default(yystate) \ - ((yystate) == (-9)) + ((yystate) == (-10)) #define yytable_value_is_error(yytable_value) \ YYID (0) static const yytype_int8 yycheck[] = { - 3, 4, 8, 0, 3, 8, 9, 3, 4, 5, - 12, 12, 7, 9, 22, 6, 22, 10, 12, 24, - 23, 10, 25, 27, 22, -1, -1, -1, -1, -1, - 22, -1, 22, -1, 22, 22, 22, 22 + 2, 10, 0, 10, 3, 4, 3, 12, 10, 8, + 9, 20, 21, 20, 21, 3, 4, 5, 20, 21, + 27, 9, 7, 12, 23, 27, 25, 3, 4, 5, + 11, 22, 13, 10, 6, 22, 22, 12, 22, 10, + 22, -1, 22, -1, 27, 24, -1, -1, 22 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 29, 30, 0, 3, 33, 12, 34, 31, 4, - 5, 9, 33, 35, 38, 7, 12, 22, 10, 6, - 12, 36, 32, 8, 9, 23, 25, 33, 35, 37, - 39, 40, 22, 22, 22, 10, 22, 27, 22, 24, - 22 + 0, 29, 30, 0, 3, 33, 12, 34, 4, 5, + 31, 33, 35, 38, 7, 12, 9, 33, 35, 38, + 31, 31, 22, 10, 6, 12, 36, 32, 8, 9, + 23, 25, 33, 35, 37, 39, 40, 22, 22, 22, + 10, 22, 27, 22, 24, 22 }; #define yyerrok (yyerrstatus = 0) @@ -1428,7 +1430,7 @@ yyreduce: { postprocess_devtree(); } break; - case 14: + case 16: { (yyval.device) = new_chip(cur_parent, cur_bus, (yyvsp[(2) - (2)].string)); @@ -1436,7 +1438,7 @@ yyreduce: } break; - case 15: + case 17: { cur_parent = (yyvsp[(3) - (5)].device)->parent; @@ -1445,7 +1447,7 @@ yyreduce: } break; - case 16: + case 18: { (yyval.device) = new_device(cur_parent, cur_bus, (yyvsp[(2) - (4)].number), (yyvsp[(3) - (4)].string), (yyvsp[(4) - (4)].number)); @@ -1454,7 +1456,7 @@ yyreduce: } break; - case 17: + case 19: { cur_parent = (yyvsp[(5) - (7)].device)->parent; @@ -1464,27 +1466,27 @@ yyreduce: } break; - case 18: + case 20: { add_resource(cur_parent, (yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); } break; - case 19: + case 21: { add_register(cur_parent, (yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); } break; - case 20: + case 22: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (3)].string), NULL, 16), strtol((yyvsp[(3) - (3)].string), NULL, 16), 0); } break; - case 21: + case 23: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), strtol((yyvsp[(3) - (4)].string), NULL, 16), 1); } break; - case 22: + case 24: { add_ioapic_info(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), (yyvsp[(3) - (4)].string), strtol((yyvsp[(4) - (4)].string), NULL, 16)); } break; diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 8ea702e..f298ce2 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -34,7 +34,7 @@ static struct device *cur_parent, *cur_bus; %% devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ; -chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; +chipchildren: chipchildren device | device | chipchildren chip | chipchildren registers | registers chipchildren | chip chipchildren ; devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | /* empty */ ;

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Patch set updated for coreboot: ea9d972 I/O APIC Kconfig: `select IOAPIC if !DRIVERS_GENERIC_IOAPIC`
by David Hendricks 06 May '13

06 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3196 -gerrit commit ea9d9720fc9dce087355b14a1c86a203bc47973f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat May 4 16:54:52 2013 +0200 I/O APIC Kconfig: `select IOAPIC if !DRIVERS_GENERIC_IOAPIC` Using the generic I/O APIC driver src/drivers/generic/ioapic/ioapic.c added by Sven Schnelle in commit »Add generic IOAPIC driver« (aa03af74) [1], the other I/O APIC source file is not needed. src/arch/x86/lib/ioapic.c The Kconfig variable `CONFIG_IOAPIC` is only used in src/include/cpu/x86/lapic.h which maybe needs to be adapted too. Let’s see what breaks. [1] http://review.coreboot.org/1137 Change-Id: Ieb462c9e2e8a09628ee317ea4fb0e9266bb86c33 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/p2b-d/Kconfig | 2 +- src/mainboard/asus/p2b-ds/Kconfig | 2 +- src/northbridge/via/cx700/Kconfig | 2 +- src/southbridge/amd/agesa/hudson/Kconfig | 2 +- src/southbridge/amd/amd8111/Kconfig | 2 +- src/southbridge/amd/cimx/sb700/Kconfig | 2 +- src/southbridge/amd/cimx/sb800/Kconfig | 2 +- src/southbridge/amd/cimx/sb900/Kconfig | 2 +- src/southbridge/amd/sb600/Kconfig | 2 +- src/southbridge/amd/sb700/Kconfig | 2 +- src/southbridge/amd/sb800/Kconfig | 2 +- src/southbridge/intel/bd82x6x/Kconfig | 2 +- src/southbridge/intel/esb6300/Kconfig | 2 +- src/southbridge/intel/i3100/Kconfig | 2 +- src/southbridge/intel/i82801ax/Kconfig | 2 +- src/southbridge/intel/i82801bx/Kconfig | 2 +- src/southbridge/intel/i82801cx/Kconfig | 2 +- src/southbridge/intel/i82801dx/Kconfig | 2 +- src/southbridge/intel/i82801ex/Kconfig | 2 +- src/southbridge/intel/i82801gx/Kconfig | 2 +- src/southbridge/intel/i82801ix/Kconfig | 2 +- src/southbridge/intel/lynxpoint/Kconfig | 2 +- src/southbridge/nvidia/ck804/Kconfig | 2 +- src/southbridge/nvidia/mcp55/Kconfig | 2 +- src/southbridge/sis/sis966/Kconfig | 2 +- src/southbridge/via/vt8237r/Kconfig | 2 +- 26 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig index 54a1bae..1213ba8 100644 --- a/src/mainboard/asus/p2b-d/Kconfig +++ b/src/mainboard/asus/p2b-d/Kconfig @@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig index 652b31a..1cd0aac 100644 --- a/src/mainboard/asus/p2b-ds/Kconfig +++ b/src/mainboard/asus/p2b-ds/Kconfig @@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig index 8f6e337..e0aa660 100644 --- a/src/northbridge/via/cx700/Kconfig +++ b/src/northbridge/via/cx700/Kconfig @@ -3,7 +3,7 @@ config NORTHBRIDGE_VIA_CX700 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HAVE_HARD_RESET - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select SMP # TODO: What should be the per-chipset default value here? diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 3e58563..7c216d9 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -19,7 +19,7 @@ config SOUTHBRIDGE_AMD_AGESA_HUDSON bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_USBDEBUG config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index e643aa8..d606feb 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -19,7 +19,7 @@ config SOUTHBRIDGE_AMD_AMD8111 bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index e98d3ed..c7c96fa 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -19,7 +19,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB700 bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select AMD_SB_CIMX if SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 554d8c7..8747f57 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -20,7 +20,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 bool default n - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select AMD_SB_CIMX if SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index aa30e56..6572157 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -20,7 +20,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB900 bool default n - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select AMD_SB_CIMX if SOUTHBRIDGE_AMD_CIMX_SB900 diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 4ae4641..d859207 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -19,7 +19,7 @@ config SOUTHBRIDGE_AMD_SB600 bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index bde48fe..896b7b7 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -24,7 +24,7 @@ if SOUTHBRIDGE_AMD_SB700 config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index 4d0e7f6..e0bf81c 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -19,7 +19,7 @@ config SOUTHBRIDGE_AMD_SB800 bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 5dd492c..59ad5ed 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -27,7 +27,7 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 config SOUTH_BRIDGE_OPTIONS # dummy def_bool y - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET select HAVE_USBDEBUG select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/esb6300/Kconfig b/src/southbridge/intel/esb6300/Kconfig index 01f719e..eb67d29 100644 --- a/src/southbridge/intel/esb6300/Kconfig +++ b/src/southbridge/intel/esb6300/Kconfig @@ -1,4 +1,4 @@ config SOUTHBRIDGE_INTEL_ESB6300 bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig index e0acc63..b9abe1c 100644 --- a/src/southbridge/intel/i3100/Kconfig +++ b/src/southbridge/intel/i3100/Kconfig @@ -1,6 +1,6 @@ config SOUTHBRIDGE_INTEL_I3100 bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET if SOUTHBRIDGE_INTEL_I3100 diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig index 839f735..93d62c0 100644 --- a/src/southbridge/intel/i82801ax/Kconfig +++ b/src/southbridge/intel/i82801ax/Kconfig @@ -19,7 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801AX bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig index 162f40a..7238368 100644 --- a/src/southbridge/intel/i82801bx/Kconfig +++ b/src/southbridge/intel/i82801bx/Kconfig @@ -19,7 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801BX bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801cx/Kconfig b/src/southbridge/intel/i82801cx/Kconfig index 3e01cb8..fda3580 100644 --- a/src/southbridge/intel/i82801cx/Kconfig +++ b/src/southbridge/intel/i82801cx/Kconfig @@ -1,4 +1,4 @@ config SOUTHBRIDGE_INTEL_I82801CX bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index bad9936..d0c1fb6 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -21,6 +21,6 @@ config SOUTHBRIDGE_INTEL_I82801DX bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig index 23a68b8..4fccbe4 100644 --- a/src/southbridge/intel/i82801ex/Kconfig +++ b/src/southbridge/intel/i82801ex/Kconfig @@ -1,5 +1,5 @@ config SOUTHBRIDGE_INTEL_I82801EX bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index a991f60..c709a65 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -19,7 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801GX bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 36cfefb..1ff924d 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -20,7 +20,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index f79e963..f2f8fd3 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -24,7 +24,7 @@ if SOUTHBRIDGE_INTEL_LYNXPOINT config SOUTH_BRIDGE_OPTIONS # dummy def_bool y - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index b6f718e..ae4c572 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -2,7 +2,7 @@ config SOUTHBRIDGE_NVIDIA_CK804 bool select HAVE_HARD_RESET select HAVE_USBDEBUG - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC if SOUTHBRIDGE_NVIDIA_CK804 diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index cd6009d..2e805db 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -1,7 +1,7 @@ config SOUTHBRIDGE_NVIDIA_MCP55 bool select HAVE_USBDEBUG - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_HARD_RESET if SOUTHBRIDGE_NVIDIA_MCP55 diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 03dd6b1..ffea627 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -1,6 +1,6 @@ config SOUTHBRIDGE_SIS_SIS966 bool - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index c3854c9..9a6d68d 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -20,7 +20,7 @@ config SOUTHBRIDGE_VIA_VT8237R bool select HAVE_DEBUG_SMBUS - select IOAPIC + select IOAPIC if !DRIVERS_GENERIC_IOAPIC if SOUTHBRIDGE_VIA_VT8237R

1 0

Patch set updated for coreboot: 664d34f Asus F2A85-M Cleanup the PCIe config
by David Hendricks 06 May '13

06 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3194 -gerrit commit 664d34fa474d62409c05631b62cf64d3df222701 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat May 4 00:08:34 2013 +0200 Asus F2A85-M Cleanup the PCIe config Document the lane assignment from BKDG datasheet. Assign the lanes correctly to the physical slots on the motherboard. UMI is connected to SB via 4x PCIe bridge 8 blue x16 slot is not shared with DDI and is routed through PCIe bridge 2 black x86 slot is fact x4 slot and uses all 4 GPP from CPU Assume that DDI is on out-of-PCIe-band lanes. Change sizeof(type) * 6 to sizeof(variable). I think the cleanup part may be applied to other boards. Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR? Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 133 ++++++++++----------- .../asus/f2a85-m/PlatformGnbPcieComplex.h | 40 ------- 2 files changed, 65 insertions(+), 108 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 8ee6707..e47c7bf 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -26,58 +26,75 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE +/* + +From fam15h BKDG: Table 45: Lane Id Mapping + +Lane Id +0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 +1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 +2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 +3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 +4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 +5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 +6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 +7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 +8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI +9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI +10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI +11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI +12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI +13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI +14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI +15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI +16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI +17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI +18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI +19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI +20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI +21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI +22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI +23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI +24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) +25 DP0_TX[P,N]1 +26 DP0_TX[P,N]2 +27 DP0_TX[P,N]3 +28 DP1_TX[P,N]0 +29 DP1_TX[P,N]1 +30 DP1_TX[P,N]2 +31 DP1_TX[P,N]3 +32 DP2_TX[P,N]0 +33 DP2_TX[P,N]1 +34 DP2_TX[P,N]2 +35 DP2_TX[P,N]3 +36 DP2_TX[P,N]4 +37 DP2_TX[P,N]5 +38 DP2_TX[P,N]6 +*/ + PCIe_PORT_DESCRIPTOR PortList [] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + /* PCIe port, Lanes 8:23, PCI Device Number 2 blue x16 slot */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 16:23, PCI Device Number 3 */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ + /* PCIe port, Lanes 4, PCI Device Number 4, black x16 slot (in fact x4) */ { 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - - /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/ - { - 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - -#if 1 - /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 4 UMI link to SB, PCI Device Number 8 */ { DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, -#endif }; + /* this is not known if it is completely correct VGA/DVI works, HDMI untested */ + PCIe_DDI_DESCRIPTOR DdiList [] = { // DP0 to HDMI0/DP { @@ -94,29 +111,9 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { // DP2 to HDMI1/DP { 0, -// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38), PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) }, - // GFX Lane 15-12 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) - }, - // GFX Lane 11-8 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) - }, - // GFX Lane 7-4 - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) - } }; PCIe_COMPLEX_DESCRIPTOR Trinity = { @@ -159,9 +156,9 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + AllocHeapParams.RequestedBufferSize = sizeof (Trinity) + + sizeof (DdiList) + + sizeof (PortList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -174,33 +171,33 @@ OemCustomizeInitEarly ( TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof (Trinity); TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + AllocHeapParams.BufferPtr += sizeof (PortList); TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (TrinityPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof (Trinity), &InitEarly->StdHeader); LibAmdMemFill (TrinityPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 7, + sizeof (PortList), &InitEarly->StdHeader); LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 6, + sizeof (DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (Trinity), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PortList), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (DdiList), &InitEarly->StdHeader); - ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; } diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h index 3f14805..b3c69cf 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h @@ -24,46 +24,6 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly

1 0

Patch set updated for coreboot: 9f0d335 haswell: use tsc for udelay()
by David Hendricks 06 May '13

06 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3169 -gerrit commit 9f0d335a1744d6cc040decd0ce867b35b3080fce Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:39:28 2013 -0500 haswell: use tsc for udelay() Instead of using the local apic timer for udelay() use the tsc. That way SMM, romstage, and ramstage all use the same delay functionality. Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 3 +- src/cpu/intel/haswell/Makefile.inc | 3 ++ src/cpu/intel/haswell/tsc_freq.c | 31 +++++++++++++++ src/northbridge/intel/haswell/Makefile.inc | 1 - src/northbridge/intel/haswell/udelay.c | 63 ------------------------------ 5 files changed, 36 insertions(+), 65 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 13861f9..152059f 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE select SMM_TSEG select SMM_MODULES select RELOCATABLE_MODULES diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 90ffd66..60c061d 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,7 +1,9 @@ ramstage-y += haswell_init.c subdirs-y += ../../x86/name ramstage-y += mp_init.c +ramstage-y += tsc_freq.c romstage-y += romstage.c +romstage-y += tsc_freq.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c @@ -10,6 +12,7 @@ ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc diff --git a/src/cpu/intel/haswell/tsc_freq.c b/src/cpu/intel/haswell/tsc_freq.c new file mode 100644 index 0000000..0a78053 --- /dev/null +++ b/src/cpu/intel/haswell/tsc_freq.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include "cpu/intel/haswell/haswell.h" + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff); +} diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 896360d..b2ac85e 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail diff --git a/src/northbridge/intel/haswell/udelay.c b/src/northbridge/intel/haswell/udelay.c deleted file mode 100644 index f5d541e..0000000 --- a/src/northbridge/intel/haswell/udelay.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include "cpu/intel/haswell/haswell.h" - -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_PLATFORM_INFO); - divisor = (msr.lo >> 8) & 0xff; - - d = HASWELL_BCLK * divisor; - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); -}

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coreboot-gerrit May 2013