coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 35b3b9a haswell: use tsc for udelay()
by Aaron Durbin 07 May '13

07 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3169 -gerrit commit 35b3b9ac4eef287b51417bcf8ba7b8210151a2d3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:39:28 2013 -0500 haswell: use tsc for udelay() Instead of using the local apic timer for udelay() use the tsc. That way SMM, romstage, and ramstage all use the same delay functionality. Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 3 +- src/cpu/intel/haswell/Makefile.inc | 3 ++ src/cpu/intel/haswell/tsc_freq.c | 31 +++++++++++++++ src/northbridge/intel/haswell/Makefile.inc | 1 - src/northbridge/intel/haswell/udelay.c | 63 ------------------------------ 5 files changed, 36 insertions(+), 65 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 13861f9..152059f 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE select SMM_TSEG select SMM_MODULES select RELOCATABLE_MODULES diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 90ffd66..60c061d 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,7 +1,9 @@ ramstage-y += haswell_init.c subdirs-y += ../../x86/name ramstage-y += mp_init.c +ramstage-y += tsc_freq.c romstage-y += romstage.c +romstage-y += tsc_freq.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c @@ -10,6 +12,7 @@ ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc diff --git a/src/cpu/intel/haswell/tsc_freq.c b/src/cpu/intel/haswell/tsc_freq.c new file mode 100644 index 0000000..0a78053 --- /dev/null +++ b/src/cpu/intel/haswell/tsc_freq.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include "cpu/intel/haswell/haswell.h" + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff); +} diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 896360d..b2ac85e 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail diff --git a/src/northbridge/intel/haswell/udelay.c b/src/northbridge/intel/haswell/udelay.c deleted file mode 100644 index f5d541e..0000000 --- a/src/northbridge/intel/haswell/udelay.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include "cpu/intel/haswell/haswell.h" - -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_PLATFORM_INFO); - divisor = (msr.lo >> 8) & 0xff; - - d = HASWELL_BCLK * divisor; - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); -}

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Patch set updated for coreboot: d031db0 x86: add TSC_CONSTANT_RATE option
by Aaron Durbin 07 May '13

07 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3168 -gerrit commit d031db051702381a6f7bb73a310fc01f0b776484 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:27:09 2013 -0500 x86: add TSC_CONSTANT_RATE option Some boards use the local apic for udelay(), but they also provide their own implementation of udelay() for SMM. The reason for using the local apic for udelay() in ramstage is to not have to pay the penalty of calibrating the TSC frequency. Therefore provide a TSC_CONSTANT_RATE option to indicate that TSC calibration is not needed. Instead rely on the presence of a tsc_freq_mhz() function provided by the cpu/board. Additionally, assume that if TSC_CONSTANT_RATE is selected the udelay() function in SMM will be the tsc. Change-Id: I1629c2fbe3431772b4e80495160584fb6f599e9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 7 +++++++ src/cpu/x86/tsc/Makefile.inc | 4 ++++ src/cpu/x86/tsc/delay_tsc.c | 27 ++++++++++++++++++++++++--- src/include/cpu/x86/tsc.h | 4 ++++ 4 files changed, 39 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5cf40fa..c64a8e4 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -25,6 +25,13 @@ config UDELAY_TSC bool default n +config TSC_CONSTANT_RATE + def_bool n + depends on UDELAY_TSC + help + This option asserts that the TSC ticks at a known constant rate. + Therefore, no TSC calibration is required. + config TSC_MONOTONIC_TIMER def_bool n depends on UDELAY_TSC diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 44bfe85..3bbae84 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,2 +1,6 @@ ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) +smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +endif diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index e4993d0..0540496 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -5,8 +5,16 @@ #include <smp/spinlock.h> #include <delay.h> +#if !defined(__PRE_RAM__) + static unsigned long clocks_per_usec; +#if CONFIG_TSC_CONSTANT_RATE +static unsigned long calibrate_tsc(void) +{ + return tsc_freq_mhz(); +} +#else /* CONFIG_TSC_CONSTANT_RATE */ #if !CONFIG_TSC_CALIBRATE_WITH_IO #define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ @@ -139,6 +147,7 @@ static unsigned long long calibrate_tsc(void) #endif /* CONFIG_TSC_CALIBRATE_WITH_IO */ +#endif /* CONFIG_TSC_CONSTANT_RATE */ void init_timer(void) { @@ -148,15 +157,27 @@ void init_timer(void) } } +static inline unsigned long get_clocks_per_usec(void) +{ + init_timer(); + return clocks_per_usec; +} +#else /* !defined(__PRE_RAM__) */ +/* romstage calls into cpu/board specific function every time. */ +static inline unsigned long get_clocks_per_usec(void) +{ + return tsc_freq_mhz(); +} +#endif /* !defined(__PRE_RAM__) */ + void udelay(unsigned us) { unsigned long long count; unsigned long long stop; unsigned long long clocks; - init_timer(); clocks = us; - clocks *= clocks_per_usec; + clocks *= get_clocks_per_usec(); count = rdtscll(); stop = clocks + count; while(stop > count) { @@ -165,7 +186,7 @@ void udelay(unsigned us) } } -#if CONFIG_TSC_MONOTONIC_TIMER +#if CONFIG_TSC_MONOTONIC_TIMER && !defined(__PRE_RAM__) && !defined(__SMM__) #include <timer.h> static struct monotonic_counter { diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 6ce7f5f..8e49a66 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -40,4 +40,8 @@ static inline unsigned long long rdtscll(void) } #endif +#if CONFIG_TSC_CONSTANT_RATE +unsigned long tsc_freq_mhz(void); +#endif + #endif /* CPU_X86_TSC_H */

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Patch set updated for coreboot: 1c00872 x86: harden tsc udelay() function
by Aaron Durbin 07 May '13

07 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3171 -gerrit commit 1c008726adcd67c9f18c92b30c58284c9e5a25a1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:55:14 2013 -0500 x86: harden tsc udelay() function Since the TSC udelay() fucntion can be used in SMM that means the TSC can count up to whatever value. The current loop was not handling TSC rollover properly. In most cases this should not matter as the TSC typically starts ticking at value 0, and it would take a very long time to roll it over. However, it is my understanding that this behavior is not guaranteed. Theoretically the TSC could start or be be written to with a large value that would cause the rollover. Change-Id: I2f11a5bc4f27d5543e74f8224811fa91e4a55484 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/tsc/delay_tsc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 0540496..0e2a9c0 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -172,18 +172,18 @@ static inline unsigned long get_clocks_per_usec(void) void udelay(unsigned us) { - unsigned long long count; - unsigned long long stop; - unsigned long long clocks; + unsigned long long start; + unsigned long long current; + unsigned long long clocks; + start = rdtscll(); clocks = us; clocks *= get_clocks_per_usec(); - count = rdtscll(); - stop = clocks + count; - while(stop > count) { + current = rdtscll(); + while((current - start) < clocks) { cpu_relax(); - count = rdtscll(); - } + current = rdtscll(); + } } #if CONFIG_TSC_MONOTONIC_TIMER && !defined(__PRE_RAM__) && !defined(__SMM__)

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Patch set updated for coreboot: eef0d15 coreboot: add thread cooperative multitasking
by Aaron Durbin 07 May '13

07 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3206 -gerrit commit eef0d15d451584a073e20c2e054f2930ae58e68c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon May 6 12:20:52 2013 -0500 coreboot: add thread cooperative multitasking The cooperative multitasking support allows the boot state machine to be ran cooperatively with other threads of work. The main thread still continues to run the boot state machine (src/lib/hardwaremain.c). All callbacks from the state machine are still ran synchronously from within the main thread's context. Without any other code added the only change to the boot sequence when cooperative multitasking is enabled is the queueing of an idlle thread. The idle thread is responsible for ensuring progress is made by calling timer callbacks. The main thread can yield to any other threads in the system. That means that anyone that spins up a thread must ensure no shared resources are used from 2 or more execution contexts. The support is originally intentioned to allow for long work itesm with busy loops to occur in parallel during a boot. Note that the intention on when to yield a thread will be on calls to udelay(). Change-Id: Ia4d67a38665b12ce2643474843a93babd8a40c77 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 16 ++ src/arch/armv7/include/arch/cpu.h | 5 + src/arch/x86/include/arch/cpu.h | 5 + src/include/thread.h | 82 +++++++++ src/lib/Makefile.inc | 1 + src/lib/hardwaremain.c | 3 + src/lib/thread.c | 376 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 488 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index ce7f400..5dcd7ba 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -324,6 +324,22 @@ config TIMER_QUEUE help Provide a timer queue for performing time-based callbacks. +config COOP_MULTITASKING + def_bool n + depends on TIMER_QUEUE + help + Cooperative multitasking allows callbacks to be multiplexed on the + main thread of ramstage. With this enabled it allows for multiple + execution paths to take place when they have udelay() calls within + their code. + +config NUM_THREADS + int + default 4 + depends on COOP_MULTITASKING + help + How many execution threads to cooperatively multitask with. + config HIGH_SCRATCH_MEMORY_SIZE hex default 0x0 diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h index 20a12c9..5621aed 100644 --- a/src/arch/armv7/include/arch/cpu.h +++ b/src/arch/armv7/include/arch/cpu.h @@ -30,9 +30,14 @@ struct cpu_driver { struct cpu_device_id *id_table; }; +struct thread; + struct cpu_info { device_t cpu; unsigned long index; +#if CONFIG_COOP_MULTITASKING + struct thread *thread; +#endif }; struct cpuinfo_arm { diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index a3555d8..4a31088 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -164,9 +164,14 @@ struct cpu_driver *find_cpu_driver(struct device *cpu); #include <arch/io.h> #endif +struct thread; + struct cpu_info { device_t cpu; unsigned int index; +#if CONFIG_COOP_MULTITASKING + struct thread *thread; +#endif }; static inline struct cpu_info *cpu_info(void) diff --git a/src/include/thread.h b/src/include/thread.h new file mode 100644 index 0000000..6f3419f --- /dev/null +++ b/src/include/thread.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef THREAD_H_ +#define THREAD_H_ + +#include <stddef.h> +#include <stdint.h> +#include <bootstate.h> +#include <timer.h> +#include <arch/cpu.h> + +#if CONFIG_COOP_MULTITASKING && !defined(__SMM__) && !defined(__PRE_RAM__) + +struct thread { + int id; + uintptr_t stack_current; + uintptr_t stack_orig; + struct thread *next; + void (*entry)(void *); + void *entry_arg; + int can_yield; +}; + +void threads_initialize(void); +/* Run func(arrg) on a new thread. Return 0 on successful start of thread, < 0 + * when thread could not be started. Note that the thread will block the + * current state in the boot state machine until it is complete. */ +int thread_run(void (*func)(void *), void *arg); +/* thread_run_until is the same as thread_run() except that it blocks state + * transitions from occuring in the (state, seq) pair of the boot state + * machine. */ +int thread_run_until(void (*func)(void *), void *arg, + boot_state_t state, boot_state_sequence_t seq); +/* Return 0 on successful yield for the given amount of time, < 0 when thread + * did not yield. */ +int thread_yield_microseconds(unsigned microsecs); + +/* Allow and prevent thread cooperation on current running thread. By default + * all threads are marked to be cooperative. That means a thread can yeild + * to another thread at a pre-determined switch point. Current there is + * only a single place where switching may occur: a call to udelay(). */ +void thread_cooperate(void); +void thread_prevent_coop(void); + +static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) +{ + ci->thread = NULL; +} + +/* Architecture specific thread functions. */ +void asmlinkage switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack); +/* Set up the stack frame for a new thread so that a switch_to_thread() call + * will enter the thread_entry() function with arg as a parameter. The + * saved_stack field in the struct thread needs to be updated accordingly. */ +void arch_prepare_thread(struct thread *t, + void asmlinkage (*thread_entry)(void *), void *arg); +#else +static inline void threads_initialize(void) {} +static inline int thread_run(void (*func)(void *), void *arg) { return -1; } +static inline int thread_yield_microseconds(unsigned microsecs) { return -1; } +static inline void thread_cooperate(void) {} +static inline void thread_prevent_coop(void) {} +static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { } +#endif + +#endif /* THREAD_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 7306e6d..2600aa5 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -90,6 +90,7 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c ramstage-y += memrange.c +ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c # The CBMEM implementations are chosen based on CONFIG_DYNAMIC_CBMEM. diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 13aa512..16508e7 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -39,6 +39,7 @@ #endif #include <timer.h> #include <timestamp.h> +#include <thread.h> #if BOOT_STATE_DEBUG #define BS_DEBUG_LVL BIOS_DEBUG @@ -465,6 +466,8 @@ void hardwaremain(int boot_complete) hard_reset(); } + threads_initialize(); + /* Schedule the static boot state entries. */ boot_state_schedule_static_entries(); diff --git a/src/lib/thread.c b/src/lib/thread.c new file mode 100644 index 0000000..6508bfa --- /dev/null +++ b/src/lib/thread.c @@ -0,0 +1,376 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> +#include <arch/cpu.h> +#include <bootstate.h> +#include <console/console.h> +#include <thread.h> + +static void idle_thread_init(void); + +/* There needs to be at least one thread to run the ramstate state machine. */ +#define TOTAL_NUM_THREADS (CONFIG_NUM_THREADS + 1) +extern char thread_stacks[CONFIG_NUM_THREADS*CONFIG_STACK_SIZE]; + +/* Storage space for the thread structs .*/ +static struct thread all_threads[TOTAL_NUM_THREADS]; + +/* All runnable (but not running) and free threads are kept on their + * respective lists. */ +static struct thread *runnable_threads; +static struct thread *free_threads; + +static inline struct cpu_info *thread_cpu_info(const struct thread *t) +{ + return (void *)(t->stack_orig); +} + +static inline int thread_can_yield(const struct thread *t) +{ + return (t != NULL && t->can_yield); +} + +/* Assumes current cpu info can switch. */ +static inline struct thread *cpu_info_to_thread(const struct cpu_info *ci) +{ + return ci->thread; +} + +static inline struct thread *current_thread(void) +{ + return cpu_info_to_thread(cpu_info()); +} + +static inline int thread_list_empty(struct thread **list) +{ + return *list == NULL; +} + +static inline struct thread *pop_thread(struct thread **list) +{ + struct thread *t; + + t = *list; + *list = t->next; + t->next = NULL; + return t; +} + +static inline void push_thread(struct thread **list, struct thread *t) +{ + t->next = *list; + *list = t; +} + +static inline void push_runnable(struct thread *t) +{ + push_thread(&runnable_threads, t); +} + +static inline struct thread *pop_runnable(void) +{ + return pop_thread(&runnable_threads); +} + +static inline struct thread *get_free_thread(void) +{ + struct thread *t; + struct cpu_info *ci; + struct cpu_info *new_ci; + + if (thread_list_empty(&free_threads)) + return NULL; + + t = pop_thread(&free_threads); + + ci = cpu_info(); + + /* Initialize the cpu_info structure on the new stack. */ + new_ci = thread_cpu_info(t); + *new_ci = *ci; + new_ci->thread = t; + + /* Reset the current stack value to the original. */ + t->stack_current = t->stack_orig; + + return t; +} + +static inline void free_thread(struct thread *t) +{ + push_thread(&free_threads, t); +} + +/* The idle thread is ran whenever there isn't anything else that is runnable. + * It's sole responsibility is to ensure progress is made by running the timer + * callbacks. */ +static void idle_thread(void *unused) +{ + /* This thread never voluntarily yields. */ + thread_prevent_coop(); + while (1) { + timers_run(); + } +} + +static void schedule(struct thread *t) +{ + struct thread *current = current_thread(); + + /* If t is NULL need to find new runnable thread. */ + if (t == NULL) { + if (thread_list_empty(&runnable_threads)) + die("Runnable thread list is empty!\n"); + t = pop_runnable(); + } else { + /* current is still runnable. */ + push_runnable(current); + } + switch_to_thread(t->stack_current, &current->stack_current); +} + +static void terminate_thread(struct thread *t) +{ + free_thread(t); + schedule(NULL); +} + +static void asmlinkage call_wrapper(void *unused) +{ + struct thread *current = current_thread(); + + current->entry(current->entry_arg); + terminate_thread(current); +} + +/* Block the current state transitions until thread is complete. */ +static void asmlinkage call_wrapper_block_current(void *unused) +{ + struct thread *current = current_thread(); + + boot_state_current_block(); + current->entry(current->entry_arg); + boot_state_current_unblock(); + terminate_thread(current); +} + +struct block_boot_state { + boot_state_t state; + boot_state_sequence_t seq; +}; + +/* Block the provided state until thread is complete. */ +static void asmlinkage call_wrapper_block_state(void *arg) +{ + struct block_boot_state *bbs = arg; + struct thread *current = current_thread(); + + boot_state_block(bbs->state, bbs->seq); + current->entry(current->entry_arg); + boot_state_unblock(bbs->state, bbs->seq); + terminate_thread(current); +} + +/* Prepare a thread so that it starts by executing thread_entry(thread_arg). + * Within thread_entry() it will call func(arg). */ +static void prepare_thread(struct thread *t, void *func, void *arg, + void asmlinkage (*thread_entry)(void *), + void *thread_arg) +{ + /* Stash the function and argument to run. */ + t->entry = func; + t->entry_arg = arg; + + /* All new threads can yield by default. */ + t->can_yield = 1; + + arch_prepare_thread(t, thread_entry, thread_arg); +} + +static void thread_resume_from_timeout(struct timeout_callback *tocb) +{ + struct thread *to; + + to = tocb->priv; + schedule(to); +} + +static void idle_thread_init(void) +{ + struct thread *t; + + t = get_free_thread(); + + if (t == NULL) { + die("No threads available for idle thread!\n"); + } + + /* Queue idle thread to run once all other threads have yielded. */ + prepare_thread(t, idle_thread, NULL, call_wrapper, NULL); + push_runnable(t); + /* Mark the currently executing thread to cooperate. */ + thread_cooperate(); +} + +/* Don't inline this function so the timeout_callback won't have its storage + * space on the stack cleaned up before the call to schedule(). */ +static int __attribute__((noinline)) +thread_yield_timed_callback(struct timeout_callback *tocb, unsigned microsecs) +{ + tocb->priv = current_thread(); + tocb->callback = thread_resume_from_timeout; + + if (timer_sched_callback(tocb, microsecs)) + return -1; + + /* The timer callback will wake up the current thread. */ + schedule(NULL); + return 0; +} + +static void *thread_alloc_space(struct thread *t, size_t bytes) +{ + /* Allocate the amount of space on the stack keeping the stack + * aligned to the pointer size. */ + t->stack_current -= ALIGN_UP(bytes, sizeof(uintptr_t)); + + return (void *)t->stack_current; +} + +void threads_initialize(void) +{ + int i; + struct thread *t; + char *stack_top; + struct cpu_info *ci; + + /* Initialize the BSP thread first. The cpu_info structure is assumed + * to be just under the top of the stack. */ + t = &all_threads[0]; + ci = cpu_info(); + ci->thread = t; + t->stack_orig = (uintptr_t)ci; + t->id = 0; + + stack_top = &thread_stacks[CONFIG_STACK_SIZE] - sizeof(struct cpu_info); + for (i = 1; i < TOTAL_NUM_THREADS; i++) { + t = &all_threads[i]; + t->stack_orig = (uintptr_t)stack_top; + t->id = i; + stack_top += CONFIG_STACK_SIZE; + free_thread(t); + } + + idle_thread_init(); +} + +int thread_run(void (*func)(void *), void *arg) +{ + struct thread *current; + struct thread *t; + + current = current_thread(); + + if (!thread_can_yield(current)) { + printk(BIOS_ERR, + "thread_run() called from non-yielding context!\n"); + return -1; + } + + t = get_free_thread(); + + if (t == NULL) { + printk(BIOS_ERR, "thread_run() No more threads!\n"); + return -1; + } + + prepare_thread(t, func, arg, call_wrapper_block_current, NULL); + schedule(t); + + return 0; +} + +int thread_run_until(void (*func)(void *), void *arg, + boot_state_t state, boot_state_sequence_t seq) +{ + struct thread *current; + struct thread *t; + struct block_boot_state *bbs; + + current = current_thread(); + + if (!thread_can_yield(current)) { + printk(BIOS_ERR, + "thread_run() called from non-yielding context!\n"); + return -1; + } + + t = get_free_thread(); + + if (t == NULL) { + printk(BIOS_ERR, "thread_run() No more threads!\n"); + return -1; + } + + bbs = thread_alloc_space(t, sizeof(*bbs)); + bbs->state = state; + bbs->seq = seq; + prepare_thread(t, func, arg, call_wrapper_block_state, bbs); + schedule(t); + + return 0; +} + +int thread_yield_microseconds(unsigned microsecs) +{ + struct thread *current; + struct timeout_callback tocb; + + current = current_thread(); + + if (!thread_can_yield(current)) + return -1; + + if (thread_yield_timed_callback(&tocb, microsecs)) + return -1; + + return 0; +} + +void thread_cooperate(void) +{ + struct thread *current; + + current = current_thread(); + + if (current != NULL) + current->can_yield = 1; +} + +void thread_prevent_coop(void) +{ + struct thread *current; + + current = current_thread(); + + if (current != NULL) + current->can_yield = 0; +}

1 0

Patch set updated for coreboot: d96ec2b x86: add thread support
by Aaron Durbin 07 May '13

07 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3207 -gerrit commit d96ec2b94d4c07452cf6a9ab8e77af6f48a42476 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon May 6 12:22:23 2013 -0500 x86: add thread support Thread support is added for the x86 architecture. Both the local apic and the tsc udelay() functions have a call to thread_yield_microseconds() so as to provide an opportunity to run pending threads. Change-Id: Ie39b9eb565eb189676c06645bdf2a8720fe0636a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 2 +- src/arch/x86/lib/Makefile.inc | 2 ++ src/arch/x86/lib/c_start.S | 9 ++++++ src/arch/x86/lib/thread.c | 58 ++++++++++++++++++++++++++++++++++++++ src/arch/x86/lib/thread_switch.S | 58 ++++++++++++++++++++++++++++++++++++++ src/cpu/intel/haswell/mp_init.c | 2 ++ src/cpu/x86/lapic/apic_timer.c | 4 +++ src/cpu/x86/lapic/lapic_cpu_init.c | 2 ++ src/cpu/x86/tsc/delay_tsc.c | 4 +++ 9 files changed, 140 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 5dcd7ba..9fde0e4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -326,7 +326,7 @@ config TIMER_QUEUE config COOP_MULTITASKING def_bool n - depends on TIMER_QUEUE + depends on TIMER_QUEUE && ARCH_X86 help Cooperative multitasking allows callbacks to be multiplexed on the main thread of ramstage. With this enabled it allows for multiple diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 82f4e62..7cdd3c6 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -9,6 +9,8 @@ ramstage-y += memset.c ramstage-y += memcpy.c ramstage-y += ebda.c ramstage-y += rom_media.c +ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c +ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S romstage-$(CONFIG_EARLY_CONSOLE) += romstage_console.c romstage-y += cbfs_and_run.c diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index 32af0cc..e9d072f 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -10,6 +10,11 @@ _stack: .space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE _estack: +#if CONFIG_COOP_MULTITASKING +.global thread_stacks +thread_stacks: +.space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS +#endif .section ".textfirst", "ax", @progbits .code32 @@ -45,6 +50,10 @@ _start: /* set new stack */ movl $_estack, %esp +#if CONFIG_COOP_MULTITASKING + /* Push the thread pointer. */ + pushl $0 +#endif /* Push the cpu index and struct cpu */ pushl $0 pushl $0 diff --git a/src/arch/x86/lib/thread.c b/src/arch/x86/lib/thread.c new file mode 100644 index 0000000..06f8a15 --- /dev/null +++ b/src/arch/x86/lib/thread.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <thread.h> + +/* The stack frame looks like the following after a pushad instruction. */ +struct pushad_regs { + uint32_t edi; /* Offset 0x00 */ + uint32_t esi; /* Offset 0x04 */ + uint32_t ebp; /* Offset 0x08 */ + uint32_t esp; /* Offset 0x0c */ + uint32_t ebx; /* Offset 0x10 */ + uint32_t edx; /* Offset 0x14 */ + uint32_t ecx; /* Offset 0x18 */ + uint32_t eax; /* Offset 0x1c */ +}; + +static inline uintptr_t push_stack(uintptr_t cur_stack, uintptr_t value) +{ + uintptr_t *addr; + + cur_stack -= sizeof(value); + addr = (uintptr_t *)cur_stack; + *addr = value; + return cur_stack; +} + +void arch_prepare_thread(struct thread *t, + void asmlinkage (*thread_entry)(void *), void *arg) +{ + uintptr_t stack = t->stack_current; + + /* Imitate thread_entry(t) with return address of 0. thread_entry() + * is assumed to never return. */ + stack = push_stack(stack, (uintptr_t)arg); + stack = push_stack(stack, (uintptr_t)0); + stack = push_stack(stack, (uintptr_t)thread_entry); + /* Make room for the registers. Ignore intial values. */ + stack -= sizeof(struct pushad_regs); + + t->stack_current = stack; +} diff --git a/src/arch/x86/lib/thread_switch.S b/src/arch/x86/lib/thread_switch.S new file mode 100644 index 0000000..8de1948 --- /dev/null +++ b/src/arch/x86/lib/thread_switch.S @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +.code32 +.text + +/* + * stack layout after pushad: + * +------------+ + * | save stack | <-- esp + 0x28 + * +------------+ + * | new stack | <-- esp + 0x24 + * +------------+ + * | ret addr | <-- esp + 0x20 + * +------------+ + * | eax | <-- esp + 0x1c + * +------------+ + * | ecx | <-- esp + 0x18 + * +------------+ + * | edx | <-- esp + 0x14 + * +------------+ + * | ebx | <-- esp + 0x10 + * +------------+ + * | orig esp | <-- esp + 0x0c + * +------------+ + * | ebp | <-- esp + 0x08 + * +------------+ + * | esi | <-- esp + 0x04 + * +------------+ + * | edi | <-- esp + 0x00 + * +------------+ + */ +.globl switch_to_thread +switch_to_thread: + pusha + /* Save the current stack */ + movl 0x28(%esp), %ebx + movl %esp, (%ebx) + /* Switch to the new stack. */ + movl 0x24(%esp), %eax + movl %eax, %esp + popa + ret diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index deba629..357fbb2 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -36,6 +36,7 @@ #include <lib.h> #include <smp/atomic.h> #include <smp/spinlock.h> +#include <thread.h> #include "haswell.h" /* This needs to match the layout in the .module_parametrs section. */ @@ -163,6 +164,7 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) info = cpu_info(); info->index = cpu; info->cpu = cpu_devs[cpu]; + thread_init_cpu_info_non_bsp(info); apic_id_table[info->index] = lapicid(); info->cpu->path.apic.apic_id = apic_id_table[info->index]; diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 749fef0..e5ce62f 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <console/console.h> #include <delay.h> +#include <thread.h> #include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/car.h> @@ -95,6 +96,9 @@ void udelay(u32 usecs) { u32 start, value, ticks; + if (!thread_yield_microseconds(usecs)) + return; + if (!timer_fsb || (lapic_read(LAPIC_LVTT) & (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) != (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 69430d5..fbc8aa4 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -32,6 +32,7 @@ #include <smp/spinlock.h> #include <cpu/cpu.h> #include <cpu/intel/speedstep.h> +#include <thread.h> #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 /* This is a lot more paranoid now, since Linux can NOT handle @@ -292,6 +293,7 @@ int start_cpu(device_t cpu) info = (struct cpu_info *)stack_end; info->index = index; info->cpu = cpu; + thread_init_cpu_info_non_bsp(info); /* Advertise the new stack and index to start_cpu */ secondary_stack = stack_end; diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 0e2a9c0..b8f2503 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -4,6 +4,7 @@ #include <cpu/x86/tsc.h> #include <smp/spinlock.h> #include <delay.h> +#include <thread.h> #if !defined(__PRE_RAM__) @@ -176,6 +177,9 @@ void udelay(unsigned us) unsigned long long current; unsigned long long clocks; + if (!thread_yield_microseconds(us)) + return; + start = rdtscll(); clocks = us; clocks *= get_clocks_per_usec();

1 0

Patch set updated for coreboot: 25fb3ce boot state: add ability to block state transitions
by Aaron Durbin 07 May '13

07 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3204 -gerrit commit 25fb3cec3d7b7f21dbb7de0193274cb7eca0eee0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon May 6 10:50:19 2013 -0500 boot state: add ability to block state transitions In order to properly sequence the boot state machine it's important that outside code can block the transition from one state to the next. When timers are not involved there's no reason for any of the existing code to block a state transition. However, if there is a timer callback that needs to complete by a certain point in the boot sequence it is necessary to place a block for the given state. To that end, 4 new functions are added to provide the API for blocking a state. 1. boot_state_block(boot_state_t state, boot_state_sequence_t seq); 2. boot_state_unblock(boot_state_t state, boot_state_sequence_t seq); 3. boot_state_current_block(void); 4. boot_state_current_unblock(void); Change-Id: Ieb37050ff652fd85a6b1e0e2f81a1a2807bab8e0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootstate.h | 8 +++ src/lib/hardwaremain.c | 137 +++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 126 insertions(+), 19 deletions(-) diff --git a/src/include/bootstate.h b/src/include/bootstate.h index f732d1e..0370c36 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -156,6 +156,14 @@ int boot_state_sched_on_entry(struct boot_state_callback *bscb, int boot_state_sched_on_exit(struct boot_state_callback *bscb, boot_state_t state); +/* Block/Unblock the (state, seq) pair from transitioning. Returns 0 on + * success < 0 when the phase of the (state,seq) has already ran. */ +int boot_state_block(boot_state_t state, boot_state_sequence_t seq); +int boot_state_unblock(boot_state_t state, boot_state_sequence_t seq); +/* Block/Unblock current state phase from transitioning. */ +void boot_state_current_block(void); +void boot_state_current_unblock(void); + /* Entry into the boot state machine. */ void hardwaremain(int boot_complete); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 8e5481e..39aae6d 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -72,10 +72,18 @@ struct boot_state_times { struct mono_time samples[MAX_TIME_SAMPLES]; }; +/* The prologue (BS_ON_ENTRY) and epilogue (BS_ON_EXIT) of a state can be + * blocked from transitioning to the next (state,seq) pair. When the blockers + * field is 0 a transition may occur. */ +struct boot_phase { + struct boot_state_callback *callbacks; + int blockers; +}; + struct boot_state { const char *name; boot_state_t id; - struct boot_state_callback *seq_callbacks[2]; + struct boot_phase phases[2]; boot_state_t (*run_state)(void *arg); void *arg; int complete : 1; @@ -89,7 +97,7 @@ struct boot_state { { \ .name = #state_, \ .id = state_, \ - .seq_callbacks = { NULL, NULL }, \ + .phases = { { NULL, 0 }, { NULL, 0 } }, \ .run_state = run_func_, \ .arg = NULL, \ .complete = 0, \ @@ -299,29 +307,55 @@ static void bs_run_timers(int drain) {} static void bs_call_callbacks(struct boot_state *state, boot_state_sequence_t seq) { - while (state->seq_callbacks[seq] != NULL) { - struct boot_state_callback *bscb; + struct boot_phase *phase = &state->phases[seq]; + + while (1) { + if (phase->callbacks != NULL) { + struct boot_state_callback *bscb; - /* Remove the first callback. */ - bscb = state->seq_callbacks[seq]; - state->seq_callbacks[seq] = bscb->next; - bscb->next = NULL; + /* Remove the first callback. */ + bscb = phase->callbacks; + phase->callbacks = bscb->next; + bscb->next = NULL; #if BOOT_STATE_DEBUG - printk(BS_DEBUG_LVL, "BS: callback (%p) @ %s.\n", - bscb, bscb->location); + printk(BS_DEBUG_LVL, "BS: callback (%p) @ %s.\n", + bscb, bscb->location); #endif - bscb->callback(bscb->arg); + bscb->callback(bscb->arg); + + continue; + } + + /* All callbacks are complete and there are no blockers for + * this state. Therefore, this part of the state is complete. */ + if (!phase->blockers) + break; + + /* Something is blocking this state from transitioning. As + * there are no more callbacks a pending timer needs to be + * ran to unblock the state. */ + bs_run_timers(0); } } -static void bs_walk_state_machine(boot_state_t current_state_id) +/* Keep track of the current state. */ +static struct state_tracker { + boot_state_t state_id; + boot_state_sequence_t seq; +} current_phase = { + .state_id = BS_PRE_DEVICE, + .seq = BS_ON_ENTRY, +}; + +static void bs_walk_state_machine(void) { while (1) { struct boot_state *state; + boot_state_t next_id; - state = &boot_states[current_state_id]; + state = &boot_states[current_phase.state_id]; if (state->complete) { printk(BIOS_EMERG, "BS: %s state already executed.\n", @@ -335,17 +369,25 @@ static void bs_walk_state_machine(boot_state_t current_state_id) bs_sample_time(state); - bs_call_callbacks(state, BS_ON_ENTRY); + bs_call_callbacks(state, current_phase.seq); + /* Update the current sequence so that any calls to block the + * current state from the run_state() function will place a + * block on the correct phase. */ + current_phase.seq = BS_ON_EXIT; bs_sample_time(state); - current_state_id = state->run_state(state->arg); + next_id = state->run_state(state->arg); printk(BS_DEBUG_LVL, "BS: Exiting %s state.\n", state->name); bs_sample_time(state); - bs_call_callbacks(state, BS_ON_EXIT); + bs_call_callbacks(state, current_phase.seq); + + /* Update the current phase with new state id and sequence. */ + current_phase.state_id = next_id; + current_phase.seq = BS_ON_ENTRY; bs_sample_time(state); @@ -367,8 +409,8 @@ static int boot_state_sched_callback(struct boot_state *state, return -1; } - bscb->next = state->seq_callbacks[seq]; - state->seq_callbacks[seq] = bscb; + bscb->next = state->phases[seq].callbacks; + state->phases[seq].callbacks = bscb; return 0; } @@ -433,7 +475,64 @@ void hardwaremain(int boot_complete) /* FIXME: Is there a better way to handle this? */ init_timer(); - bs_walk_state_machine(BS_PRE_DEVICE); + bs_walk_state_machine(); + die("Boot state machine failure.\n"); } + +int boot_state_block(boot_state_t state, boot_state_sequence_t seq) +{ + struct boot_phase *bp; + + /* Blocking a previously ran state is not appropriate. */ + if (current_phase.state_id > state || + (current_phase.state_id == state && current_phase.seq > seq) ) { + printk(BIOS_WARNING, + "BS: Completed state (%d, %d) block attempted.\n", + state, seq); + return -1; + } + + bp = &boot_states[state].phases[seq]; + bp->blockers++; + + return 0; +} + +int boot_state_unblock(boot_state_t state, boot_state_sequence_t seq) +{ + struct boot_phase *bp; + + /* Blocking a previously ran state is not appropriate. */ + if (current_phase.state_id > state || + (current_phase.state_id == state && current_phase.seq > seq) ) { + printk(BIOS_WARNING, + "BS: Completed state (%d, %d) unblock attempted.\n", + state, seq); + return -1; + } + + bp = &boot_states[state].phases[seq]; + + if (bp->blockers == 0) { + printk(BIOS_WARNING, + "BS: Unblock attempted on non-blocked state (%d, %d).\n", + state, seq); + return -1; + } + + bp->blockers--; + + return 0; +} + +void boot_state_current_block(void) +{ + boot_state_block(current_phase.state_id, current_phase.seq); +} + +void boot_state_current_unblock(void) +{ + boot_state_unblock(current_phase.state_id, current_phase.seq); +}

1 0

Patch set updated for coreboot: 9afc7fe boot state: remove drain timers option
by Aaron Durbin 07 May '13

07 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3205 -gerrit commit 9afc7fec4044c544125352e4fb69955ec2c1a5bd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon May 6 10:52:24 2013 -0500 boot state: remove drain timers option Internally there were states that had an attribute to indicate that the timers needed to be drained. Now that there is a way to block state transitions rely on this ability instead of draining timers. The timers will drain themselves when a state is blocked. Change-Id: I59be9a71b2fd5a17310854d2f91c2a8957aafc28 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/hardwaremain.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 39aae6d..13aa512 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -87,13 +87,12 @@ struct boot_state { boot_state_t (*run_state)(void *arg); void *arg; int complete : 1; - int timers_drain : 1; #if CONFIG_HAVE_MONOTONIC_TIMER struct boot_state_times times; #endif }; -#define BS_INIT(state_, run_func_, drain_timers_) \ +#define BS_INIT(state_, run_func_) \ { \ .name = #state_, \ .id = state_, \ @@ -101,12 +100,9 @@ struct boot_state { .run_state = run_func_, \ .arg = NULL, \ .complete = 0, \ - .timers_drain = drain_timers_, \ } #define BS_INIT_ENTRY(state_, run_func_) \ - [state_] = BS_INIT(state_, run_func_, 0) -#define BS_INIT_ENTRY_DRAIN_TIMERS(state_, run_func_) \ - [state_] = BS_INIT(state_, run_func_, 1) + [state_] = BS_INIT(state_, run_func_) static struct boot_state boot_states[] = { BS_INIT_ENTRY(BS_PRE_DEVICE, bs_pre_device), @@ -117,10 +113,10 @@ static struct boot_state boot_states[] = { BS_INIT_ENTRY(BS_DEV_INIT, bs_dev_init), BS_INIT_ENTRY(BS_POST_DEVICE, bs_post_device), BS_INIT_ENTRY(BS_OS_RESUME_CHECK, bs_os_resume_check), - BS_INIT_ENTRY_DRAIN_TIMERS(BS_OS_RESUME, bs_os_resume), - BS_INIT_ENTRY_DRAIN_TIMERS(BS_WRITE_TABLES, bs_write_tables), - BS_INIT_ENTRY_DRAIN_TIMERS(BS_PAYLOAD_LOAD, bs_payload_load), - BS_INIT_ENTRY_DRAIN_TIMERS(BS_PAYLOAD_BOOT, bs_payload_boot), + BS_INIT_ENTRY(BS_OS_RESUME, bs_os_resume), + BS_INIT_ENTRY(BS_WRITE_TABLES, bs_write_tables), + BS_INIT_ENTRY(BS_PAYLOAD_LOAD, bs_payload_load), + BS_INIT_ENTRY(BS_PAYLOAD_BOOT, bs_payload_boot), }; static boot_state_t bs_pre_device(void *arg) @@ -365,7 +361,7 @@ static void bs_walk_state_machine(void) printk(BS_DEBUG_LVL, "BS: Entering %s state.\n", state->name); - bs_run_timers(state->timers_drain); + bs_run_timers(0); bs_sample_time(state);

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Patch set updated for coreboot: ce986db haswell: use asmlinkage for assembly-called funcs
by Aaron Durbin 07 May '13

07 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3203 -gerrit commit ce986db233197f24f23be4c6310a1f088b74c7d1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 2 09:42:13 2013 -0500 haswell: use asmlinkage for assembly-called funcs When the haswell MP/SMM code was developed it was using a coreboot repository that did not contain the asmlinkage macro. Now that the asmlinkage macro exists use it. BUG=None BRANCH=None TEST=Built and booted. Change-Id: I662f1b16d1777263b96a427334fff8f98a407755 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell.h | 4 +++- src/cpu/intel/haswell/mp_init.c | 3 +-- src/cpu/intel/haswell/romstage.c | 2 +- src/cpu/intel/haswell/smmrelocate.c | 2 +- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index a1c6f39..8f4368f 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -22,6 +22,8 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H +#include <arch/cpu.h> + /* Haswell bus clock is fixed at 100MHz */ #define HASWELL_BCLK 100 @@ -148,7 +150,7 @@ void romstage_common(const struct romstage_params *params); * +32: MTTR mask 1 63:32 * ... */ -void * __attribute__((regparm(0))) romstage_main(unsigned long bist); +void * asmlinkage romstage_main(unsigned long bist); /* romstage_after_car() is the C function called after cache-as-ram has * been torn down. It is responsible for loading the ramstage. */ void romstage_after_car(void); diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index ddcff6c..deba629 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -150,8 +150,7 @@ static void cleanup_rom_caching(void) /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ -static void __attribute__((cdecl)) -ap_init(unsigned int cpu, void *microcode_ptr) +static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) { struct cpu_info *info; diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index ff57584..077e409 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -162,7 +162,7 @@ static void *setup_romstage_stack_after_car(void) return slot; } -void * __attribute__((regparm(0))) romstage_main(unsigned long bist) +void * asmlinkage romstage_main(unsigned long bist) { int i; void *romstage_stack_after_car; diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index a8ab841..6caeafa 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -164,7 +164,7 @@ static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) /* The relocation work is actually performed in SMM context, but the code * resides in the ramstage module. This occurs by trampolining from the default * SMRAM entry point to here. */ -static void __attribute__((cdecl)) +static void asmlinkage cpu_smm_do_relocation(void *arg, int cpu, const struct smm_runtime *runtime) { msr_t mtrr_cap;

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New patch to review for coreboot: 8cc9ce3 exynos5: select HAVE_MONOTONIC_TIMER
by David Hendricks 07 May '13

07 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3210 -gerrit commit 8cc9ce33b3029a4926ca0e73954424d2d7b1e857 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon May 6 16:12:20 2013 -0700 exynos5: select HAVE_MONOTONIC_TIMER We have the monotonic timer implemented on exynos now, and this also enables helpful bootstage prints with timing info. Change-Id: I3baa4c9d70d4b4d059abd5e05eddcabd5258dbfd Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index 92b6460..9e2ec4c 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -1,5 +1,6 @@ config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 + select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select DEFAULT_EARLY_CONSOLE bool

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New patch to review for coreboot: 525f370 asrock/e350m1: reduce default stack size
by Stefan Reinauer 07 May '13

07 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3209 -gerrit commit 525f37009a011d9ff9db1c1b2232c27851a71426 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 6 16:16:03 2013 -0700 asrock/e350m1: reduce default stack size The stack used on the asrock e350m1 is significantly less than what we currently set (64k per core). In fact, we use about half of the default stack size (4k) on core 0 and even less on non BSP cores: CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes Change-Id: Ibdb2102c86094fce3787e3b5a162ca8423de205c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/asrock/e350m1/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index a308850..4c05037 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -84,10 +84,6 @@ config HEAP_SIZE hex default 0xc0000 -config STACK_SIZE - hex - default 0x10000 - config RAMBASE hex default 0x200000

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coreboot-gerrit May 2013