coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ce9b57e Intel Lynx Point: LPC: Unify I/O APIC setup
by Paul Menzel 07 May '13

07 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3182 -gerrit commit ce9b57e798dbb8c9434a775957700c2ddeebaf5f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:17:02 2013 +0200 Intel Lynx Point: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/lpc.c | 48 +++++++++++++---------------------- src/southbridge/intel/lynxpoint/pch.h | 1 + 2 files changed, 18 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 40e0468..eb46c95 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -43,43 +43,29 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void pch_enable_ioapic(struct device *dev) { - int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); + /* Enable ACPI I/O range decode */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) @@ -547,7 +533,7 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7246739..44182e3 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -237,6 +237,7 @@ unsigned get_gpios(const int *gpio_num_array); #define PMBASE 0x40 #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */

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Patch merged into coreboot/master: 703aa97 x86: harden tsc udelay() function
by gerrit＠coreboot.org 07 May '13

07 May '13

the following patch was just integrated into master: commit 703aa978aa6db915fbc7fa42e5ca79cf31f57505 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:55:14 2013 -0500 x86: harden tsc udelay() function Since the TSC udelay() function can be used in SMM that means the TSC can count up to whatever value. The current loop was not handling TSC rollover properly. In most cases this should not matter as the TSC typically starts ticking at value 0, and it would take a very long time to roll it over. However, it is my understanding that this behavior is not guaranteed. Theoretically the TSC could start or be be written to with a large value that would cause the rollover. Change-Id: I2f11a5bc4f27d5543e74f8224811fa91e4a55484 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3171 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Tue May 7 22:25:15 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue May 7 20:02:01 2013, giving +2 See http://review.coreboot.org/3171 for details. -gerrit

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Patch merged into coreboot/master: ddddf15 Intel 82801Gx: LPC: Unify I/O APIC setup
by gerrit＠coreboot.org 07 May '13

07 May '13

the following patch was just integrated into master: commit ddddf15ca359e932ed2e61e9a6dcec77ed2d4411 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:40:23 2013 +0200 Intel 82801Gx: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. As commented by Aaron Durbin, a separate `i82801gx_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3181 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Build-Tested: build bot (Jenkins) at Tue May 7 19:56:29 2013, giving +1 Reviewed-By: Aaron Durbin <adurbin(a)google.com> at Tue May 7 20:02:31 2013, giving +2 See http://review.coreboot.org/3181 for details. -gerrit

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Patch merged into coreboot/master: 1b3e176 x86 I/O APIC: Dump I/O APIC regs in `ioapic.c`
by gerrit＠coreboot.org 07 May '13

07 May '13

the following patch was just integrated into master: commit 1b3e176468213747188c8979a505a4dd8b83f0bd Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:49:41 2013 +0200 x86 I/O APIC: Dump I/O APIC regs in `ioapic.c` Some southbridges have code in their `lpc.c` files to dump the I/O APIC registers. printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); for (i=0; i<3; i++) { *ioapic_index = i; printk(BIOS_SPEW, " reg 0x%04x:", i); reg32 = *ioapic_data; printk(BIOS_SPEW, " 0x%08x\n", reg32); } Add similar code to `src/arch/x86/lib/ioapic.c` so all boards using the function `set_ioapic_id()` get the debug feature and the other boards can be more easily adapted in follow-up patches. Change-Id: Ic59c4c2213ed97bdf3798b3dc6e7cecc30e135d8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3184 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue May 7 20:34:54 2013, giving +1 Reviewed-By: Aaron Durbin <adurbin(a)google.com> at Tue May 7 20:02:15 2013, giving +2 See http://review.coreboot.org/3184 for details. -gerrit

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Patch merged into coreboot/master: ac75bc6 x86 I/O APIC: Make functions `io_apic_{read, write}()` public
by gerrit＠coreboot.org 07 May '13

07 May '13

the following patch was just integrated into master: commit ac75bc682b2c546ea01d6ad254df7b1a48a9f68f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:34:43 2013 +0200 x86 I/O APIC: Make functions `io_apic_{read,write}()` public Some LPC initialiation can save some lines of code when being able to use the functions `io_apic_read()` and `io_apic_write()`. As these two functions are now public, remove them from the generic driver as otherwise we get a build errors like the following. […] Building roda/rk9; i386: ok, using i386-elf-gcc Using payload /srv/jenkins/payloads/seabios/bios.bin.elf Creating config file... (blobs, ccache) ok; Compiling image on 4 cpus in parallel .. FAILED after 12s! Log excerpt: coreboot-builds/roda_rk9/arch/x86/lib/ramstage.o: In function `io_apic_write': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/arch/x86/lib/ioapic.c:32: multiple definition of `io_apic_write' coreboot-builds/roda_rk9/drivers/generic/ioapic/ramstage.o:/srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/drivers/generic/ioapic/ioapic.c:22: first defined here collect2: error: ld returned 1 exit status make: *** [coreboot-builds/roda_rk9/generated/coreboot_ram.o] Error 1 make: *** Waiting for unfinished jobs.... […] Change-Id: Id600007573ff011576967339cc66e6c883a2ed5a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3180 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Build-Tested: build bot (Jenkins) at Sun May 5 02:36:09 2013, giving +1 Reviewed-By: Aaron Durbin <adurbin(a)google.com> at Tue May 7 20:01:50 2013, giving +2 See http://review.coreboot.org/3180 for details. -gerrit

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Patch set updated for coreboot: e3d60ab src/cpu/amd/agesa/Kconfig: Use tabs instead of spaces for alignment
by Stefan Reinauer 07 May '13

07 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3173 -gerrit commit e3d60ab6af92fce750eec94e2d159b46e3a0484b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu May 2 10:34:49 2013 +0200 src/cpu/amd/agesa/Kconfig: Use tabs instead of spaces for alignment Some entries still used spaces while others used tabulators[1]. Convert spaces to tabs to uniformly use tabs. ---------------------- 8< -------------- 8< ----------------------------- For all of the Kconfig* configuration files throughout the source tree, the indentation is somewhat different. Lines under a "config" definition are indented with one tab, while help text is indented an additional two spaces. [2] ---------------------- 8< -------------- 8< ----------------------------- [1] http://en.wikipedia.org/wiki/File:HollerithMachine.CHM.jpg [2] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documen… Change-Id: Iee80ad4a90e95b925afbb0c6adc563fa3a6503cf Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/agesa/Kconfig | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 5e99c7b..c660470 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -18,13 +18,13 @@ # config CPU_AMD_AGESA - bool - default y if CPU_AMD_AGESA_FAMILY10 - default y if CPU_AMD_AGESA_FAMILY12 - default y if CPU_AMD_AGESA_FAMILY14 - default y if CPU_AMD_AGESA_FAMILY15 - default y if CPU_AMD_AGESA_FAMILY15_TN - default n + bool + default y if CPU_AMD_AGESA_FAMILY10 + default y if CPU_AMD_AGESA_FAMILY12 + default y if CPU_AMD_AGESA_FAMILY14 + default y if CPU_AMD_AGESA_FAMILY15 + default y if CPU_AMD_AGESA_FAMILY15_TN + default n select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER

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New patch to review for coreboot: 46efb42 Drop prototype guarding for romcc
by Stefan Reinauer 07 May '13

07 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3216 -gerrit commit 46efb42c33dc977789bd1520f00d898c626405ea Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue May 7 20:35:29 2013 +0200 Drop prototype guarding for romcc 11a7db3b570eb07759a7f4b5d8397be87518388d made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/cpu.h | 3 --- src/cpu/intel/haswell/haswell.h | 4 ---- src/cpu/intel/model_206ax/model_206ax.h | 2 -- src/include/console/ne2k.h | 6 ++---- src/include/cpu/amd/gx2def.h | 2 +- src/include/cpu/amd/lxdef.h | 2 +- src/include/cpu/intel/speedstep.h | 2 -- src/include/cpu/x86/lapic.h | 2 -- src/include/delay.h | 4 ---- src/include/ehci.h | 2 -- src/include/ip_checksum.h | 3 --- src/include/lib.h | 2 -- src/include/pc80/i8254.h | 2 -- src/include/pc80/mc146818rtc.h | 2 -- src/include/reset.h | 4 ---- src/include/uart.h | 2 +- src/include/uart8250.h | 3 --- src/include/usbdebug.h | 2 -- src/northbridge/intel/e7501/raminit.h | 2 -- src/northbridge/intel/i3100/raminit.h | 2 -- src/southbridge/amd/cs5535/cs5535.h | 2 +- src/southbridge/amd/cs5536/cs5536.h | 2 +- src/southbridge/intel/bd82x6x/pch.h | 2 +- src/southbridge/intel/i82371eb/i82371eb.h | 13 +++---------- src/southbridge/intel/i82801ax/i82801ax.h | 4 +--- src/southbridge/intel/i82801bx/i82801bx.h | 2 +- src/southbridge/intel/i82801dx/i82801dx.h | 2 +- src/southbridge/intel/i82801gx/i82801gx.h | 2 +- src/southbridge/intel/lynxpoint/pch.h | 3 +-- src/southbridge/nvidia/mcp55/mcp55.h | 2 -- src/southbridge/sis/sis966/sis966.h | 2 -- src/southbridge/via/vt8237r/vt8237r.h | 2 -- src/superio/ite/it8712f/it8712f.h | 3 --- src/superio/ite/it8716f/it8716f.h | 2 +- src/superio/ite/it8718f/it8718f.h | 2 +- src/superio/ite/it8721f/it8721f.h | 2 +- src/superio/ite/it8772f/it8772f.h | 3 --- src/superio/nsc/pc87417/pc87417.h | 2 +- src/superio/winbond/w83627ehg/w83627ehg.h | 2 +- src/superio/winbond/w83627hf/w83627hf.h | 2 +- src/superio/winbond/w83697hf/w83697hf.h | 3 --- 41 files changed, 22 insertions(+), 90 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index a3555d8..bc85bca 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -140,7 +140,6 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff -#if !defined(__ROMCC__) #if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> @@ -209,6 +208,4 @@ static void inline get_fms(struct cpuinfo_x86 *c, uint32_t tfms) #define asmlinkage __attribute__((regparm(0))) -#endif - #endif /* ARCH_CPU_H */ diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8f4368f..1171bc0 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -122,8 +122,6 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif -#ifndef __ROMCC__ - #if defined(__PRE_RAM__) struct pei_data; struct rcba_config_instruction; @@ -194,5 +192,3 @@ struct ramstage_cache { } __attribute__((packed)); #endif - -#endif diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index d440c70..1773cc8 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -97,7 +97,6 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -#ifndef __ROMCC__ #ifdef __SMM__ /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); @@ -106,6 +105,5 @@ void intel_model_206ax_finalize_smm(void); void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); #endif -#endif #endif diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index 630252b..62424f1 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -1,5 +1,3 @@ -#ifndef _NE2K_H__ -#define _NE2K_H__ /* * This file is part of the coreboot project. * @@ -19,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __ROMCC__ +#ifndef _NE2K_H__ +#define _NE2K_H__ void ne2k_append_data(unsigned char *d, int len, unsigned int base); int ne2k_init(unsigned int eth_nic_base); void ne2k_transmit(unsigned int eth_nic_base); -#endif #endif /* _NE2K_H */ diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index c0467be..ee55c2f 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -511,7 +511,7 @@ #define PMLogic_BASE (0x9D00) -#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(void); void SystemPreInit(void); diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 632bfe2..4eee156 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -630,7 +630,7 @@ #define DELAY_UPPER_DISABLE_CLK135 (1 << 23) #define DELAY_LOWER_STATUS_MASK 0x7C0 -#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated); void SystemPreInit(void); diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index f4c4d72..8bfae60 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -105,9 +105,7 @@ typedef struct { int num_states; } sst_table_t; -#ifndef __ROMCC__ void speedstep_gen_pstates(sst_table_t *); -#endif #define SPEEDSTEP_MAX_POWER_YONAH 31000 #define SPEEDSTEP_MIN_POWER_YONAH 13100 diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 54b2f54..d4f3232 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -51,7 +51,6 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) return lapic_read(LAPIC_ID) >> 24; } -#ifndef __ROMCC__ #if !CONFIG_AP_IN_SIPI_WAIT /* If we need to go back to sipi wait, we use the long non-inlined version of * this function in lapic_cpu_init.c @@ -155,6 +154,5 @@ int start_cpu(struct device *cpu); #endif /* !__PRE_RAM__ */ int boot_cpu(void); -#endif #endif /* CPU_X86_LAPIC_H */ diff --git a/src/include/delay.h b/src/include/delay.h index 0333879..676579b 100644 --- a/src/include/delay.h +++ b/src/include/delay.h @@ -1,8 +1,6 @@ #ifndef DELAY_H #define DELAY_H -#if !defined( __ROMCC__) - #if CONFIG_HAVE_INIT_TIMER void init_timer(void); #else @@ -12,6 +10,4 @@ void init_timer(void); void udelay(unsigned usecs); void mdelay(unsigned msecs); void delay(unsigned secs); - -#endif #endif /* DELAY_H */ diff --git a/src/include/ehci.h b/src/include/ehci.h index 29347f9..7ec9810 100644 --- a/src/include/ehci.h +++ b/src/include/ehci.h @@ -25,7 +25,6 @@ #define EHCI_BAR_INDEX 0x10 -#ifndef __ROMCC__ /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ /* Section 2.2 Host Controller Capability Registers */ @@ -201,4 +200,3 @@ struct ehci_dbg_port { #define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) } __attribute__ ((packed)); #endif -#endif diff --git a/src/include/ip_checksum.h b/src/include/ip_checksum.h index de26fa0..a1e0ffa 100644 --- a/src/include/ip_checksum.h +++ b/src/include/ip_checksum.h @@ -1,8 +1,5 @@ #ifndef IP_CHECKSUM_H #define IP_CHECKSUM_H - -#ifndef __ROMCC__ unsigned long compute_ip_checksum(void *addr, unsigned long length); unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new); -#endif #endif /* IP_CHECKSUM_H */ diff --git a/src/include/lib.h b/src/include/lib.h index 40c76f2..cb540a7 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -22,7 +22,6 @@ #ifndef __LIB_H__ #define __LIB_H__ #include <stdint.h> -#ifndef __ROMCC__ /* romcc doesn't support prototypes. */ #ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */ /* Defined in src/lib/clog2.c */ @@ -53,5 +52,4 @@ void cache_as_ram_main(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #endif -#endif /* __ROMCC__ */ #endif /* __LIB_H__ */ diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index f8e2b48..f4f0dca 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -58,7 +58,5 @@ #define PPCB_SPKR 0x02 /* Bit 1 */ #define PPCB_T2GATE 0x01 /* Bit 0 */ -#ifndef __ROMCC__ void setup_i8254(void); #endif -#endif diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index ee1473b..29e0348 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -203,9 +203,7 @@ static inline int get_option(void *dest __attribute__((unused)), #define CMOS_POST_BANK_1_MAGIC 0x81 #define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) -#if !defined(__ROMCC__) void cmos_post_log(void); -#endif #endif /* CONFIG_CMOS_POST */ #endif /* PC80_MC146818RTC_H */ diff --git a/src/include/reset.h b/src/include/reset.h index 79bf6d5..9f117db 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -1,9 +1,6 @@ #ifndef RESET_H #define RESET_H -#if !defined( __ROMCC__ ) -/* ROMCC can't do function prototypes... */ - #if CONFIG_HAVE_HARD_RESET void hard_reset(void); #else @@ -12,4 +9,3 @@ void hard_reset(void); void soft_reset(void); #endif -#endif diff --git a/src/include/uart.h b/src/include/uart.h index 6b8d8e8..9601bfa 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -30,7 +30,7 @@ #include <uart8250.h> #endif -#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); diff --git a/src/include/uart8250.h b/src/include/uart8250.h index d1164c5..d42e822 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -114,7 +114,6 @@ /* Line Control Settings */ #define UART_LCS CONFIG_TTYS0_LCS -#ifndef __ROMCC__ #if CONFIG_CONSOLE_SERIAL8250 unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); @@ -145,8 +144,6 @@ void oxford_init(void); #endif #endif -#endif /* __ROMCC__ */ - #endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ #endif /* UART8250_H */ diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index 8caf361..c3b3437 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -34,7 +34,6 @@ struct ehci_debug_info { u8 bufidx; }; -#ifndef __ROMCC__ void enable_usbdebug(unsigned int port); int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size); int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size); @@ -47,4 +46,3 @@ void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data); void usbdebug_tx_flush(struct ehci_debug_info *info); int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info); #endif -#endif diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h index df0e929..05c3889 100644 --- a/src/northbridge/intel/e7501/raminit.h +++ b/src/northbridge/intel/e7501/raminit.h @@ -15,8 +15,6 @@ struct mem_controller { uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; }; -#ifndef __ROMCC__ void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/i3100/raminit.h b/src/northbridge/intel/i3100/raminit.h index 03e1458..ea6c60f 100644 --- a/src/northbridge/intel/i3100/raminit.h +++ b/src/northbridge/intel/i3100/raminit.h @@ -30,8 +30,6 @@ struct mem_controller { u16 channel1[DIMM_SOCKETS]; }; -#ifndef __ROMCC__ void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif #endif diff --git a/src/southbridge/amd/cs5535/cs5535.h b/src/southbridge/amd/cs5535/cs5535.h index 0db7c17..0b43563 100644 --- a/src/southbridge/amd/cs5535/cs5535.h +++ b/src/southbridge/amd/cs5535/cs5535.h @@ -115,7 +115,7 @@ /* Flash Memory Mask values */ #define FLASH_MEM_4K 0xFFFFF000 -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cs5535_disable_internal_uart(void); #else diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index 84738a2..c193d9d 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -442,7 +442,7 @@ #define FLASH_IO_128B 0x0000FF80 #define FLASH_IO_256B 0x0000FF00 -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cs5536_setup_onchipuart(int uart); void cs5536_disable_internal_uart(void); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7f64571..3904866 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -56,7 +56,7 @@ void intel_pch_finalize_smm(void); #endif -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #if !defined(__SMM__) #include "chip.h" diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 76d5fc7..e6062c6 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,26 +21,19 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) #if !defined(__PRE_RAM__) -#if !defined(__ACPI__) /* dsdt include */ - #include <arch/io.h> #include <device/device.h> #include "chip.h" - void i82371eb_enable(device_t dev); void i82371eb_hard_reset(void); - -#endif -#endif -#endif - -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#else void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); void enable_pm(void); #endif +#endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the * 'reg' variable, otherwise it clears those bits. diff --git a/src/southbridge/intel/i82801ax/i82801ax.h b/src/southbridge/intel/i82801ax/i82801ax.h index ed15bba..f459f2f 100644 --- a/src/southbridge/intel/i82801ax/i82801ax.h +++ b/src/southbridge/intel/i82801ax/i82801ax.h @@ -24,9 +24,7 @@ #if !defined(__PRE_RAM__) #include "chip.h" void i82801ax_enable(device_t dev); -#endif - -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#else void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); #endif diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h index 202b41c..b2ee79c 100644 --- a/src/southbridge/intel/i82801bx/i82801bx.h +++ b/src/southbridge/intel/i82801bx/i82801bx.h @@ -26,7 +26,7 @@ extern void i82801bx_enable(device_t dev); #endif -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); #endif diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index dba5bd6..c7d7e77 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -31,7 +31,7 @@ #ifndef I82801DX_H #define I82801DX_H -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801dx_enable(device_t dev); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index b5df5d9..1064dde 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -37,7 +37,7 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7246739..21933b4 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -21,7 +21,6 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H - /* * Lynx Point PCH PCI Devices: * @@ -125,7 +124,7 @@ struct rcba_config_instruction u32 or_value; }; -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); int pch_silicon_type(void); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 5454d79..4fb3391 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -33,9 +33,7 @@ void mcp55_enable(device_t dev); extern struct pci_operations mcp55_pci_ops; #else -#if !defined(__ROMCC__) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif -#endif #endif diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h index 6c1e7e2..6085ab5 100644 --- a/src/southbridge/sis/sis966/sis966.h +++ b/src/southbridge/sis/sis966/sis966.h @@ -35,8 +35,6 @@ #define DEBUG_USB 0 #define DEBUG_USB2 0 -#if !defined(__ROMCC__) void sis966_enable(device_t dev); -#endif #endif /* SIS966_H */ diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index b43ce3c..3cca58d 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -145,7 +145,6 @@ __attribute__ ((packed)) #ifdef __PRE_RAM__ -#ifndef __ROMCC__ u8 smbus_read_byte(u8 dimm, u8 offset); void smbus_write_byte(u8 dimm, u8 offset, u8 data); void enable_smbus(void); @@ -155,7 +154,6 @@ void vt8237_sb_enable_fid_vid(void); void enable_rom_decode(void); void vt8237_early_spi_init(void); int vt8237_early_network_init(struct vt8237_network_rom *rom); -#endif #else void writeback(device_t dev, u16 where, u8 what); void dump_south(device_t dev); diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 0616c2a..5ec6188 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -35,11 +35,8 @@ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ -#ifndef __ROMCC__ void it8712f_kill_watchdog(void); void it8712f_enable_serial(device_t dev, u16 iobase); void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); #endif - -#endif diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index be9f720..6657db4 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -41,7 +41,7 @@ void init_ec(u16 base); #endif -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void it8716f_disable_dev(device_t dev); void it8716f_enable_dev(device_t dev, u16 iobase); void it8716f_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 4da5af5..527d1c2 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -33,7 +33,7 @@ #define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void it8718f_24mhz_clkin(void); void it8718f_disable_reboot(void); void it8718f_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h index cca404a..25300e6 100644 --- a/src/superio/ite/it8721f/it8721f.h +++ b/src/superio/ite/it8721f/it8721f.h @@ -32,7 +32,7 @@ #define IT8721F_GPIO 0x07 /* GPIO */ #define IT8721F_IR 0x0a /* Consumer IR */ -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void it8721f_24mhz_clkin(void); void it8721f_disable_reboot(void); void it8721f_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 343d9b3..f881d7a 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -105,7 +105,6 @@ #define GPIO_REG_ENABLE(x) (0xc0 + (x)) #define GPIO_REG_OUTPUT(x) (0xc8 + (x)) -#ifndef __ROMCC__ u8 it8772f_sio_read(u8 index); void it8772f_sio_write(u8 index, u8 value); void it8772f_enable_serial(device_t dev, u16 iobase); @@ -116,5 +115,3 @@ void it8772f_ac_resume_southbridge(void); void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup, u8 output, u8 enable); #endif - -#endif diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index 7208c8e..73c1fbc 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -114,7 +114,7 @@ #define PC87417_XSCNF 0x15 #define PC87417_XWBCNF 0x16 -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void pc87417_enable_serial(device_t dev, u16 iobase); void pc87417_enable_dev(device_t dev); #endif diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index deab7ce..c982603 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,7 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void w83627ehg_enable_dev(device_t dev, u16 iobase); void w83627ehg_disable_dev(device_t dev); void w83627ehg_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index 423ba8f..468cb55 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -113,7 +113,7 @@ #define W83627HF_XSCNF 0x15 #define W83627HF_XWBCNF 0x16 -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void w83627hf_disable_dev(device_t dev); void w83627hf_enable_dev(device_t dev, u16 iobase); void w83627hf_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 741d5b2..7e353e2 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -32,8 +32,5 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ -#ifndef __ROMCC__ void w83697hf_set_clksel_48(device_t); #endif - -#endif

1 0

Patch merged into coreboot/master: 15c671e boot state: remove drain timers option
by gerrit＠coreboot.org 07 May '13

07 May '13

the following patch was just integrated into master: commit 15c671efb5e6834824569a812dcec7bb5d5ce384 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon May 6 10:52:24 2013 -0500 boot state: remove drain timers option Internally there were states that had an attribute to indicate that the timers needed to be drained. Now that there is a way to block state transitions rely on this ability instead of draining timers. The timers will drain themselves when a state is blocked. Change-Id: I59be9a71b2fd5a17310854d2f91c2a8957aafc28 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3205 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Tue May 7 09:47:00 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue May 7 20:08:03 2013, giving +2 See http://review.coreboot.org/3205 for details. -gerrit

1 0

Patch merged into coreboot/master: 0748d30 boot state: add ability to block state transitions
by gerrit＠coreboot.org 07 May '13

07 May '13

the following patch was just integrated into master: commit 0748d305545440ae89034542ea761d39b9aab526 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon May 6 10:50:19 2013 -0500 boot state: add ability to block state transitions In order to properly sequence the boot state machine it's important that outside code can block the transition from one state to the next. When timers are not involved there's no reason for any of the existing code to block a state transition. However, if there is a timer callback that needs to complete by a certain point in the boot sequence it is necessary to place a block for the given state. To that end, 4 new functions are added to provide the API for blocking a state. 1. boot_state_block(boot_state_t state, boot_state_sequence_t seq); 2. boot_state_unblock(boot_state_t state, boot_state_sequence_t seq); 3. boot_state_current_block(void); 4. boot_state_current_unblock(void); Change-Id: Ieb37050ff652fd85a6b1e0e2f81a1a2807bab8e0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3204 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Tue May 7 10:23:05 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue May 7 20:07:42 2013, giving +2 See http://review.coreboot.org/3204 for details. -gerrit

1 0

New patch to review for coreboot: a050af7 x86: use asmlinkage macro for smm_handler_t
by Aaron Durbin 07 May '13

07 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3215 -gerrit commit a050af7f446281f87a387040cac6e6b0e336de2f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 7 12:58:12 2013 -0500 x86: use asmlinkage macro for smm_handler_t The smm_handler_t type was added before the introduction of the asmlinkage macro. Now that asmlinkage is available use it. Change-Id: I85ec72cf958bf4b77513a85faf6d300c781af603 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cpu/x86/smm.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 62494a9..df7e3de 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -33,6 +33,7 @@ #define SMM_ENTRY_OFFSET 0x8000 #define SMM_SAVE_STATE_BEGIN(x) (SMM_ENTRY_OFFSET + (x)) +#include <arch/cpu.h> #include <types.h> typedef struct { u16 es_selector; @@ -429,8 +430,8 @@ struct smm_runtime { u8 apic_id_to_cpu[CONFIG_MAX_CPUS]; } __attribute__ ((packed)); -typedef void __attribute__((cdecl)) (*smm_handler_t)(void *arg, int cpu, - const struct smm_runtime *runtime); +typedef void asmlinkage (*smm_handler_t)(void *arg, int cpu, + const struct smm_runtime *runtime); #ifdef __SMM__ /* SMM Runtime helpers. */

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coreboot-gerrit May 2013