coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 0ec8b23 haswell: Fix VGA option rom INT15 handler
by Stefan Reinauer 09 May '13

09 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3230 -gerrit commit 0ec8b238686e81d189dbbf18df2cfd123b803455 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Apr 23 08:39:19 2013 -0700 haswell: Fix VGA option rom INT15 handler The format of this function changed but was not updated in all mainboards. This fixes BaskingRidge and WTM2. The int15 handler no longer takes a regs structure as an argument and instead uses global variables. The yabel interface is now similar enough that we can drop the duplicate handler. Change-Id: Ia717ae14f99cee6d83ccdb1e26b9d7defe1638c4 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48896 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/intel/baskingridge/mainboard.c | 138 +++++---------------------- src/mainboard/intel/wtm2/mainboard.c | 136 +++++--------------------- 2 files changed, 51 insertions(+), 223 deletions(-) diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index c7b0ee0..d49ba45 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,7 +25,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> @@ -42,15 +42,15 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static int int15_handler(struct eregs *regs) +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +static int int15_handler(void) { int res=-1; - printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", - __func__, regs->eax & 0xffff); + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); - switch(regs->eax & 0xffff) { + switch (X86_AX) { case 0x5f34: /* * Set Panel Fitting Hook: @@ -59,10 +59,8 @@ static int int15_handler(struct eregs *regs) * bit 0 = Centering (do not set with bit1 or bit2) * 0 = video bios default */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffffff00; - regs->ecx |= 0x01; + X86_AX = 0x005f; + X86_CX = 0x0001; res = 0; break; case 0x5f35: @@ -77,10 +75,8 @@ static int int15_handler(struct eregs *regs) * bit 6 = EFP2 * * bit 7 = LFP2 */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 0x5f51: @@ -91,129 +87,47 @@ static int int15_handler(struct eregs *regs) * 02h = SVDO-LVDS, LFP driven by SVDO decoder * 03h = eDP, LFP Driven by Int-DisplayPort encoder */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0003; + X86_AX = 0x005f; + X86_CX = 0x0003; res = 0; break; case 0x5f70: - switch ((regs->ecx >> 8) & 0xff) { + switch ((X86_CX >> 8) & 0xff) { case 0: /* Get Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 1: /* Set Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 2: /* Get SG/Non-SG mode */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; default: /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - ((regs->ecx >> 8) & 0xff)); + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); return 0; } break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - regs->eax & 0xffff); + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } #endif -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL -static int int15_handler(void) -{ - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); - - switch (M.x86.R_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x0001; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV (eDP) * - * bit 2 = EFP * - * bit 3 = LFP - * bit 4 = CRT2 - * bit 5 = TV2 (eDP) * - * bit 6 = EFP2 * - * bit 7 = LFP2 - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x0000; - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 3; - break; - case 0x5f70: - /* Unknown */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", - M.x86.R_AX); - return 0; - } - - /* Interrupt handled */ - return 1; -} -#endif - -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static void int15_install(void) -{ -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL - typedef int (* yabel_handleIntFunc)(void); - extern yabel_handleIntFunc yabel_intFuncArray[256]; - yabel_intFuncArray[0x15] = int15_handler; -#endif -#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif -} -#endif - /* Audio Setup */ extern const u32 * cim_verb_data; @@ -230,9 +144,9 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ - int15_install(); + mainboard_interrupt_handlers(0x15, &int15_handler); #endif verb_setup(); } diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index f5b0054..d49ba45 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -25,7 +25,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> @@ -42,15 +42,15 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static int int15_handler(struct eregs *regs) +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +static int int15_handler(void) { int res=-1; - printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", - __func__, regs->eax & 0xffff); + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); - switch(regs->eax & 0xffff) { + switch (X86_AX) { case 0x5f34: /* * Set Panel Fitting Hook: @@ -59,10 +59,8 @@ static int int15_handler(struct eregs *regs) * bit 0 = Centering (do not set with bit1 or bit2) * 0 = video bios default */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffffff00; - regs->ecx |= 0x01; + X86_AX = 0x005f; + X86_CX = 0x0001; res = 0; break; case 0x5f35: @@ -77,10 +75,8 @@ static int int15_handler(struct eregs *regs) * bit 6 = EFP2 * * bit 7 = LFP2 */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 0x5f51: @@ -91,129 +87,47 @@ static int int15_handler(struct eregs *regs) * 02h = SVDO-LVDS, LFP driven by SVDO decoder * 03h = eDP, LFP Driven by Int-DisplayPort encoder */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0003; + X86_AX = 0x005f; + X86_CX = 0x0003; res = 0; break; case 0x5f70: - switch ((regs->ecx >> 8) & 0xff) { + switch ((X86_CX >> 8) & 0xff) { case 0: /* Get Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 1: /* Set Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 2: /* Get SG/Non-SG mode */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; default: /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - ((regs->ecx >> 8) & 0xff)); + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); return 0; } break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - regs->eax & 0xffff); + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } #endif -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL -static int int15_handler(void) -{ - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); - - switch (M.x86.R_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x0001; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV (eDP) * - * bit 2 = EFP * - * bit 3 = LFP - * bit 4 = CRT2 - * bit 5 = TV2 (eDP) * - * bit 6 = EFP2 * - * bit 7 = LFP2 - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x0000; - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 3; - break; - case 0x5f70: - /* Unknown */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", - M.x86.R_AX); - return 0; - } - - /* Interrupt handled */ - return 1; -} -#endif - -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static void int15_install(void) -{ -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL - typedef int (* yabel_handleIntFunc)(void); - extern yabel_handleIntFunc yabel_intFuncArray[256]; - yabel_intFuncArray[0x15] = int15_handler; -#endif -#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif -} -#endif - /* Audio Setup */ extern const u32 * cim_verb_data; @@ -230,9 +144,9 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ - int15_install(); + mainboard_interrupt_handlers(0x15, &int15_handler); #endif verb_setup(); }

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New patch to review for coreboot: 42266b8 PC Engines ALIX.1C: Add CMOS defaults.
by Denis Carikli 09 May '13

09 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3229 -gerrit commit 42266b8416b74ae3442d28242f9c88388e055fe8 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 23:35:18 2013 +0200 PC Engines ALIX.1C: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Disable baud_rate = 115200 power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0x7f nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Iba2701d4611cd2c2e5a2d76d41ffc23ed65574e8 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/pcengines/alix1c/Kconfig | 2 ++ src/mainboard/pcengines/alix1c/cmos.default | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 315b7ed..fab8710 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_DEFAULT_DISABLE + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/alix1c/cmos.default b/src/mainboard/pcengines/alix1c/cmos.default new file mode 100644 index 0000000..189c691 --- /dev/null +++ b/src/mainboard/pcengines/alix1c/cmos.default @@ -0,0 +1,11 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Disable +baud_rate=115200 +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0x7f

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New patch to review for coreboot: f2bd5dd Get rid of a number of __GNUC__ checks
by Stefan Reinauer 09 May '13

09 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3226 -gerrit commit f2bd5dd12e00647fc4cd0c1f8b2bcb1f3c52f8f7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 9 14:33:14 2013 -0700 Get rid of a number of __GNUC__ checks In the process of streamlining coreboot code and getting rid of unneeded ifdefs, drop a number of unneeded checks for the GNU C compiler. This also cleans up x86emu/types.h significantly by dropping all the duplicate types in there. Change-Id: I0bf289e149ed02e5170751c101adc335b849a410 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/device/oprom/include/x86emu/types.h | 47 ++----------------------------- src/include/cpu/amd/amdfam12.h | 6 ---- src/include/cpu/amd/multicore.h | 4 --- src/northbridge/amd/amdk8/incoherent_ht.c | 2 -- src/northbridge/intel/i3100/i3100.h | 2 -- src/southbridge/via/vt8237r/vt8237r.h | 10 +------ 6 files changed, 4 insertions(+), 67 deletions(-) diff --git a/src/device/oprom/include/x86emu/types.h b/src/device/oprom/include/x86emu/types.h index 5485eea..bb6dab44 100644 --- a/src/device/oprom/include/x86emu/types.h +++ b/src/device/oprom/include/x86emu/types.h @@ -36,54 +36,13 @@ * ****************************************************************************/ -/* $XFree86: xc/extras/x86emu/include/x86emu/types.h,v 1.4 2000/09/26 15:56:44 tsi Exp $ */ - #ifndef __X86EMU_TYPES_H #define __X86EMU_TYPES_H -//#ifndef IN_MODULE -//#include <sys/types.h> -//#endif - -/* - * The following kludge is an attempt to work around typedef conflicts with - * <sys/types.h>. - */ -#define u8 x86emuu8 -#define u16 x86emuu16 -#define u32 x86emuu32 -#define u64 x86emuu64 -#define s8 x86emus8 -#define s16 x86emus16 -#define s32 x86emus32 -#define s64 x86emus64 -#define uint x86emuuint -#define sint x86emusint - -/*---------------------- Macros and type definitions ----------------------*/ - -/* Currently only for Linux/32bit */ -#if defined(__GNUC__) && !defined(NO_LONG_LONG) -#define __HAS_LONG_LONG__ -#endif - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned int u32; -#ifdef __HAS_LONG_LONG__ -typedef unsigned long long u64; -#endif - -typedef signed char s8; -typedef signed short s16; -typedef signed int s32; -#ifdef __HAS_LONG_LONG__ -typedef signed long long s64; -#endif - -typedef unsigned int uint; -typedef signed int sint; +#include <stdint.h> +typedef unsigned int uint; +typedef signed int sint; typedef u16 X86EMU_pioAddr; #endif /* __X86EMU_TYPES_H */ diff --git a/src/include/cpu/amd/amdfam12.h b/src/include/cpu/amd/amdfam12.h index 9ad84bd..5252e89 100644 --- a/src/include/cpu/amd/amdfam12.h +++ b/src/include/cpu/amd/amdfam12.h @@ -33,12 +33,6 @@ #define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 -//#if defined(__GNUC__) -//// it can be used to get unitid and coreid it running only -//struct node_core_id get_node_core_id(u32 nb_cfg_54); -//struct node_core_id get_node_core_id_x(void); -//#endif - #if defined(__PRE_RAM__) void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h index e06725a..c871223 100644 --- a/src/include/cpu/amd/multicore.h +++ b/src/include/cpu/amd/multicore.h @@ -20,20 +20,16 @@ #ifndef CPU_AMD_QUADCORE_H #define CPU_AMD_QUADCORE_H -#if defined(__GNUC__) u32 read_nb_cfg_54(void); -#endif struct node_core_id { u32 nodeid; u32 coreid; }; -#if defined(__GNUC__) // it can be used to get unitid and coreid it running only struct node_core_id get_node_core_id(u32 nb_cfg_54); struct node_core_id get_node_core_id_x(void); -#endif #if !defined(__PRE_RAM__) struct device; diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index ee1945a..6cbe7dc 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -699,9 +699,7 @@ static int ht_setup_chains(uint8_t ht_c_num) } -#if defined (__GNUC__) static inline unsigned get_nodes(void); -#endif #if CONFIG_RAMINIT_SYSINFO static void ht_setup_chains_x(struct sys_info *sysinfo) diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h index 7305714..2d036bd 100644 --- a/src/northbridge/intel/i3100/i3100.h +++ b/src/northbridge/intel/i3100/i3100.h @@ -67,8 +67,6 @@ #define RCBA 0xF0 #define DEFAULT_RCBA 0xFEA00000 -#ifdef __GNUC__ int bios_reset_detected(void); -#endif #endif diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index 3cca58d..ee5cc82 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -28,11 +28,7 @@ #define VT8237R_SMBUS_IO_BASE 0x400 /* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */ #define VT8237R_ACPI_IRQ 0x9 -#if defined(__GNUC__) -#define VT8237S_SPI_MEM_BASE 0xfed02000ULL -#else #define VT8237S_SPI_MEM_BASE 0xfed02000UL -#endif /* PMBASE FIXME mostly taken from ich7 */ #define PM1_STS 0x00 @@ -129,11 +125,7 @@ struct vt8237_network_rom { u8 cfg_c; u8 cfg_d; u8 checksum; -} -#if defined(__GNUC__) -__attribute__ ((packed)) -#endif -; +} __attribute__ ((packed)); #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1

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New patch to review for coreboot: 228b1e2 romcc: support attribute((packed))
by Stefan Reinauer 09 May '13

09 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3225 -gerrit commit 228b1e2bf4fff87bb8a2adcd500d506866734526 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 9 14:06:04 2013 -0700 romcc: support attribute((packed)) right now this is just a fake option to get rid of ifdefs in coreboot's code. Change-Id: I59233f3c1d266b4e716a5921e9db298c7f96751d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/romcc/romcc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index d371506..0c7c7e1 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -3,8 +3,8 @@ #undef RELEASE_DATE #undef VERSION #define VERSION_MAJOR "0" -#define VERSION_MINOR "72" -#define RELEASE_DATE "10 February 2010" +#define VERSION_MINOR "73" +#define RELEASE_DATE "08 May 2013" #define VERSION VERSION_MAJOR "." VERSION_MINOR #include <stdarg.h> @@ -1085,6 +1085,7 @@ struct compile_state { struct hash_entry *i_return; struct hash_entry *i_noreturn; struct hash_entry *i_unused; + struct hash_entry *i_packed; /* Additional hash entries for predefined macros */ struct hash_entry *i_defined; struct hash_entry *i___VA_ARGS__; @@ -12756,6 +12757,9 @@ static unsigned int attrib(struct compile_state *state, unsigned int attributes) else if (ident == state->i_unused) { // attribute((unused)) does nothing (yet?) } + else if (ident == state->i_packed) { + // attribute((packed)) does nothing (yet?) + } else { error(state, 0, "Unknown attribute:%s", ident->name); } @@ -24994,6 +24998,7 @@ static void compile(const char *filename, state.i_always_inline = lookup(&state, "always_inline", 13); state.i_noreturn = lookup(&state, "noreturn", 8); state.i_unused = lookup(&state, "unused", 6); + state.i_packed = lookup(&state, "packed", 6); /* Process the command line macros */ process_cmdline_macros(&state);

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New patch to review for coreboot: bac20d7 Asus M4A785T-M: Add CMOS defaults.
by Denis Carikli 09 May '13

09 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3224 -gerrit commit bac20d736ae04b30a22b28bb564778a423a58a05 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 16:14:59 2013 +0200 Asus M4A785T-M: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Enable baud_rate = 115200 hw_scrubber = Enable interleave_chip_selects = Enable max_mem_clock = 400Mhz multi_core = Enable power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0xc slow_cpu = off nmi = Enable iommu = Enable nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide. nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Ifa09c7a468e3e0713b426763266ae633e67d8397 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/Kconfig | 1 + src/mainboard/asus/m4a785t-m/cmos.default | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 10f6838..6816d58 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/asus/m4a785t-m/cmos.default b/src/mainboard/asus/m4a785t-m/cmos.default new file mode 100644 index 0000000..da086de --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Enable +baud_rate=115200 +hw_scrubber=Enable +interleave_chip_selects=Enable +max_mem_clock=400Mhz +multi_core=Enable +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0xc +slow_cpu=off +nmi=Enable +iommu=Enable

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New patch to review for coreboot: 955af60 Kconfig: Simplify and repair the cmos.default handling.
by Denis Carikli 09 May '13

09 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3223 -gerrit commit 955af6063051cb36c2165a5fac8c7a74425f22f0 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 22:19:17 2013 +0200 Kconfig: Simplify and repair the cmos.default handling. Without that fix we have: make: *** No rule to make target `nvramtool', needed by `build/coreboot.pre1'. Stop. This commit was tested on the Asus M4A785T-M with the following commit: Asus M4A785T-M: Add CMOS defaults. Change-Id: I548005a58f430ed7b6da5249a24bbdcae440a1e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- Makefile.inc | 8 -------- src/drivers/pc80/Makefile.inc | 10 ++++++++-- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index da350d1..71acc87 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -142,14 +142,6 @@ $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h endef ####################################################################### -# Parse plaintext cmos defaults into binary format -# arg1: source file -# arg2: binary file name -cbfs-files-processor-nvramtool= \ - $(eval $(2): $(1) $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout | $(objutil)/nvramtool/nvramtool ; \ - printf " CREATE $(2) (from $(1))\n"; $(objutil)/nvramtool/nvramtool -y $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout -D $(2).tmp -p $(1) && mv $(2).tmp $(2)) - -####################################################################### # Link VSA binary to ELF-ish stage # arg1: source file # arg2: binary file name diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index 23e986a..a09ad43 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -9,11 +9,17 @@ romstage-$(CONFIG_TPM) += tpm.c romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c subdirs-y += vga -cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default -cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool +ifeq ($(CONFIG_HAVE_CMOS_DEFAULT),y) +cbfs-files-y += cmos.default +cmos.default-file = $(obj)/cmos.default.bin cmos.default-type = 0xaa +endif smm-y += mc146818rtc.c $(obj)/drivers/pc80/mc146818rtc.ramstage.o : $(obj)/build.h $(obj)/drivers/pc80/mc146818rtc.smm.o : $(obj)/build.h + +$(obj)/cmos.default.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout + @printf " OPTION $(subst $(obj)/,,$(@))\n" + $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -D $@ -p $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.default

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Patch set updated for coreboot: 6bc0762 Drop prototype guarding for romcc
by Stefan Reinauer 09 May '13

09 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3216 -gerrit commit 6bc0762b3571fbf05bd2fcc5b93e5b918ae9a803 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue May 7 20:35:29 2013 +0200 Drop prototype guarding for romcc Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/cpu.h | 14 ++++++-------- src/cpu/intel/haswell/haswell.h | 2 +- src/cpu/intel/model_206ax/model_206ax.h | 2 -- src/include/console/ne2k.h | 6 ++---- src/include/cpu/amd/gx2def.h | 2 +- src/include/cpu/amd/lxdef.h | 2 +- src/include/cpu/intel/speedstep.h | 2 -- src/include/cpu/x86/lapic.h | 2 -- src/include/delay.h | 4 ---- src/include/ehci.h | 2 -- src/include/ip_checksum.h | 3 --- src/include/lib.h | 4 ++-- src/include/pc80/i8254.h | 2 -- src/include/pc80/mc146818rtc.h | 2 -- src/include/reset.h | 4 ---- src/include/uart.h | 2 +- src/include/uart8250.h | 3 --- src/include/usbdebug.h | 2 -- src/northbridge/intel/e7501/raminit.h | 2 -- src/northbridge/intel/i3100/raminit.h | 2 -- src/southbridge/amd/cs5535/cs5535.h | 2 +- src/southbridge/amd/cs5536/cs5536.h | 2 +- src/southbridge/intel/bd82x6x/pch.h | 2 +- src/southbridge/intel/i82371eb/i82371eb.h | 13 +++---------- src/southbridge/intel/i82801ax/i82801ax.h | 4 +--- src/southbridge/intel/i82801bx/i82801bx.h | 2 +- src/southbridge/intel/i82801dx/i82801dx.h | 2 +- src/southbridge/intel/i82801gx/i82801gx.h | 2 +- src/southbridge/intel/lynxpoint/pch.h | 3 +-- src/southbridge/nvidia/mcp55/mcp55.h | 2 -- src/southbridge/sis/sis966/sis966.h | 2 -- src/southbridge/via/vt8237r/vt8237r.h | 2 -- src/superio/ite/it8712f/it8712f.h | 3 --- src/superio/ite/it8716f/it8716f.h | 2 +- src/superio/ite/it8718f/it8718f.h | 2 +- src/superio/ite/it8721f/it8721f.h | 2 +- src/superio/ite/it8772f/it8772f.h | 3 --- src/superio/nsc/pc87417/pc87417.h | 2 +- src/superio/winbond/w83627ehg/w83627ehg.h | 2 +- src/superio/winbond/w83627hf/w83627hf.h | 2 +- src/superio/winbond/w83697hf/w83697hf.h | 3 --- 41 files changed, 31 insertions(+), 92 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index a3555d8..890c77f 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -140,7 +140,6 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff -#if !defined(__ROMCC__) #if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> @@ -158,11 +157,7 @@ struct cpu_driver { struct acpi_cstate *cstates; }; -struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); -#else -#include <arch/io.h> -#endif struct cpu_info { device_t cpu; @@ -187,7 +182,11 @@ static inline unsigned long cpu_index(void) ci = cpu_info(); return ci->index; } +#else +#include <arch/io.h> +#endif +#ifndef __ROMCC__ // romcc is segfaulting in some cases struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ @@ -195,7 +194,7 @@ struct cpuinfo_x86 { uint8_t x86_mask; }; -static void inline get_fms(struct cpuinfo_x86 *c, uint32_t tfms) +static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) { c->x86 = (tfms >> 8) & 0xf; c->x86_model = (tfms >> 4) & 0xf; @@ -206,9 +205,8 @@ static void inline get_fms(struct cpuinfo_x86 *c, uint32_t tfms) c->x86_model += ((tfms >> 16) & 0xF) << 4; } +#endif #define asmlinkage __attribute__((regparm(0))) -#endif - #endif /* ARCH_CPU_H */ diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8f4368f..c550cfa 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -122,7 +122,7 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif -#ifndef __ROMCC__ +#if !defined(__ROMCC__) // FIXME romcc should handle below constructs #if defined(__PRE_RAM__) struct pei_data; diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index d440c70..1773cc8 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -97,7 +97,6 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -#ifndef __ROMCC__ #ifdef __SMM__ /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); @@ -106,6 +105,5 @@ void intel_model_206ax_finalize_smm(void); void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); #endif -#endif #endif diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index 630252b..62424f1 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -1,5 +1,3 @@ -#ifndef _NE2K_H__ -#define _NE2K_H__ /* * This file is part of the coreboot project. * @@ -19,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __ROMCC__ +#ifndef _NE2K_H__ +#define _NE2K_H__ void ne2k_append_data(unsigned char *d, int len, unsigned int base); int ne2k_init(unsigned int eth_nic_base); void ne2k_transmit(unsigned int eth_nic_base); -#endif #endif /* _NE2K_H */ diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index c0467be..ee55c2f 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -511,7 +511,7 @@ #define PMLogic_BASE (0x9D00) -#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(void); void SystemPreInit(void); diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 632bfe2..4eee156 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -630,7 +630,7 @@ #define DELAY_UPPER_DISABLE_CLK135 (1 << 23) #define DELAY_LOWER_STATUS_MASK 0x7C0 -#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated); void SystemPreInit(void); diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index f4c4d72..8bfae60 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -105,9 +105,7 @@ typedef struct { int num_states; } sst_table_t; -#ifndef __ROMCC__ void speedstep_gen_pstates(sst_table_t *); -#endif #define SPEEDSTEP_MAX_POWER_YONAH 31000 #define SPEEDSTEP_MIN_POWER_YONAH 13100 diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 54b2f54..d4f3232 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -51,7 +51,6 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) return lapic_read(LAPIC_ID) >> 24; } -#ifndef __ROMCC__ #if !CONFIG_AP_IN_SIPI_WAIT /* If we need to go back to sipi wait, we use the long non-inlined version of * this function in lapic_cpu_init.c @@ -155,6 +154,5 @@ int start_cpu(struct device *cpu); #endif /* !__PRE_RAM__ */ int boot_cpu(void); -#endif #endif /* CPU_X86_LAPIC_H */ diff --git a/src/include/delay.h b/src/include/delay.h index 0333879..676579b 100644 --- a/src/include/delay.h +++ b/src/include/delay.h @@ -1,8 +1,6 @@ #ifndef DELAY_H #define DELAY_H -#if !defined( __ROMCC__) - #if CONFIG_HAVE_INIT_TIMER void init_timer(void); #else @@ -12,6 +10,4 @@ void init_timer(void); void udelay(unsigned usecs); void mdelay(unsigned msecs); void delay(unsigned secs); - -#endif #endif /* DELAY_H */ diff --git a/src/include/ehci.h b/src/include/ehci.h index 29347f9..7ec9810 100644 --- a/src/include/ehci.h +++ b/src/include/ehci.h @@ -25,7 +25,6 @@ #define EHCI_BAR_INDEX 0x10 -#ifndef __ROMCC__ /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ /* Section 2.2 Host Controller Capability Registers */ @@ -201,4 +200,3 @@ struct ehci_dbg_port { #define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) } __attribute__ ((packed)); #endif -#endif diff --git a/src/include/ip_checksum.h b/src/include/ip_checksum.h index de26fa0..a1e0ffa 100644 --- a/src/include/ip_checksum.h +++ b/src/include/ip_checksum.h @@ -1,8 +1,5 @@ #ifndef IP_CHECKSUM_H #define IP_CHECKSUM_H - -#ifndef __ROMCC__ unsigned long compute_ip_checksum(void *addr, unsigned long length); unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new); -#endif #endif /* IP_CHECKSUM_H */ diff --git a/src/include/lib.h b/src/include/lib.h index 40c76f2..1f71d35 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -22,7 +22,6 @@ #ifndef __LIB_H__ #define __LIB_H__ #include <stdint.h> -#ifndef __ROMCC__ /* romcc doesn't support prototypes. */ #ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */ /* Defined in src/lib/clog2.c */ @@ -43,8 +42,10 @@ void quick_ram_check(void); /* Defined in src/lib/stack.c */ int checkstack(void *top_of_stack, int core); +#ifndef __PRE_RAM__ // fails in bootblock compiled with romcc /* currently defined by a ldscript */ extern unsigned char _estack[]; +#endif /* Defined in romstage.c */ #if CONFIG_CPU_AMD_GEODE_LX @@ -53,5 +54,4 @@ void cache_as_ram_main(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #endif -#endif /* __ROMCC__ */ #endif /* __LIB_H__ */ diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index f8e2b48..f4f0dca 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -58,7 +58,5 @@ #define PPCB_SPKR 0x02 /* Bit 1 */ #define PPCB_T2GATE 0x01 /* Bit 0 */ -#ifndef __ROMCC__ void setup_i8254(void); #endif -#endif diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index ee1473b..29e0348 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -203,9 +203,7 @@ static inline int get_option(void *dest __attribute__((unused)), #define CMOS_POST_BANK_1_MAGIC 0x81 #define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) -#if !defined(__ROMCC__) void cmos_post_log(void); -#endif #endif /* CONFIG_CMOS_POST */ #endif /* PC80_MC146818RTC_H */ diff --git a/src/include/reset.h b/src/include/reset.h index 79bf6d5..9f117db 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -1,9 +1,6 @@ #ifndef RESET_H #define RESET_H -#if !defined( __ROMCC__ ) -/* ROMCC can't do function prototypes... */ - #if CONFIG_HAVE_HARD_RESET void hard_reset(void); #else @@ -12,4 +9,3 @@ void hard_reset(void); void soft_reset(void); #endif -#endif diff --git a/src/include/uart.h b/src/include/uart.h index 6b8d8e8..9601bfa 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -30,7 +30,7 @@ #include <uart8250.h> #endif -#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); diff --git a/src/include/uart8250.h b/src/include/uart8250.h index d1164c5..d42e822 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -114,7 +114,6 @@ /* Line Control Settings */ #define UART_LCS CONFIG_TTYS0_LCS -#ifndef __ROMCC__ #if CONFIG_CONSOLE_SERIAL8250 unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); @@ -145,8 +144,6 @@ void oxford_init(void); #endif #endif -#endif /* __ROMCC__ */ - #endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ #endif /* UART8250_H */ diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index 8caf361..c3b3437 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -34,7 +34,6 @@ struct ehci_debug_info { u8 bufidx; }; -#ifndef __ROMCC__ void enable_usbdebug(unsigned int port); int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size); int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size); @@ -47,4 +46,3 @@ void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data); void usbdebug_tx_flush(struct ehci_debug_info *info); int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info); #endif -#endif diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h index df0e929..05c3889 100644 --- a/src/northbridge/intel/e7501/raminit.h +++ b/src/northbridge/intel/e7501/raminit.h @@ -15,8 +15,6 @@ struct mem_controller { uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; }; -#ifndef __ROMCC__ void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/i3100/raminit.h b/src/northbridge/intel/i3100/raminit.h index 03e1458..ea6c60f 100644 --- a/src/northbridge/intel/i3100/raminit.h +++ b/src/northbridge/intel/i3100/raminit.h @@ -30,8 +30,6 @@ struct mem_controller { u16 channel1[DIMM_SOCKETS]; }; -#ifndef __ROMCC__ void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif #endif diff --git a/src/southbridge/amd/cs5535/cs5535.h b/src/southbridge/amd/cs5535/cs5535.h index 0db7c17..0b43563 100644 --- a/src/southbridge/amd/cs5535/cs5535.h +++ b/src/southbridge/amd/cs5535/cs5535.h @@ -115,7 +115,7 @@ /* Flash Memory Mask values */ #define FLASH_MEM_4K 0xFFFFF000 -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cs5535_disable_internal_uart(void); #else diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index 84738a2..c193d9d 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -442,7 +442,7 @@ #define FLASH_IO_128B 0x0000FF80 #define FLASH_IO_256B 0x0000FF00 -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cs5536_setup_onchipuart(int uart); void cs5536_disable_internal_uart(void); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7f64571..3904866 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -56,7 +56,7 @@ void intel_pch_finalize_smm(void); #endif -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #if !defined(__SMM__) #include "chip.h" diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 76d5fc7..e6062c6 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,26 +21,19 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) #if !defined(__PRE_RAM__) -#if !defined(__ACPI__) /* dsdt include */ - #include <arch/io.h> #include <device/device.h> #include "chip.h" - void i82371eb_enable(device_t dev); void i82371eb_hard_reset(void); - -#endif -#endif -#endif - -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#else void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); void enable_pm(void); #endif +#endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the * 'reg' variable, otherwise it clears those bits. diff --git a/src/southbridge/intel/i82801ax/i82801ax.h b/src/southbridge/intel/i82801ax/i82801ax.h index ed15bba..f459f2f 100644 --- a/src/southbridge/intel/i82801ax/i82801ax.h +++ b/src/southbridge/intel/i82801ax/i82801ax.h @@ -24,9 +24,7 @@ #if !defined(__PRE_RAM__) #include "chip.h" void i82801ax_enable(device_t dev); -#endif - -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#else void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); #endif diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h index 202b41c..b2ee79c 100644 --- a/src/southbridge/intel/i82801bx/i82801bx.h +++ b/src/southbridge/intel/i82801bx/i82801bx.h @@ -26,7 +26,7 @@ extern void i82801bx_enable(device_t dev); #endif -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); #endif diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index dba5bd6..c7d7e77 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -31,7 +31,7 @@ #ifndef I82801DX_H #define I82801DX_H -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801dx_enable(device_t dev); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index b5df5d9..1064dde 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -37,7 +37,7 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7246739..21933b4 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -21,7 +21,6 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H - /* * Lynx Point PCH PCI Devices: * @@ -125,7 +124,7 @@ struct rcba_config_instruction u32 or_value; }; -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); int pch_silicon_type(void); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 5454d79..4fb3391 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -33,9 +33,7 @@ void mcp55_enable(device_t dev); extern struct pci_operations mcp55_pci_ops; #else -#if !defined(__ROMCC__) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif -#endif #endif diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h index 6c1e7e2..6085ab5 100644 --- a/src/southbridge/sis/sis966/sis966.h +++ b/src/southbridge/sis/sis966/sis966.h @@ -35,8 +35,6 @@ #define DEBUG_USB 0 #define DEBUG_USB2 0 -#if !defined(__ROMCC__) void sis966_enable(device_t dev); -#endif #endif /* SIS966_H */ diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index b43ce3c..3cca58d 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -145,7 +145,6 @@ __attribute__ ((packed)) #ifdef __PRE_RAM__ -#ifndef __ROMCC__ u8 smbus_read_byte(u8 dimm, u8 offset); void smbus_write_byte(u8 dimm, u8 offset, u8 data); void enable_smbus(void); @@ -155,7 +154,6 @@ void vt8237_sb_enable_fid_vid(void); void enable_rom_decode(void); void vt8237_early_spi_init(void); int vt8237_early_network_init(struct vt8237_network_rom *rom); -#endif #else void writeback(device_t dev, u16 where, u8 what); void dump_south(device_t dev); diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 0616c2a..5ec6188 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -35,11 +35,8 @@ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ -#ifndef __ROMCC__ void it8712f_kill_watchdog(void); void it8712f_enable_serial(device_t dev, u16 iobase); void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); #endif - -#endif diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index be9f720..6657db4 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -41,7 +41,7 @@ void init_ec(u16 base); #endif -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void it8716f_disable_dev(device_t dev); void it8716f_enable_dev(device_t dev, u16 iobase); void it8716f_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 4da5af5..527d1c2 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -33,7 +33,7 @@ #define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void it8718f_24mhz_clkin(void); void it8718f_disable_reboot(void); void it8718f_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h index cca404a..25300e6 100644 --- a/src/superio/ite/it8721f/it8721f.h +++ b/src/superio/ite/it8721f/it8721f.h @@ -32,7 +32,7 @@ #define IT8721F_GPIO 0x07 /* GPIO */ #define IT8721F_IR 0x0a /* Consumer IR */ -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void it8721f_24mhz_clkin(void); void it8721f_disable_reboot(void); void it8721f_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 343d9b3..f881d7a 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -105,7 +105,6 @@ #define GPIO_REG_ENABLE(x) (0xc0 + (x)) #define GPIO_REG_OUTPUT(x) (0xc8 + (x)) -#ifndef __ROMCC__ u8 it8772f_sio_read(u8 index); void it8772f_sio_write(u8 index, u8 value); void it8772f_enable_serial(device_t dev, u16 iobase); @@ -116,5 +115,3 @@ void it8772f_ac_resume_southbridge(void); void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup, u8 output, u8 enable); #endif - -#endif diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index 7208c8e..73c1fbc 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -114,7 +114,7 @@ #define PC87417_XSCNF 0x15 #define PC87417_XWBCNF 0x16 -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void pc87417_enable_serial(device_t dev, u16 iobase); void pc87417_enable_dev(device_t dev); #endif diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index deab7ce..c982603 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,7 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void w83627ehg_enable_dev(device_t dev, u16 iobase); void w83627ehg_disable_dev(device_t dev); void w83627ehg_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index 423ba8f..468cb55 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -113,7 +113,7 @@ #define W83627HF_XSCNF 0x15 #define W83627HF_XWBCNF 0x16 -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void w83627hf_disable_dev(device_t dev); void w83627hf_enable_dev(device_t dev, u16 iobase); void w83627hf_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 741d5b2..7e353e2 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -32,8 +32,5 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ -#ifndef __ROMCC__ void w83697hf_set_clksel_48(device_t); #endif - -#endif

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Patch merged into coreboot/master: d654f42 AMD: Reduce stack size from 64 KB to the default of 4 KB
by gerrit＠coreboot.org 09 May '13

09 May '13

the following patch was just integrated into master: commit d654f42e271b2daa17a4daddcb7c9603aa25e018 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed May 8 13:23:14 2013 +0200 AMD: Reduce stack size from 64 KB to the default of 4 KB Apply the following commit to all AMD boards. commit 935850e08293cec1cb27d12358b27285e780566a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 6 16:16:03 2013 -0700 asrock/e350m1: reduce default stack size The stack used on the ASRock E350M1 is significantly less than what we currently set (64k per core). In fact, we use about half of the default stack size (4k) on core 0 and even less on non BSP cores [1]: $ grep stack coreboot_without_patch_but_monotonic_timer.log CPU1: stack_base 002a0000, stack_end 002afff8 CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes […] Reviewed-on: http://review.coreboot.org/3209 Please note that AGESA seems to define bigger stack sizes. But these seem to be too much too. $ git grep STACK_SIZE src/vendorcode/amd […] src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define BSP_STACK_SIZE 16384 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE0_STACK_SIZE 16384 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE1_STACK_SIZE 4096 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: BSP_STACK_SIZE, src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: CORE0_STACK_SIZE, src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: CORE1_STACK_SIZE, […] The following command was used to create the patch. $ git grep -l STACK_SIZE src/mainboard/ | xargs sed -i '/STACK_SIZE/,+3d' Change-Id: I36b95b7a6f190b64d0639fc036ce2fb0253f3fa1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3217 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3217 for details. -gerrit

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New patch to review for coreboot: 6d66fa6 PC Engines ALIX 1C: Make it compatible with nvramtool.
by Denis Carikli 08 May '13

08 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3222 -gerrit commit 6d66fa6e233cb83a5a4a815d3824bddd27b7f6a5 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed May 8 23:15:11 2013 +0200 PC Engines ALIX 1C: Make it compatible with nvramtool. This commit was inspired by the Lenovo X60 mainboard.c code. It was tested on the ALIX 1C with the following result: The first boot had garbage on serial, but the second boot was ok and nvramtool worked: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Disable baud_rate = 115200 power_on_after_fail = Disable debug_level = Spew # Bad value -> boot_first = 0xf # Bad value -> boot_second = 0xf # Bad value -> boot_third = 0xf boot_index = 0xf boot_countdown = 0x7f Change-Id: I4553db56be8e016b60b0c2d44b1bfd8265f3dd55 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/pcengines/alix1c/Kconfig | 1 + src/mainboard/pcengines/alix1c/mainboard.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 315b7ed..ea3c17a 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_DEFAULT_DISABLE + select HAVE_OPTION_TABLE config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/alix1c/mainboard.c b/src/mainboard/pcengines/alix1c/mainboard.c index 7c67fce..e8032a3 100644 --- a/src/mainboard/pcengines/alix1c/mainboard.c +++ b/src/mainboard/pcengines/alix1c/mainboard.c @@ -19,10 +19,28 @@ #include <console/console.h> #include <device/device.h> +#include <pc80/mc146818rtc.h> static void init(struct device *dev) { + u8 defaults_loaded = 0; + printk(BIOS_DEBUG, "ALIX1.C ENTER %s\n", __func__); + + if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) { + printk(BIOS_INFO, "failed to get cmos_defaults_loaded"); + defaults_loaded = 0; + } + if (!defaults_loaded) { + printk(BIOS_INFO, "Restoring CMOS defaults\n"); + /* set baudrate to 115200 baud */ + set_option("baud_rate", &(u8[]){ 0x00 }); + /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */ + set_option("debug_level", + &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 }); + set_option("cmos_defaults_loaded", &(u8[]){ 0x01 }); + } + printk(BIOS_DEBUG, "ALIX1.C EXIT %s\n", __func__); }

1 0

Patch merged into coreboot/master: 3949e37 Drop CONFIG_AP_CODE_IN_CAR
by gerrit＠coreboot.org 08 May '13

08 May '13

the following patch was just integrated into master: commit 3949e3783409ec1ddda25116d06da2a7e16c6c51 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 6 16:56:37 2013 -0700 Drop CONFIG_AP_CODE_IN_CAR This option has not been enabled on any board and was considered obsolete last time it was touched. If we need the functionality, let's fix this in a generic way instead of a K8 specific way. This was mostly a speedup hack back in the day. Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/3211 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/3211 for details. -gerrit

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coreboot-gerrit May 2013