coreboot-gerrit May 2013

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Patch set updated for coreboot: 964513e Intel Lynx Point: LPC: Unify I/O APIC setup
by Paul Menzel 08 May '13

08 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3182 -gerrit commit 964513e1e9c407ea29736ff6e5126d80257474c5 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:17:02 2013 +0200 Intel Lynx Point: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/lpc.c | 48 +++++++++++++---------------------- src/southbridge/intel/lynxpoint/pch.h | 1 + 2 files changed, 18 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 40e0468..be68549 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -43,43 +43,29 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void pch_enable_ioapic(struct device *dev) { - int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); + /* Enable ACPI I/O range decode */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, 0x01, reg32); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) @@ -547,7 +533,7 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7246739..44182e3 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -237,6 +237,7 @@ unsigned get_gpios(const int *gpio_num_array); #define PMBASE 0x40 #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */

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Patch merged into coreboot/master: 37f8c3a cbfs_core.c: make cfbs searches even less verbose
by gerrit＠coreboot.org 08 May '13

08 May '13

the following patch was just integrated into master: commit 37f8c3af0e8a7527eacac4646ef19239413b3328 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon May 6 15:51:39 2013 -0600 cbfs_core.c: make cfbs searches even less verbose The cbfs core code would print out the name of the file it is searching for and when it is found would print out the name again. This contributes to a lot of unnecessary messages in a functioning payload’s output. Change this message to a DEBUG one so that it will only be printed when CONFIG_DEBUG_CBFS is enabled. Change-Id: Ib238ff174bedba8eaaad8d1d452721fcac339b1a Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3208 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3208 for details. -gerrit

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Patch set updated for coreboot: 2719eb6 copy_and_run: drop boot_complete parameter
by Stefan Reinauer 08 May '13

08 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3213 -gerrit commit 2719eb67b555aaa211e7efbc788e9f9b63eda420 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 6 18:05:39 2013 -0700 copy_and_run: drop boot_complete parameter Since this parameter is not used anymore, drop it from all calls to copy_and_run() Change-Id: Ifba25aff4b448c1511e26313fe35007335aa7f7a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/stages.h | 3 +-- src/arch/x86/init/crt0_romcc_epilogue.inc | 5 ----- src/arch/x86/lib/c_start.S | 1 - src/arch/x86/lib/cbfs_and_run.c | 13 ++++--------- src/arch/x86/lib/stages.c | 2 -- src/cpu/amd/car/post_cache_as_ram.c | 2 +- src/cpu/amd/geode_gx2/cache_as_ram.inc | 4 ---- src/cpu/amd/geode_lx/cache_as_ram.inc | 4 ---- src/cpu/intel/car/cache_as_ram.inc | 5 ----- src/cpu/intel/car/cache_as_ram_ht.inc | 5 ----- src/cpu/intel/haswell/romstage.c | 2 +- src/cpu/intel/model_206ax/cache_as_ram.inc | 5 ----- src/cpu/intel/model_6ex/cache_as_ram.inc | 5 ----- src/cpu/via/car/cache_as_ram.inc | 5 ----- src/mainboard/amd/dinar/romstage.c | 2 +- src/mainboard/amd/inagua/romstage.c | 2 +- src/mainboard/amd/parmer/romstage.c | 2 +- src/mainboard/amd/persimmon/romstage.c | 2 +- src/mainboard/amd/south_station/romstage.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 2 +- src/mainboard/amd/torpedo/romstage.c | 2 +- src/mainboard/amd/union_station/romstage.c | 2 +- src/mainboard/asrock/e350m1/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/emulation/qemu-x86/cache_as_ram.inc | 5 ----- src/mainboard/lippert/frontrunner-af/romstage.c | 2 +- src/mainboard/lippert/toucan-af/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/romstage.c | 2 +- src/mainboard/supermicro/h8scm/romstage.c | 2 +- src/mainboard/tyan/s8226/romstage.c | 2 +- 30 files changed, 22 insertions(+), 74 deletions(-) diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 0d00144..3dea427 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -22,6 +22,5 @@ #include <arch/cpu.h> -void asmlinkage copy_and_run(unsigned cpu_reset); -void asmlinkage copy_and_run_ap_code_in_car(unsigned ret_addr); +void asmlinkage copy_and_run(void); #endif diff --git a/src/arch/x86/init/crt0_romcc_epilogue.inc b/src/arch/x86/init/crt0_romcc_epilogue.inc index b19f968..419418d 100644 --- a/src/arch/x86/init/crt0_romcc_epilogue.inc +++ b/src/arch/x86/init/crt0_romcc_epilogue.inc @@ -7,17 +7,12 @@ */ #include <cpu/x86/post_code.h> - /* clear boot_complete flag */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* clear direction flag */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index 99a4d92..1e38aca 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -77,7 +77,6 @@ _start: #if CONFIG_GDB_WAIT call gdb_stub_breakpoint #endif - /* The boot_complete flag has already been pushed */ call hardwaremain /* NOTREACHED */ .Lhlt: diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 2db50a1..6379842 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -22,7 +22,7 @@ #include <arch/stages.h> #include <timestamp.h> -static void cbfs_and_run_core(const char *filename, unsigned ebp) +static void cbfs_and_run_core(const char *filename) { u8 *dst; @@ -35,17 +35,12 @@ static void cbfs_and_run_core(const char *filename, unsigned ebp) timestamp_add_now(TS_END_COPYRAM); print_debug("Jumping to image.\n"); __asm__ volatile ( - "movl %%eax, %%ebp\n" "jmp *%%edi\n" - :: "a"(ebp), "D"(dst) + :: "D"(dst) ); } -void asmlinkage copy_and_run(unsigned cpu_reset) +void asmlinkage copy_and_run(void) { - // FIXME fix input parameters instead normalizing them here. - if (cpu_reset == 1) cpu_reset = -1; - else cpu_reset = 0; - - cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset); + cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram"); } diff --git a/src/arch/x86/lib/stages.c b/src/arch/x86/lib/stages.c index a6a232a..2da66d3 100644 --- a/src/arch/x86/lib/stages.c +++ b/src/arch/x86/lib/stages.c @@ -20,8 +20,6 @@ static void skip_romstage(void) { asm volatile ( - "/* set the boot_complete flag */\n" - "movl $0xffffffff, %%ebp\n" "jmp __main\n" ); } diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 861948f..68e7c09 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -165,7 +165,7 @@ static void post_cache_as_ram(void) set_sysinfo_in_ram(1); // So other core0 could start to train mem /*copy and execute coreboot_ram */ - copy_and_run(0); + copy_and_run(); /* We will not return */ print_debug("should not be here -\n"); diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 941d507..6a107fe 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -182,8 +182,6 @@ done_cache_as_ram_main: xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ movl %eax, %cr0 - /* clear boot_complete flag */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) @@ -197,8 +195,6 @@ __main: * the location it is compiled to run at. * Normally this is copying from FLASH ROM to RAM. */ - movl %ebp, %esi - pushl %esi call copy_and_run .Lhlt: diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index 3146fd2..d2c2415 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -208,8 +208,6 @@ done_cache_as_ram_main: xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ movl %eax, %cr0 - /* clear boot_complete flag */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) @@ -223,8 +221,6 @@ __main: * the location it is compiled to run at. * Normally this is copying from FLASH ROM to RAM. */ - movl %ebp, %esi - pushl %esi call copy_and_run .Lhlt: diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 781e480..1ea50b8 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -357,17 +357,12 @@ lout: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 9ef69ad..8a845e9 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -431,17 +431,12 @@ no_msr_11e: post_code(0x3c) - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 077e409..1093e6b 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -326,7 +326,7 @@ void romstage_after_car(void) #endif /* Load the ramstage. */ - copy_and_run(0); + copy_and_run(); } diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 4202da9..2652cb7 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -316,17 +316,12 @@ __acpi_resume_backup_done: post_code(0x3d) - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index b8222e1..50fab35 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -225,17 +225,12 @@ clear_mtrrs: post_code(0x3c) - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 1af8ecc..17b4b83 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -264,17 +264,12 @@ testok: movl %eax, %cr0 invd - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index a9bcde0..77f73e2 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("done\n"); post_code(0x44); - copy_and_run(0); + copy_and_run(); post_code(0x45); // Should never see this post code. } diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index d46d4ab..3474d76 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254(); post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 25f14e8..7cd7638 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 (); post_code(0x50); - copy_and_run(0); + copy_and_run(); post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index eedae56..b748a90 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 (); post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index c273344..970046d 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 1f3e86d..601aa7e 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -168,7 +168,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 (); post_code(0x50); - copy_and_run(0); + copy_and_run(); post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 8edba80..bbcd764 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x43); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run returned!\n"); post_code(0x44); // Should never see this post code. diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 9045c04..93aa327 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -106,7 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 96339b9..7e806fa 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -122,7 +122,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254(); post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index c2fc75e..b7bcf43 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -199,7 +199,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 (); post_code(0x50); - copy_and_run(0); + copy_and_run(); post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/emulation/qemu-x86/cache_as_ram.inc b/src/mainboard/emulation/qemu-x86/cache_as_ram.inc index 1a7d8af..11ac91d 100644 --- a/src/mainboard/emulation/qemu-x86/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-x86/cache_as_ram.inc @@ -80,17 +80,12 @@ __acpi_resume_backup_done: post_code(0x3d) - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index b04b0ea..8913568 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -182,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 (); post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index b5ff31f..ebc4d0e 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -182,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 (); post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 45422bb..0d25113 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("done\n"); post_code(0x51); - copy_and_run(0); + copy_and_run(); /* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n"); diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 3219fda..5dccf78 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("done\n"); post_code(0x51); - copy_and_run(0); + copy_and_run(); /* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n"); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index ee16ceb..b4f9523 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x51); setup_i8259 (); setup_i8254 (); - copy_and_run(0); + copy_and_run(); /* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n");

1 0

Patch set updated for coreboot: f7bc16e hardwaremain: drop boot_complete parameter
by Stefan Reinauer 08 May '13

08 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3212 -gerrit commit f7bc16e31aaba6a187fa453a501968ec13526163 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 6 16:49:56 2013 -0700 hardwaremain: drop boot_complete parameter it has been unused since 9 years or so, hence drop it. Change-Id: I0706feb7b3f2ada8ecb92176a94f6a8df53eaaa1 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/lib/c_start.S | 9 --------- src/include/bootstate.h | 2 +- src/lib/hardwaremain.c | 12 +++--------- src/mainboard/emulation/qemu-armv7/ramstage.c | 6 ++---- src/mainboard/google/snow/ramstage.c | 8 +++----- src/northbridge/via/vx800/examples/chipset_init.c | 2 +- 6 files changed, 10 insertions(+), 29 deletions(-) diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index 32af0cc..99a4d92 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -49,12 +49,6 @@ _start: pushl $0 pushl $0 - /* push the boot_complete flag */ - pushl %ebp - - /* Save the stack location */ - movl %esp, %ebp - /* Initialize the Interrupt Descriptor table */ leal _idt, %edi leal vec0, %ebx @@ -80,9 +74,6 @@ _start: */ post_code(POST_PRE_HARDWAREMAIN) /* post fe */ - /* Restore the stack location */ - movl %ebp, %esp - #if CONFIG_GDB_WAIT call gdb_stub_breakpoint #endif diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 0370c36..40822a7 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -165,7 +165,7 @@ void boot_state_current_block(void); void boot_state_current_unblock(void); /* Entry into the boot state machine. */ -void hardwaremain(int boot_complete); +void hardwaremain(void); /* In order to schedule boot state callbacks at compile-time specify the * entries in an array using the BOOT_STATE_INIT_ENTRIES and diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 13aa512..99b4a06 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -444,7 +444,7 @@ static void boot_state_schedule_static_entries(void) } } -void hardwaremain(int boot_complete) +void hardwaremain(void) { timestamp_stash(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); @@ -454,17 +454,11 @@ void hardwaremain(int boot_complete) post_code(POST_CONSOLE_READY); - printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", - coreboot_version, coreboot_extra_version, coreboot_build, - (boot_complete)?"rebooting":"booting"); + printk(BIOS_NOTICE, "coreboot-%s%s %s booting...\n", + coreboot_version, coreboot_extra_version, coreboot_build); post_code(POST_CONSOLE_BOOT_MSG); - /* If we have already booted attempt a hard reboot */ - if (boot_complete) { - hard_reset(); - } - /* Schedule the static boot state entries. */ boot_state_schedule_static_entries(); diff --git a/src/mainboard/emulation/qemu-armv7/ramstage.c b/src/mainboard/emulation/qemu-armv7/ramstage.c index 24d0d7f..5fce9fa 100644 --- a/src/mainboard/emulation/qemu-armv7/ramstage.c +++ b/src/mainboard/emulation/qemu-armv7/ramstage.c @@ -15,10 +15,8 @@ #include <console/console.h> -void hardwaremain(int boot_complete); +void hardwaremain(void); void main(void) { - console_init(); - printk(BIOS_INFO, "hello from ramstage\n"); - hardwaremain(0); + hardwaremain(); } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 09b51a7..72f830d 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -77,12 +77,10 @@ void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) } -void hardwaremain(int boot_complete); +void hardwaremain(void); void main(void) { - console_init(); - printk(BIOS_INFO, - "hello from ramstage; now with deluxe exception handling.\n"); + /* FIXME this should be moved elsewhere. We don't want ramstage.c */ /* set up coreboot tables */ high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; @@ -114,7 +112,7 @@ void main(void) power_enable_xclkout(); - hardwaremain(0); + hardwaremain(); } /* TODO: transplanted DP stuff, clean up once we have something that works */ diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c index 1e06d47..d9b85e4 100644 --- a/src/northbridge/via/vx800/examples/chipset_init.c +++ b/src/northbridge/via/vx800/examples/chipset_init.c @@ -604,7 +604,7 @@ void init_VIA_chipset(void) * In the dev_enumerate() phase, */ -void hardwaremain(int boot_complete) +void hardwaremain(void) { struct lb_memory *lb_mem; #if CONFIG_HAVE_ACPI_RESUME

1 0

Patch set updated for coreboot: 7ccf199 Drop CONFIG_AP_CODE_IN_CAR
by Stefan Reinauer 08 May '13

08 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3211 -gerrit commit 7ccf199777e991ade8d4e7d90a067adb688c4951 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 6 16:56:37 2013 -0700 Drop CONFIG_AP_CODE_IN_CAR This option has not been enabled on any board and was considered obsolete last time it was touched. If we need the functionality, let's fix this in a generic way instead of a K8 specific way. This was mostly a speedup hack back in the day. Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 4 - src/arch/x86/Makefile.inc | 18 ---- src/arch/x86/init/ldscript_apc.lb | 31 ------- src/arch/x86/lib/cbfs_and_run.c | 7 -- src/mainboard/amd/serengeti_cheetah/Kconfig | 1 - src/mainboard/amd/serengeti_cheetah/ap_romstage.c | 74 ---------------- src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c | 99 --------------------- src/mainboard/gigabyte/m57sli/ap_romstage.c | 97 --------------------- src/mainboard/msi/ms7260/ap_romstage.c | 82 ------------------ src/mainboard/nvidia/l1_2pvv/ap_romstage.c | 91 ------------------- src/mainboard/supermicro/h8dme/Kconfig | 1 - src/mainboard/supermicro/h8dme/ap_romstage.c | 97 --------------------- src/mainboard/supermicro/h8dmr/ap_romstage.c | 101 ---------------------- src/mainboard/tyan/s2912/ap_romstage.c | 89 ------------------- src/northbridge/amd/amdk8/raminit_f_dqs.c | 8 -- 15 files changed, 800 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index ce7f400..ce5a048 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -943,10 +943,6 @@ config DEBUG_COVERAGE endmenu # These probably belong somewhere else, but they are needed somewhere. -config AP_CODE_IN_CAR - bool - default n - config RAMINIT_SYSINFO bool default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index ee2bc47..62f7a3f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -48,9 +48,6 @@ endif ifeq ($(CONFIG_PAYLOAD_FILO),y) COREBOOT_ROM_DEPENDENCIES+=filo endif -ifeq ($(CONFIG_AP_CODE_IN_CAR),y) -COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf -endif extract_nth=$(word $(1), $(subst |, ,$(2))) @@ -79,10 +76,6 @@ endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB_ELF) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp - if [ -f $(objcbfs)/coreboot_ap.elf ]; \ - then \ - $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ap.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ap -c $(CBFS_COMPRESS_FLAG); \ - fi $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf " PAYLOAD none (as specified by user)\n" @@ -188,17 +181,6 @@ else endif ################################################################################ -# Ramstage for AP CPU (AMD K8, obsolete?) - -$(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $< - -$(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ - -################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc diff --git a/src/arch/x86/init/ldscript_apc.lb b/src/arch/x86/init/ldscript_apc.lb deleted file mode 100644 index 1c64c69..0000000 --- a/src/arch/x86/init/ldscript_apc.lb +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -INCLUDE "ldoptions" -SECTIONS -{ - .apcrom . : { - _apcrom = .; - *(.text) - *(.rodata) - *(.rodata.*) - _eapcrom = .; - } -} diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index a023141..2db50a1 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -49,10 +49,3 @@ void asmlinkage copy_and_run(unsigned cpu_reset) cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset); } - -#if CONFIG_AP_CODE_IN_CAR -void asmlinkage copy_and_run_ap_code_in_car(unsigned ret_addr) -{ - cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr); -} -#endif diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index 26fa45f..b26803e 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - #select AP_CODE_IN_CAR select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c deleted file mode 100644 index fa680fe..0000000 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ /dev/null @@ -1,74 +0,0 @@ -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include "console/console.c" -#include "lib/uart8250.c" -#include "console/vtxprintf.c" - -#include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" - -#include "lib/delay.c" - -#include "northbridge/amd/amdk8/reset_test.c" - -#include "northbridge/amd/amdk8/debug.c" - -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" - -#include "northbridge/amd/amdk8/amdk8_f.h" - -#include "cpu/x86/mtrr.h" -#include "cpu/amd/mtrr.h" -#include "cpu/x86/tsc.h" - -#include "northbridge/amd/amdk8/amdk8_f_pci.c" -#include "northbridge/amd/amdk8/raminit_f_dqs.c" - -static inline unsigned get_nodes(void) -{ - return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; -} - -#include "cpu/amd/dualcore/dualcore.c" - -void hardwaremain(int ret_addr) -{ - struct sys_info *sysinfo = &sysinfo_car; // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM - - struct node_core_id id; - - id = get_node_core_id_x(); - - printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n", id.nodeid); - - train_ram(id.nodeid, sysinfo, sysinfox); - - /* - * go back, but can not use stack any more, because we - * only keep ret_addr and can not restore esp, and ebp. - */ - - __asm__ volatile ( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - :: "a"(ret_addr) - ); -} - -#include <arch/registers.h> - -void x86_exception(struct eregs *info) -{ - do { - hlt(); - } while(1); -} - diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c deleted file mode 100644 index 9def81d..0000000 --- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai(a)sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> - -#include "lib/uart8250.c" -#include "arch/x86/lib/printk_init.c" -#include "console/vtxprintf.c" -#include "console/console.c" - -#include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" - -#include "lib/delay.c" - -//#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" - -#include "northbridge/amd/amdk8/debug.c" - -#include "southbridge/sis/sis966/sis966_early_ctrl.c" - -#include "northbridge/amd/amdk8/amdk8_f.h" - -#include "cpu/x86/mtrr.h" -#include "cpu/amd/mtrr.h" -#include "cpu/x86/tsc.h" - -#include "northbridge/amd/amdk8/amdk8_f_pci.c" -#include "northbridge/amd/amdk8/raminit_f_dqs.c" - -#include "cpu/amd/dualcore/dualcore.c" - -void hardwaremain(int ret_addr) -{ - struct sys_info *sysinfo = &sysinfo_car; // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM - - struct node_core_id id; - - id = get_node_core_id_x(); - - //FIXME: for USBDEBUG you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); - - train_ram(id.nodeid, sysinfo, sysinfox); - - /* - go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp - */ - - __asm__ volatile ( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - :: "a"(ret_addr) - ); - - - -} - -#include <arch/registers.h> - -void x86_exception(struct eregs *info) -{ - do { - hlt(); - } while(1); -} - - diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c deleted file mode 100644 index df00eed..0000000 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> - -#include "lib/uart8250.c" -#include "arch/x86/lib/printk_init.c" -#include "console/vtxprintf.c" -#include "console/console.c" - -#include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" - -#include "lib/delay.c" - -//#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" - -#include "northbridge/amd/amdk8/debug.c" - -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - -#include "northbridge/amd/amdk8/amdk8_f.h" - -#include "cpu/x86/mtrr.h" -#include "cpu/amd/mtrr.h" -#include "cpu/x86/tsc.h" - -#include "northbridge/amd/amdk8/amdk8_f_pci.c" -#include "northbridge/amd/amdk8/raminit_f_dqs.c" - -#include "cpu/amd/dualcore/dualcore.c" - -void hardwaremain(int ret_addr) -{ - struct sys_info *sysinfo = &sysinfo_car; // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM - - struct node_core_id id; - - id = get_node_core_id_x(); - - //FIXME: for USBDEBUG you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); - - train_ram(id.nodeid, sysinfo, sysinfox); - - /* - go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp - */ - - __asm__ volatile ( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - :: "a"(ret_addr) - ); - - - -} - -#include <arch/registers.h> - -void x86_exception(struct eregs *info) -{ - do { - hlt(); - } while(1); -} - - diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c deleted file mode 100644 index f0a3dc4..0000000 --- a/src/mainboard/msi/ms7260/ap_romstage.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include "lib/uart8259.c" - -#include "console/console.c" -#include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" -#include "lib/delay.c" -/* #include "cpu/x86/lapic/boot_cpu.c" */ -#include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -#include "northbridge/amd/amdk8/amdk8_f.h" -#include "cpu/x86/mtrr.h" -#include "cpu/amd/mtrr.h" -#include "cpu/x86/tsc.h" -#include "northbridge/amd/amdk8/amdk8_f_pci.c" -#include "northbridge/amd/amdk8/raminit_f_dqs.c" -#include "cpu/amd/dualcore/dualcore.c" - -void hardwaremain(int ret_addr) -{ - struct sys_info *sysinfo = &sysinfo_car; /* in CACHE */ - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); /* in RAM */ - struct node_core_id id; - - id = get_node_core_id_x(); - - /* FIXME: For USBDEBUG you need to make sure dbg_info gets - * assigned in AP. - */ - print_debug("CODE IN CACHE ON NODE:"); - print_debug_hex8(id.nodeid); - print_debug("\n"); - - train_ram(id.nodeid, sysinfo, sysinfox); - - /* Go back, but cannot use stack any more, because we only - * keep ret_addr and can not restore esp, and ebp. - */ - __asm__ __volatile__( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - : : "a" (ret_addr) - ); -} - -#include <arch/registers.h> - -void x86_exception(struct eregs *info) -{ - while (1) - hlt(); -} diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c deleted file mode 100644 index 005de7b..0000000 --- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include "lib/uart8250.c" -#include "arch/x86/lib/printk_init.c" -#include "console/vtxprintf.c" -#include "console/console.c" - -#include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" - -#include "lib/delay.c" - -#include "northbridge/amd/amdk8/reset_test.c" - -#include "northbridge/amd/amdk8/debug.c" - -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - -#include "northbridge/amd/amdk8/amdk8_f.h" - -#include "cpu/x86/mtrr.h" -#include "cpu/amd/mtrr.h" -#include "cpu/x86/tsc.h" - -#include "northbridge/amd/amdk8/amdk8_f_pci.c" -#include "northbridge/amd/amdk8/raminit_f_dqs.c" - -#include "cpu/amd/dualcore/dualcore.c" - -void hardwaremain(int ret_addr) -{ - struct sys_info *sysinfo = &sysinfo_car; // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM - - struct node_core_id id; - - id = get_node_core_id_x(); - - //FIXME: for USBDEBUG you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); - - train_ram(id.nodeid, sysinfo, sysinfox); - - /* - * go back, but can not use stack any more, because we only keep - * ret_addr and can not restore esp, and ebp - */ - - __asm__ volatile ( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - :: "a"(ret_addr) - ); -} - -#include <arch/registers.h> - -void x86_exception(struct eregs *info) -{ - do { - hlt(); - } while(1); -} diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index 221ccb2..b8bd694 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - #select AP_CODE_IN_CAR select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c deleted file mode 100644 index ed2d16a..0000000 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> - -#include "console/console.c" -#include "lib/uart8250.c" -#include "console/vtxprintf.c" -#include "./arch/x86/lib/printk_init.c" - -#include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" - -#include "lib/delay.c" - -//#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" - -#include "northbridge/amd/amdk8/debug.c" - -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - -#include "northbridge/amd/amdk8/amdk8_f.h" - -#include "cpu/x86/mtrr.h" -#include "cpu/amd/mtrr.h" -#include "cpu/x86/tsc.h" - -#include "northbridge/amd/amdk8/amdk8_f_pci.c" -#include "northbridge/amd/amdk8/raminit_f_dqs.c" - -static inline unsigned get_nodes(void) -{ - return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; -} - -#include "cpu/amd/dualcore/dualcore.c" - -void hardwaremain(int ret_addr) -{ - struct sys_info *sysinfo = &sysinfo_car; // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM - - struct node_core_id id; - - id = get_node_core_id_x(); - - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); - - train_ram(id.nodeid, sysinfo, sysinfox); - - /* - * go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp - */ - - __asm__ volatile ( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - :: "a"(ret_addr) - ); -} - -#include <arch/registers.h> - -void x86_exception(struct eregs *info) -{ - do { - hlt(); - } while(1); -} - diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c deleted file mode 100644 index 8008bb2..0000000 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> - -#include "console/console.c" -#include "lib/uart8250.c" -#include "console/vtxprintf.c" -#include "./arch/x86/lib/printk_init.c" - -#include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" - -#include "lib/delay.c" - -//#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" - -#include "northbridge/amd/amdk8/debug.c" - -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - -#include "northbridge/amd/amdk8/amdk8_f.h" - -#include "cpu/x86/mtrr.h" -#include "cpu/amd/mtrr.h" -#include "cpu/x86/tsc.h" - -#include "northbridge/amd/amdk8/amdk8_f_pci.c" -#include "northbridge/amd/amdk8/raminit_f_dqs.c" - -static inline unsigned get_nodes(void) -{ - return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; -} - -#include "cpu/amd/dualcore/dualcore.c" - -void hardwaremain(int ret_addr) -{ - struct sys_info *sysinfo = &sysinfo_car; // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM - - struct node_core_id id; - - id = get_node_core_id_x(); - - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); - - train_ram(id.nodeid, sysinfo, sysinfox); - - /* - go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp - */ - - __asm__ volatile ( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - :: "a"(ret_addr) - ); - - - -} - -#include <arch/registers.h> - -void x86_exception(struct eregs *info) -{ - do { - hlt(); - } while(1); -} - - diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c deleted file mode 100644 index e22d2a5..0000000 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include "console/console.c" - -#include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" - -#include "lib/delay.c" - -//#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" - -#include "northbridge/amd/amdk8/debug.c" - -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - -#include "northbridge/amd/amdk8/amdk8_f.h" - -#include "cpu/x86/mtrr.h" -#include "cpu/amd/mtrr.h" -#include "cpu/x86/tsc.h" - -#include "northbridge/amd/amdk8/amdk8_f_pci.c" -#include "northbridge/amd/amdk8/raminit_f_dqs.c" - -#include "cpu/amd/dualcore/dualcore.c" - -void hardwaremain(int ret_addr) -{ - struct sys_info *sysinfo = &sysinfo_car; // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM - - struct node_core_id id; - - id = get_node_core_id_x(); - - //FIXME: for USBDEBUG you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); - - train_ram(id.nodeid, sysinfo, sysinfox); - - /* - go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp - */ - - __asm__ volatile ( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - :: "a"(ret_addr) - ); -} - -#include <arch/registers.h> - -void x86_exception(struct eregs *info) -{ - do { - hlt(); - } while(1); -} - diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index a7a4538..08a3bab 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -2103,16 +2103,8 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy memcpy(sysinfo, sysinfox, sizeof(*sysinfo)); #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's - #if !CONFIG_AP_CODE_IN_CAR printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid); train_ram(nodeid, sysinfo, sysinfox); - #else - /* Can copy dqs_timing to ap cache and run from cache? - * we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom for ap ? - */ - copy_and_run_ap_code_in_car(retcall); - // will go back by jump - #endif } } #endif

1 0

Patch merged into coreboot/master: ea23a6b src/cpu/amd/agesa/Kconfig: Use tabs instead of spaces for alignment
by gerrit＠coreboot.org 08 May '13

08 May '13

the following patch was just integrated into master: commit ea23a6b23f2e15ed1805918d3b7105582f3789f0 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu May 2 10:34:49 2013 +0200 src/cpu/amd/agesa/Kconfig: Use tabs instead of spaces for alignment Some entries still used spaces while others used tabulators[1]. Convert spaces to tabs to uniformly use tabs. ---------------------- 8< -------------- 8< ----------------------------- For all of the Kconfig* configuration files throughout the source tree, the indentation is somewhat different. Lines under a "config" definition are indented with one tab, while help text is indented an additional two spaces. [2] ---------------------- 8< -------------- 8< ----------------------------- [1] http://en.wikipedia.org/wiki/File:HollerithMachine.CHM.jpg [2] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documen… Change-Id: Iee80ad4a90e95b925afbb0c6adc563fa3a6503cf Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3173 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/3173 for details. -gerrit

1 0

Patch set updated for coreboot: 23c2ce9 Drop prototype guarding for romcc
by Paul Menzel 07 May '13

07 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3216 -gerrit commit 23c2ce9045b825dbfa238f0c3742f64ed8661ca8 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue May 7 20:35:29 2013 +0200 Drop prototype guarding for romcc Commit »romcc: Don't fail on function prototypes« (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/include/arch/cpu.h | 3 --- src/cpu/intel/haswell/haswell.h | 4 ---- src/cpu/intel/model_206ax/model_206ax.h | 2 -- src/include/console/ne2k.h | 6 ++---- src/include/cpu/amd/gx2def.h | 2 +- src/include/cpu/amd/lxdef.h | 2 +- src/include/cpu/intel/speedstep.h | 2 -- src/include/cpu/x86/lapic.h | 2 -- src/include/delay.h | 4 ---- src/include/ehci.h | 2 -- src/include/ip_checksum.h | 3 --- src/include/lib.h | 2 -- src/include/pc80/i8254.h | 2 -- src/include/pc80/mc146818rtc.h | 2 -- src/include/reset.h | 4 ---- src/include/uart.h | 2 +- src/include/uart8250.h | 3 --- src/include/usbdebug.h | 2 -- src/northbridge/intel/e7501/raminit.h | 2 -- src/northbridge/intel/i3100/raminit.h | 2 -- src/southbridge/amd/cs5535/cs5535.h | 2 +- src/southbridge/amd/cs5536/cs5536.h | 2 +- src/southbridge/intel/bd82x6x/pch.h | 2 +- src/southbridge/intel/i82371eb/i82371eb.h | 13 +++---------- src/southbridge/intel/i82801ax/i82801ax.h | 4 +--- src/southbridge/intel/i82801bx/i82801bx.h | 2 +- src/southbridge/intel/i82801dx/i82801dx.h | 2 +- src/southbridge/intel/i82801gx/i82801gx.h | 2 +- src/southbridge/intel/lynxpoint/pch.h | 3 +-- src/southbridge/nvidia/mcp55/mcp55.h | 2 -- src/southbridge/sis/sis966/sis966.h | 2 -- src/southbridge/via/vt8237r/vt8237r.h | 2 -- src/superio/ite/it8712f/it8712f.h | 3 --- src/superio/ite/it8716f/it8716f.h | 2 +- src/superio/ite/it8718f/it8718f.h | 2 +- src/superio/ite/it8721f/it8721f.h | 2 +- src/superio/ite/it8772f/it8772f.h | 3 --- src/superio/nsc/pc87417/pc87417.h | 2 +- src/superio/winbond/w83627ehg/w83627ehg.h | 2 +- src/superio/winbond/w83627hf/w83627hf.h | 2 +- src/superio/winbond/w83697hf/w83697hf.h | 3 --- 41 files changed, 22 insertions(+), 90 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index a3555d8..bc85bca 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -140,7 +140,6 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff -#if !defined(__ROMCC__) #if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> @@ -209,6 +208,4 @@ static void inline get_fms(struct cpuinfo_x86 *c, uint32_t tfms) #define asmlinkage __attribute__((regparm(0))) -#endif - #endif /* ARCH_CPU_H */ diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8f4368f..1171bc0 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -122,8 +122,6 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif -#ifndef __ROMCC__ - #if defined(__PRE_RAM__) struct pei_data; struct rcba_config_instruction; @@ -194,5 +192,3 @@ struct ramstage_cache { } __attribute__((packed)); #endif - -#endif diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index d440c70..1773cc8 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -97,7 +97,6 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -#ifndef __ROMCC__ #ifdef __SMM__ /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); @@ -106,6 +105,5 @@ void intel_model_206ax_finalize_smm(void); void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); #endif -#endif #endif diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index 630252b..62424f1 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -1,5 +1,3 @@ -#ifndef _NE2K_H__ -#define _NE2K_H__ /* * This file is part of the coreboot project. * @@ -19,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __ROMCC__ +#ifndef _NE2K_H__ +#define _NE2K_H__ void ne2k_append_data(unsigned char *d, int len, unsigned int base); int ne2k_init(unsigned int eth_nic_base); void ne2k_transmit(unsigned int eth_nic_base); -#endif #endif /* _NE2K_H */ diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index c0467be..ee55c2f 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -511,7 +511,7 @@ #define PMLogic_BASE (0x9D00) -#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(void); void SystemPreInit(void); diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 632bfe2..4eee156 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -630,7 +630,7 @@ #define DELAY_UPPER_DISABLE_CLK135 (1 << 23) #define DELAY_LOWER_STATUS_MASK 0x7C0 -#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated); void SystemPreInit(void); diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index f4c4d72..8bfae60 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -105,9 +105,7 @@ typedef struct { int num_states; } sst_table_t; -#ifndef __ROMCC__ void speedstep_gen_pstates(sst_table_t *); -#endif #define SPEEDSTEP_MAX_POWER_YONAH 31000 #define SPEEDSTEP_MIN_POWER_YONAH 13100 diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 54b2f54..d4f3232 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -51,7 +51,6 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) return lapic_read(LAPIC_ID) >> 24; } -#ifndef __ROMCC__ #if !CONFIG_AP_IN_SIPI_WAIT /* If we need to go back to sipi wait, we use the long non-inlined version of * this function in lapic_cpu_init.c @@ -155,6 +154,5 @@ int start_cpu(struct device *cpu); #endif /* !__PRE_RAM__ */ int boot_cpu(void); -#endif #endif /* CPU_X86_LAPIC_H */ diff --git a/src/include/delay.h b/src/include/delay.h index 0333879..676579b 100644 --- a/src/include/delay.h +++ b/src/include/delay.h @@ -1,8 +1,6 @@ #ifndef DELAY_H #define DELAY_H -#if !defined( __ROMCC__) - #if CONFIG_HAVE_INIT_TIMER void init_timer(void); #else @@ -12,6 +10,4 @@ void init_timer(void); void udelay(unsigned usecs); void mdelay(unsigned msecs); void delay(unsigned secs); - -#endif #endif /* DELAY_H */ diff --git a/src/include/ehci.h b/src/include/ehci.h index 29347f9..7ec9810 100644 --- a/src/include/ehci.h +++ b/src/include/ehci.h @@ -25,7 +25,6 @@ #define EHCI_BAR_INDEX 0x10 -#ifndef __ROMCC__ /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ /* Section 2.2 Host Controller Capability Registers */ @@ -201,4 +200,3 @@ struct ehci_dbg_port { #define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) } __attribute__ ((packed)); #endif -#endif diff --git a/src/include/ip_checksum.h b/src/include/ip_checksum.h index de26fa0..a1e0ffa 100644 --- a/src/include/ip_checksum.h +++ b/src/include/ip_checksum.h @@ -1,8 +1,5 @@ #ifndef IP_CHECKSUM_H #define IP_CHECKSUM_H - -#ifndef __ROMCC__ unsigned long compute_ip_checksum(void *addr, unsigned long length); unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new); -#endif #endif /* IP_CHECKSUM_H */ diff --git a/src/include/lib.h b/src/include/lib.h index 40c76f2..cb540a7 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -22,7 +22,6 @@ #ifndef __LIB_H__ #define __LIB_H__ #include <stdint.h> -#ifndef __ROMCC__ /* romcc doesn't support prototypes. */ #ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */ /* Defined in src/lib/clog2.c */ @@ -53,5 +52,4 @@ void cache_as_ram_main(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #endif -#endif /* __ROMCC__ */ #endif /* __LIB_H__ */ diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index f8e2b48..f4f0dca 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -58,7 +58,5 @@ #define PPCB_SPKR 0x02 /* Bit 1 */ #define PPCB_T2GATE 0x01 /* Bit 0 */ -#ifndef __ROMCC__ void setup_i8254(void); #endif -#endif diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index ee1473b..29e0348 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -203,9 +203,7 @@ static inline int get_option(void *dest __attribute__((unused)), #define CMOS_POST_BANK_1_MAGIC 0x81 #define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) -#if !defined(__ROMCC__) void cmos_post_log(void); -#endif #endif /* CONFIG_CMOS_POST */ #endif /* PC80_MC146818RTC_H */ diff --git a/src/include/reset.h b/src/include/reset.h index 79bf6d5..9f117db 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -1,9 +1,6 @@ #ifndef RESET_H #define RESET_H -#if !defined( __ROMCC__ ) -/* ROMCC can't do function prototypes... */ - #if CONFIG_HAVE_HARD_RESET void hard_reset(void); #else @@ -12,4 +9,3 @@ void hard_reset(void); void soft_reset(void); #endif -#endif diff --git a/src/include/uart.h b/src/include/uart.h index 6b8d8e8..9601bfa 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -30,7 +30,7 @@ #include <uart8250.h> #endif -#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); diff --git a/src/include/uart8250.h b/src/include/uart8250.h index d1164c5..d42e822 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -114,7 +114,6 @@ /* Line Control Settings */ #define UART_LCS CONFIG_TTYS0_LCS -#ifndef __ROMCC__ #if CONFIG_CONSOLE_SERIAL8250 unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); @@ -145,8 +144,6 @@ void oxford_init(void); #endif #endif -#endif /* __ROMCC__ */ - #endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ #endif /* UART8250_H */ diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index 8caf361..c3b3437 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -34,7 +34,6 @@ struct ehci_debug_info { u8 bufidx; }; -#ifndef __ROMCC__ void enable_usbdebug(unsigned int port); int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size); int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size); @@ -47,4 +46,3 @@ void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data); void usbdebug_tx_flush(struct ehci_debug_info *info); int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info); #endif -#endif diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h index df0e929..05c3889 100644 --- a/src/northbridge/intel/e7501/raminit.h +++ b/src/northbridge/intel/e7501/raminit.h @@ -15,8 +15,6 @@ struct mem_controller { uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; }; -#ifndef __ROMCC__ void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/i3100/raminit.h b/src/northbridge/intel/i3100/raminit.h index 03e1458..ea6c60f 100644 --- a/src/northbridge/intel/i3100/raminit.h +++ b/src/northbridge/intel/i3100/raminit.h @@ -30,8 +30,6 @@ struct mem_controller { u16 channel1[DIMM_SOCKETS]; }; -#ifndef __ROMCC__ void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif #endif diff --git a/src/southbridge/amd/cs5535/cs5535.h b/src/southbridge/amd/cs5535/cs5535.h index 0db7c17..0b43563 100644 --- a/src/southbridge/amd/cs5535/cs5535.h +++ b/src/southbridge/amd/cs5535/cs5535.h @@ -115,7 +115,7 @@ /* Flash Memory Mask values */ #define FLASH_MEM_4K 0xFFFFF000 -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cs5535_disable_internal_uart(void); #else diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index 84738a2..c193d9d 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -442,7 +442,7 @@ #define FLASH_IO_128B 0x0000FF80 #define FLASH_IO_256B 0x0000FF00 -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cs5536_setup_onchipuart(int uart); void cs5536_disable_internal_uart(void); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7f64571..3904866 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -56,7 +56,7 @@ void intel_pch_finalize_smm(void); #endif -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #if !defined(__SMM__) #include "chip.h" diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 76d5fc7..e6062c6 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,26 +21,19 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) #if !defined(__PRE_RAM__) -#if !defined(__ACPI__) /* dsdt include */ - #include <arch/io.h> #include <device/device.h> #include "chip.h" - void i82371eb_enable(device_t dev); void i82371eb_hard_reset(void); - -#endif -#endif -#endif - -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#else void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); void enable_pm(void); #endif +#endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the * 'reg' variable, otherwise it clears those bits. diff --git a/src/southbridge/intel/i82801ax/i82801ax.h b/src/southbridge/intel/i82801ax/i82801ax.h index ed15bba..f459f2f 100644 --- a/src/southbridge/intel/i82801ax/i82801ax.h +++ b/src/southbridge/intel/i82801ax/i82801ax.h @@ -24,9 +24,7 @@ #if !defined(__PRE_RAM__) #include "chip.h" void i82801ax_enable(device_t dev); -#endif - -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#else void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); #endif diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h index 202b41c..b2ee79c 100644 --- a/src/southbridge/intel/i82801bx/i82801bx.h +++ b/src/southbridge/intel/i82801bx/i82801bx.h @@ -26,7 +26,7 @@ extern void i82801bx_enable(device_t dev); #endif -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); #endif diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index dba5bd6..c7d7e77 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -31,7 +31,7 @@ #ifndef I82801DX_H #define I82801DX_H -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801dx_enable(device_t dev); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index b5df5d9..1064dde 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -37,7 +37,7 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7246739..21933b4 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -21,7 +21,6 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H - /* * Lynx Point PCH PCI Devices: * @@ -125,7 +124,7 @@ struct rcba_config_instruction u32 or_value; }; -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); int pch_silicon_type(void); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 5454d79..4fb3391 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -33,9 +33,7 @@ void mcp55_enable(device_t dev); extern struct pci_operations mcp55_pci_ops; #else -#if !defined(__ROMCC__) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif -#endif #endif diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h index 6c1e7e2..6085ab5 100644 --- a/src/southbridge/sis/sis966/sis966.h +++ b/src/southbridge/sis/sis966/sis966.h @@ -35,8 +35,6 @@ #define DEBUG_USB 0 #define DEBUG_USB2 0 -#if !defined(__ROMCC__) void sis966_enable(device_t dev); -#endif #endif /* SIS966_H */ diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index b43ce3c..3cca58d 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -145,7 +145,6 @@ __attribute__ ((packed)) #ifdef __PRE_RAM__ -#ifndef __ROMCC__ u8 smbus_read_byte(u8 dimm, u8 offset); void smbus_write_byte(u8 dimm, u8 offset, u8 data); void enable_smbus(void); @@ -155,7 +154,6 @@ void vt8237_sb_enable_fid_vid(void); void enable_rom_decode(void); void vt8237_early_spi_init(void); int vt8237_early_network_init(struct vt8237_network_rom *rom); -#endif #else void writeback(device_t dev, u16 where, u8 what); void dump_south(device_t dev); diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 0616c2a..5ec6188 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -35,11 +35,8 @@ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ -#ifndef __ROMCC__ void it8712f_kill_watchdog(void); void it8712f_enable_serial(device_t dev, u16 iobase); void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); #endif - -#endif diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index be9f720..6657db4 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -41,7 +41,7 @@ void init_ec(u16 base); #endif -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void it8716f_disable_dev(device_t dev); void it8716f_enable_dev(device_t dev, u16 iobase); void it8716f_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 4da5af5..527d1c2 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -33,7 +33,7 @@ #define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void it8718f_24mhz_clkin(void); void it8718f_disable_reboot(void); void it8718f_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h index cca404a..25300e6 100644 --- a/src/superio/ite/it8721f/it8721f.h +++ b/src/superio/ite/it8721f/it8721f.h @@ -32,7 +32,7 @@ #define IT8721F_GPIO 0x07 /* GPIO */ #define IT8721F_IR 0x0a /* Consumer IR */ -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void it8721f_24mhz_clkin(void); void it8721f_disable_reboot(void); void it8721f_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 343d9b3..f881d7a 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -105,7 +105,6 @@ #define GPIO_REG_ENABLE(x) (0xc0 + (x)) #define GPIO_REG_OUTPUT(x) (0xc8 + (x)) -#ifndef __ROMCC__ u8 it8772f_sio_read(u8 index); void it8772f_sio_write(u8 index, u8 value); void it8772f_enable_serial(device_t dev, u16 iobase); @@ -116,5 +115,3 @@ void it8772f_ac_resume_southbridge(void); void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup, u8 output, u8 enable); #endif - -#endif diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index 7208c8e..73c1fbc 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -114,7 +114,7 @@ #define PC87417_XSCNF 0x15 #define PC87417_XWBCNF 0x16 -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void pc87417_enable_serial(device_t dev, u16 iobase); void pc87417_enable_dev(device_t dev); #endif diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index deab7ce..c982603 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,7 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void w83627ehg_enable_dev(device_t dev, u16 iobase); void w83627ehg_disable_dev(device_t dev); void w83627ehg_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index 423ba8f..468cb55 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -113,7 +113,7 @@ #define W83627HF_XSCNF 0x15 #define W83627HF_XWBCNF 0x16 -#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) void w83627hf_disable_dev(device_t dev); void w83627hf_enable_dev(device_t dev, u16 iobase); void w83627hf_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 741d5b2..7e353e2 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -32,8 +32,5 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ -#ifndef __ROMCC__ void w83697hf_set_clksel_48(device_t); #endif - -#endif

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Patch set updated for coreboot: dca014e cbfs_core.c: make cfbs searches even less verbose
by Paul Menzel 07 May '13

07 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3208 -gerrit commit dca014e337c76fded0249246afb432eb58836def Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon May 6 15:51:39 2013 -0600 cbfs_core.c: make cfbs searches even less verbose The cbfs core code would print out the name of the file it is searching for and when it is found would print out the name again. This contributes to a lot of unnecessary messages in a functioning payload’s output. Change this message to a DEBUG one so that it will only be printed when CONFIG_DEBUG_CBFS is enabled. Change-Id: Ib238ff174bedba8eaaad8d1d452721fcac339b1a Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- payloads/libpayload/libcbfs/cbfs_core.c | 6 +++--- src/lib/cbfs_core.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 3fe6971..48a4b3a 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -123,7 +123,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) #endif DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); - LOG("Looking for '%s' starting from 0x%x.\n", name, offset); + DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media); while (offset < romsize && media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { @@ -150,7 +150,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) } else if (strcmp(file_name, name) == 0) { int file_offset = ntohl(file.offset), file_len = ntohl(file.len); - LOG("Found file (offset=0x%x, len=%d).\n", + DEBUG("Found file (offset=0x%x, len=%d).\n", offset + file_offset, file_len); media->unmap(media, file_name); file_ptr = media->map(media, offset, @@ -169,7 +169,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) offset += align - (offset % align); } media->close(media); - LOG("WARNING: Not found.\n"); + LOG("WARNING: '%s' not found.\n", name); return NULL; } diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 1220d48..852b37f 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -123,7 +123,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) #endif DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); - LOG("Looking for '%s' starting from 0x%x.\n", name, offset); + DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media); while (offset < romsize && media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { @@ -150,7 +150,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) } else if (strcmp(file_name, name) == 0) { int file_offset = ntohl(file.offset), file_len = ntohl(file.len); - LOG("Found file (offset=0x%x, len=%d).\n", + DEBUG("Found file (offset=0x%x, len=%d).\n", offset + file_offset, file_len); media->unmap(media, file_name); file_ptr = media->map(media, offset, @@ -169,7 +169,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) offset += align - (offset % align); } media->close(media); - LOG("WARNING: Not found.\n"); + LOG("WARNING: '%s' not found.\n", name); return NULL; }

1 0

Patch set updated for coreboot: 782c73d cbfs_core.c: make cfbs searches even less verbose
by Dave Frodin 07 May '13

07 May '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3208 -gerrit commit 782c73d0fee5f0ed8ef2df3bc734cad48da34e02 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon May 6 15:51:39 2013 -0600 cbfs_core.c: make cfbs searches even less verbose The cbfs core code would print out the name of the file it is searching for and when it is found would print out the name again. This contributes to a lot of unnecessary messages in a functioning payloads output. Change this message to a DEBUG one so that it will only be printed when CONFIG_DEBUG_CBFS is enabled. Change-Id: Ib238ff174bedba8eaaad8d1d452721fcac339b1a Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- payloads/libpayload/libcbfs/cbfs_core.c | 6 +++--- src/lib/cbfs_core.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 3fe6971..48a4b3a 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -123,7 +123,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) #endif DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); - LOG("Looking for '%s' starting from 0x%x.\n", name, offset); + DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media); while (offset < romsize && media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { @@ -150,7 +150,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) } else if (strcmp(file_name, name) == 0) { int file_offset = ntohl(file.offset), file_len = ntohl(file.len); - LOG("Found file (offset=0x%x, len=%d).\n", + DEBUG("Found file (offset=0x%x, len=%d).\n", offset + file_offset, file_len); media->unmap(media, file_name); file_ptr = media->map(media, offset, @@ -169,7 +169,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) offset += align - (offset % align); } media->close(media); - LOG("WARNING: Not found.\n"); + LOG("WARNING: '%s' not found.\n", name); return NULL; } diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 1220d48..852b37f 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -123,7 +123,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) #endif DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); - LOG("Looking for '%s' starting from 0x%x.\n", name, offset); + DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media); while (offset < romsize && media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { @@ -150,7 +150,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) } else if (strcmp(file_name, name) == 0) { int file_offset = ntohl(file.offset), file_len = ntohl(file.len); - LOG("Found file (offset=0x%x, len=%d).\n", + DEBUG("Found file (offset=0x%x, len=%d).\n", offset + file_offset, file_len); media->unmap(media, file_name); file_ptr = media->map(media, offset, @@ -169,7 +169,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) offset += align - (offset % align); } media->close(media); - LOG("WARNING: Not found.\n"); + LOG("WARNING: '%s' not found.\n", name); return NULL; }

1 0

Patch set updated for coreboot: af2e68f Intel BD82x6x: LPC: Unify I/O APIC setup
by Paul Menzel 07 May '13

07 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3183 -gerrit commit af2e68fd126409d695982ad0dfb37257d56098a0 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:23:39 2013 +0200 Intel BD82x6x: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/bd82x6x/lpc.c | 48 +++++++++++++------------------------ src/southbridge/intel/bd82x6x/pch.h | 1 + 2 files changed, 18 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7bcadc9..d878155 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -39,43 +39,29 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void pch_enable_ioapic(struct device *dev) { - int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); + /* Enable ACPI I/O range decode */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) @@ -538,7 +524,7 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7f64571..1137a6e 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -119,6 +119,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define PMBASE 0x40 #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */

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coreboot-gerrit May 2013