coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: abf28b6 AMD Brazos/Trinity boards: PlatformGnbPcie.c: Reserve correct amount of memory
by Paul Menzel 11 May '13

11 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3239 -gerrit commit abf28b656c3c3cbbae9ba371db127e234ca95b5a Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 10 09:23:42 2013 +0200 AMD Brazos/Trinity boards: PlatformGnbPcie.c: Reserve correct amount of memory In `PlatformGnbPcie.c` AGESA functions are used to reserve memory space to save the PCIe configuration to. This is the With the following definitions in `AGESA.h` $ more src/vendorcode/amd/agesa/f14/AGESA.h […] /// PCIe port descriptor typedef struct { IN UINT32 Flags; /**< Descriptor flags * @li @b Bit31 - last descriptor in complex */ IN PCIe_ENGINE_DATA EngineData; ///< Engine data IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info } PCIe_PORT_DESCRIPTOR; /// DDI descriptor typedef struct { IN UINT32 Flags; /**< Descriptor flags * @li @b Bit31 - last descriptor in complex */ IN PCIe_ENGINE_DATA EngineData; ///< Engine data IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info } PCIe_DDI_DESCRIPTOR; /// PCIe Complex descriptor typedef struct { IN UINT32 Flags; /**< Descriptor flags * @li @b Bit31 - last descriptor in topology */ IN UINT32 SocketId; ///< Socket Id IN PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). IN PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). IN VOID *Reserved; ///< Reserved for future use } PCIe_COMPLEX_DESCRIPTOR; […] memory has to be reserved for the `PCIe_COMPLEX_DESCRIPTOR` and, as two struct members are pointers to arrays with elements of type `PCIe_PORT_DESCRIPTOR` and `PCIe_DDI_DESCRIPTOR`, space for these times the number of array elements have to be reserved: a + b * 5 + c * 2. sizeof(PCIe_COMPLEX_DESCRIPTOR) + sizeof(PCIe_PORT_DESCRIPTOR) * 5 + sizeof(PCIe_DDI_DESCRIPTOR) * 2; But for whatever reason parentheses were put in there making this calculation incorrect and reserving too much memory. (a + b * 5 + c) * 2 So, remove the parentheses to reserve the exact amount of memory needed. Rudolf Marek made this change as part of his patch »ASUS F2A85-M: Correct and clean up PCIe config« [1]. Factor this hunk out as it affects all AMD Brazos and Trinity based boards. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I32e8c8a3dfc5e87eb119eb17719d612e57e0817a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 4 ++-- src/mainboard/amd/parmer/PlatformGnbPcie.c | 6 +++--- src/mainboard/amd/persimmon/PlatformGnbPcie.c | 4 ++-- src/mainboard/amd/south_station/PlatformGnbPcie.c | 6 +++--- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 6 +++--- src/mainboard/amd/torpedo/PlatformGnbPcie.c | 6 +++--- src/mainboard/amd/union_station/PlatformGnbPcie.c | 6 +++--- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 6 +++--- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 6 +++--- src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c | 4 ++-- src/mainboard/lippert/toucan-af/PlatformGnbPcie.c | 4 ++-- 11 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index 0eea211..ac5eca3 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -108,9 +108,9 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + sizeof (PCIe_DDI_DESCRIPTOR) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index f4382a1..6df9c6d 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -138,9 +138,9 @@ OemCustomizeInitEarly ( /* */ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ /* */ - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 3; + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + + sizeof (PCIe_DDI_DESCRIPTOR) * 3; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 14839c7..fa909d2 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -117,9 +117,9 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + sizeof (PCIe_DDI_DESCRIPTOR) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index ee66532..d0fd71b 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -116,9 +116,9 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + sizeof (PCIe_DDI_DESCRIPTOR) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index 153b13d..2aee86e 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -137,9 +137,9 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 3; + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + + sizeof (PCIe_DDI_DESCRIPTOR) * 3; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index 459a342..a42d056 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -126,9 +126,9 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + + sizeof (PCIe_DDI_DESCRIPTOR) * 6; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index 8b100dc..98dd995 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -118,9 +118,9 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + sizeof (PCIe_DDI_DESCRIPTOR) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index cef3e37..ee25ac9 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -118,9 +118,9 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + sizeof (PCIe_DDI_DESCRIPTOR) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 8ee6707..9fed750 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -159,9 +159,9 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 6; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c index e9e482d..9bd9958 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c @@ -117,9 +117,9 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + sizeof (PCIe_DDI_DESCRIPTOR) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c index ea59c44..772ea53 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c @@ -117,9 +117,9 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + sizeof (PCIe_DDI_DESCRIPTOR) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE;

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Patch merged into coreboot/master: c1ef740 haswell: Fix VGA option rom INT15 handler
by gerrit＠coreboot.org 11 May '13

11 May '13

the following patch was just integrated into master: commit c1ef740d88ea88c4ec7ef5449bd8d348fc15a9a2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Apr 23 08:39:19 2013 -0700 haswell: Fix VGA option rom INT15 handler The format of this function changed but was not updated in all mainboards. This fixes BaskingRidge and WTM2. The int15 handler no longer takes a regs structure as an argument and instead uses global variables. The yabel interface is now similar enough that we can drop the duplicate handler. Change-Id: Ia717ae14f99cee6d83ccdb1e26b9d7defe1638c4 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48896 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/3230 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3230 for details. -gerrit

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Patch set updated for coreboot: 60b691d Simplify and repair the cmos.default handling.
by Stefan Reinauer 10 May '13

10 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3223 -gerrit commit 60b691d2e722ae4e55b87f81f721c719b498066a Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 22:19:17 2013 +0200 Simplify and repair the cmos.default handling. Without that fix we have: make: *** No rule to make target `nvramtool', needed by `build/coreboot.pre1'. Stop. This commit was tested on the Asus M4A785T-M with the following commit: Asus M4A785T-M: Add CMOS defaults. Change-Id: I548005a58f430ed7b6da5249a24bbdcae440a1e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- Makefile.inc | 8 -------- src/drivers/pc80/Makefile.inc | 10 ++++++++-- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index da350d1..71acc87 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -142,14 +142,6 @@ $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h endef ####################################################################### -# Parse plaintext cmos defaults into binary format -# arg1: source file -# arg2: binary file name -cbfs-files-processor-nvramtool= \ - $(eval $(2): $(1) $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout | $(objutil)/nvramtool/nvramtool ; \ - printf " CREATE $(2) (from $(1))\n"; $(objutil)/nvramtool/nvramtool -y $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout -D $(2).tmp -p $(1) && mv $(2).tmp $(2)) - -####################################################################### # Link VSA binary to ELF-ish stage # arg1: source file # arg2: binary file name diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index 23e986a..9c77a7a 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -9,11 +9,17 @@ romstage-$(CONFIG_TPM) += tpm.c romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c subdirs-y += vga -cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default -cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool +ifeq ($(CONFIG_HAVE_CMOS_DEFAULT),y) +cbfs-files-y += cmos.default +cmos.default-file = $(obj)/cmos.default.bin cmos.default-type = 0xaa +endif smm-y += mc146818rtc.c $(obj)/drivers/pc80/mc146818rtc.ramstage.o : $(obj)/build.h $(obj)/drivers/pc80/mc146818rtc.smm.o : $(obj)/build.h + +$(obj)/cmos.default.bin: $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout $(NVRAMTOOL) + @printf " OPTION $(subst $(obj)/,,$(@))\n" + $(NVRAMTOOL) -y $< -D $@.tmp -p $< && mv $@.tmp $@

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New patch to review for coreboot: 35bac68 EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1.
by Ronald G. Minnich 10 May '13

10 May '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3238 -gerrit commit 35bac6837e90dd98083ababc57e36c5963c79f5f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri May 10 22:18:09 2013 +0200 EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1. build-snow got broken when the snow makefile improved. So fix it. While we're at it, create a script like the update-microcode scripts that gets the bl1. I thought about making this a common script but the various names and paths always evolve, leaving me thinking it's not worth it. This script is just a piece of the snow build script. Change-Id: I65c0f8697a978c62fe12533c4f0152d14dbaefda Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/update-bl1.sh | 26 ++++++++++++++++++++++++++ src/vendorcode/google/chromeos/build-snow | 21 ++++----------------- 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/src/cpu/samsung/exynos5250/update-bl1.sh b/src/cpu/samsung/exynos5250/update-bl1.sh new file mode 100644 index 0000000..e47b25d --- /dev/null +++ b/src/cpu/samsung/exynos5250/update-bl1.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +BL1_NAME="E5250.nbl1.bin" +BL1_PATH="3rdparty/cpu/samsung/exynos5250/" +BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exyn…" + +get_bl1() { + mkdir -p "${BL1_PATH}" + cd "${BL1_PATH}" + wget "${BL1_URL}" -O bl1.tbz2 + tar jxvf bl1.tbz2 + mv "exynos-pre-boot/firmware/${BL1_NAME}" . + rm -rf exynos-pre-boot + if [ ! -e "${BL1_NAME}" ]; then + echo "Error getting BL1" + fi +} + +main() { + if [ ! -e ${BL1_PATH}/${BL1_NAME} ]; then + get_bl1 + fi +} + +set -e +main "$@" diff --git a/src/vendorcode/google/chromeos/build-snow b/src/vendorcode/google/chromeos/build-snow index a749ba5..da1566b 100755 --- a/src/vendorcode/google/chromeos/build-snow +++ b/src/vendorcode/google/chromeos/build-snow @@ -44,29 +44,16 @@ get_bl1() { fi } -merge_bl1() { - local outfile="$1" - local bl1="${BL1_PATH}/${BL1_NAME}" - - if [ ! -e "$bl1" ]; then - get_bl1 - fi - - # use the new BL1 which supports 30KB BL2/SPL/Coreboot - local size="$(stat -c "%s" "$outfile")" - local bl1_size="$(stat -c "%s" "$bl1")" - - [ "$bl1_size" = "$((0x2000))" ] || die "Incorrect BL1 input file." - dd if="$bl1" of=${outfile} conv=notrunc -} - is_servod_ready() { ps -C servod >/dev/null 2>&1 } main() { + if [ ! -e "$bl1" ]; then + get_bl1 + fi + make - merge_bl1 "$OUTPUT" create_diff_192k "$OUTPUT" "$TMP_DIFF" echo "OK: Generated image (with BL1) in $OUTPUT" if is_servod_ready; then

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New patch to review for coreboot: 9ead000 Make early x86 POST codes written to IO port optional
by Martin Roth 10 May '13

10 May '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3237 -gerrit commit 9ead000e548f4ddac8b00f7389b52b5644df1f00 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri May 10 13:40:29 2013 -0600 Make early x86 POST codes written to IO port optional This continues the work done in patch 6b908d08ab http://review.coreboot.org/#/c/1685/ and makes the early x86 post codes follow the same options. Change-Id: Idf0c17b27b3516e79a9a53048bc203245f7c18ff Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/include/cpu/x86/post_code.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h index 20b87c6..7465f62 100644 --- a/src/include/cpu/x86/post_code.h +++ b/src/include/cpu/x86/post_code.h @@ -1,7 +1,12 @@ #include <console/post_codes.h> + +#if CONFIG_IO_POST #define post_code(value) \ movb $value, %al; \ - outb %al, $0x80 + outb %al, $CONFIG_IO_POST_PORT +#else +#define post_code(value) +#endif

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Patch merged into coreboot/master: ec664bc romcc: support attribute((packed))
by gerrit＠coreboot.org 10 May '13

10 May '13

the following patch was just integrated into master: commit ec664bcfa4ac3151f58853565b930b20b61b1bdd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 9 14:06:04 2013 -0700 romcc: support attribute((packed)) right now this is just a fake option to get rid of ifdefs in coreboot's code. Change-Id: I59233f3c1d266b4e716a5921e9db298c7f96751d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/3225 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/3225 for details. -gerrit

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Patch merged into coreboot/master: 711a6fd Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary
by gerrit＠coreboot.org 10 May '13

10 May '13

the following patch was just integrated into master: commit 711a6fde0db2f7a0c388fc97faec1013caaa2789 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri May 3 18:25:27 2013 +0200 Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary This option has never had much if any use. It solved a problem over 10 years ago that resulted from an argument over the value or lack thereof of including all the debug strings in a coreboot image. The answer is in: it's a good idea to maintain the capability to print all messages, for many reasons. This option is also misleading people, as in a recent discussion, to believe that log messges are controlled at build time in a way they are not. For the record, from this day forward, we can print messages at all log levels and the default log level is set at boot time, as directed by DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and if you are having trouble override it in CMOS and get more messages. Besides, a quick glance shows it's always set to max (9 in this case) in the very few cases (1) in which it is set. Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/3188 Tested-by: build bot (Jenkins) See http://review.coreboot.org/3188 for details. -gerrit

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Patch merged into coreboot/master: c5e036a Get rid of a number of __GNUC__ checks
by gerrit＠coreboot.org 10 May '13

10 May '13

the following patch was just integrated into master: commit c5e036a04368186fe73925c6fb101c594513391c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 9 14:33:14 2013 -0700 Get rid of a number of __GNUC__ checks In the process of streamlining coreboot code and getting rid of unneeded ifdefs, drop a number of unneeded checks for the GNU C compiler. This also cleans up x86emu/types.h significantly by dropping all the duplicate types in there. Change-Id: I0bf289e149ed02e5170751c101adc335b849a410 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/3226 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/3226 for details. -gerrit

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Patch merged into coreboot/master: b8b3e8b Asus M4A785T-M: Add CMOS defaults.
by gerrit＠coreboot.org 10 May '13

10 May '13

the following patch was just integrated into master: commit b8b3e8bff32ee7dddcacec11e015f6683783eb2f Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 16:14:59 2013 +0200 Asus M4A785T-M: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Enable baud_rate = 115200 hw_scrubber = Enable interleave_chip_selects = Enable max_mem_clock = 400Mhz multi_core = Enable power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0xc slow_cpu = off nmi = Enable iommu = Enable nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide. nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Ifa09c7a468e3e0713b426763266ae633e67d8397 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: http://review.coreboot.org/3224 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3224 for details. -gerrit

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Patch merged into coreboot/master: e04dc75 AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h
by gerrit＠coreboot.org 10 May '13

10 May '13

the following patch was just integrated into master: commit e04dc7529fdeb2730b826b687fc365e9720d6647 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Mon Apr 15 17:11:19 2013 +0800 AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE, GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used. Change-Id: I5c7b7d45880367dba452ebcd4f01fbd0c15aac22 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Reviewed-on: http://review.coreboot.org/3087 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/3087 for details. -gerrit

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coreboot-gerrit May 2013