coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: a02998e sconfig: Refuse devicetree with leaf "chip"s
by Patrick Georgi 03 May '13

03 May '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3189 -gerrit commit a02998e9c2528fdaa55a33b75d4360eede1f260f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri May 3 20:31:56 2013 +0200 sconfig: Refuse devicetree with leaf "chip"s It doesn't make sense to have a chip without any containing device in the device tree, and it creates lots of funny issues when trying to make use of such a tree (ask Ron). Since the right thing is to refuse such devicetrees, this change makes them a syntax error. Change-Id: Ia35b518bd4acd631e78bdf63c4424c0fa6a81229 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/sconfig/sconfig.tab.c_shipped | 86 +++++++++++++++++++------------------- util/sconfig/sconfig.y | 2 +- 2 files changed, 45 insertions(+), 43 deletions(-) diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 3a56ac8..cd5d628 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -387,7 +387,7 @@ union yyalloc /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 37 +#define YYLAST 41 /* YYNTOKENS -- Number of terminals. */ #define YYNTOKENS 28 @@ -396,7 +396,7 @@ union yyalloc /* YYNRULES -- Number of rules. */ #define YYNRULES 22 /* YYNRULES -- Number of states. */ -#define YYNSTATES 41 +#define YYNSTATES 42 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ #define YYUNDEFTOK 2 @@ -444,22 +444,22 @@ static const yytype_uint8 yytranslate[] = YYRHS. */ static const yytype_uint8 yyprhs[] = { - 0, 0, 3, 4, 7, 10, 13, 16, 17, 20, - 23, 26, 29, 32, 33, 34, 40, 41, 49, 54, - 59, 63, 68 + 0, 0, 3, 4, 7, 10, 12, 15, 18, 21, + 24, 27, 30, 33, 34, 35, 41, 42, 50, 55, + 60, 64, 69 }; /* YYRHS -- A `-1'-separated list of the rules' RHS. */ static const yytype_int8 yyrhs[] = { 29, 0, -1, -1, 30, 33, -1, 31, 35, -1, - 31, 33, -1, 31, 38, -1, -1, 32, 35, -1, - 32, 33, -1, 32, 37, -1, 32, 39, -1, 32, - 40, -1, -1, -1, 3, 12, 34, 31, 9, -1, - -1, 4, 7, 22, 6, 36, 32, 9, -1, 8, - 22, 10, 22, -1, 5, 12, 10, 12, -1, 23, - 22, 22, -1, 23, 22, 22, 24, -1, 25, 22, - 27, 22, -1 + 35, -1, 31, 33, -1, 31, 38, -1, 32, 35, + -1, 32, 33, -1, 32, 37, -1, 32, 39, -1, + 32, 40, -1, -1, -1, 3, 12, 34, 31, 9, + -1, -1, 4, 7, 22, 6, 36, 32, 9, -1, + 8, 22, 10, 22, -1, 5, 12, 10, 12, -1, + 23, 22, 22, -1, 23, 22, 22, 24, -1, 25, + 22, 27, 22, -1 }; /* YYRLINE[YYN] -- source line where rule number YYN was defined. */ @@ -507,7 +507,7 @@ static const yytype_uint8 yyr1[] = /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ static const yytype_uint8 yyr2[] = { - 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, + 0, 2, 0, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0, 5, 0, 7, 4, 4, 3, 4, 4 }; @@ -517,37 +517,37 @@ static const yytype_uint8 yyr2[] = means the default is an error. */ static const yytype_uint8 yydefact[] = { - 2, 0, 0, 1, 0, 3, 14, 7, 0, 0, - 0, 15, 5, 4, 6, 0, 0, 0, 0, 16, - 19, 13, 0, 0, 17, 0, 0, 9, 8, 10, - 11, 12, 0, 0, 0, 0, 20, 0, 18, 21, - 22 + 2, 0, 0, 1, 0, 3, 14, 0, 0, 0, + 5, 0, 0, 15, 6, 4, 7, 0, 0, 16, + 0, 13, 19, 0, 0, 17, 0, 0, 9, 8, + 10, 11, 12, 0, 0, 0, 0, 20, 0, 18, + 21, 22 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { - -1, 1, 2, 8, 22, 5, 7, 13, 21, 29, - 14, 30, 31 + -1, 1, 2, 9, 23, 5, 7, 10, 21, 30, + 16, 31, 32 }; /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing STATE-NUM. */ -#define YYPACT_NINF -9 +#define YYPACT_NINF -8 static const yytype_int8 yypact[] = { - -9, 3, 1, -9, -2, -9, -9, -9, 4, 5, - -1, -9, -9, -9, -9, -8, 7, 9, 6, -9, - -9, -9, -3, 2, -9, 8, 10, -9, -9, -9, - -9, -9, 11, 12, -4, 13, -5, 14, -9, -9, - -9 + -8, 10, 1, -8, -1, -8, -8, 8, 7, 4, + -8, -4, 3, -8, -8, -8, -8, 13, 11, -8, + 12, -8, -8, -3, 5, -8, 6, 9, -8, -8, + -8, -8, -8, 15, 14, 2, 16, 17, 18, -8, + -8, -8 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -9, -9, -9, -9, -9, -6, -9, 15, -9, -9, - -9, -9, -9 + -8, -8, -8, -8, -8, -7, -8, -6, -8, -8, + -8, -8, -8 }; /* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If @@ -556,35 +556,37 @@ static const yytype_int8 yypgoto[] = #define YYTABLE_NINF -1 static const yytype_uint8 yytable[] = { - 4, 9, 12, 3, 4, 23, 24, 4, 9, 10, - 6, 16, 15, 11, 17, 19, 27, 18, 20, 39, - 25, 35, 26, 37, 32, 0, 0, 0, 0, 0, - 33, 0, 34, 0, 36, 38, 40, 28 + 4, 8, 14, 15, 4, 24, 25, 4, 8, 12, + 3, 6, 8, 13, 11, 18, 28, 29, 17, 19, + 26, 20, 27, 0, 22, 36, 0, 33, 34, 38, + 0, 35, 0, 0, 0, 0, 37, 0, 39, 0, + 41, 40 }; #define yypact_value_is_default(yystate) \ - ((yystate) == (-9)) + ((yystate) == (-8)) #define yytable_value_is_error(yytable_value) \ YYID (0) static const yytype_int8 yycheck[] = { - 3, 4, 8, 0, 3, 8, 9, 3, 4, 5, - 12, 12, 7, 9, 22, 6, 22, 10, 12, 24, - 23, 10, 25, 27, 22, -1, -1, -1, -1, -1, - 22, -1, 22, -1, 22, 22, 22, 22 + 3, 4, 9, 9, 3, 8, 9, 3, 4, 5, + 0, 12, 4, 9, 7, 12, 23, 23, 22, 6, + 23, 10, 25, -1, 12, 10, -1, 22, 22, 27, + -1, 22, -1, -1, -1, -1, 22, -1, 22, -1, + 22, 24 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 29, 30, 0, 3, 33, 12, 34, 31, 4, - 5, 9, 33, 35, 38, 7, 12, 22, 10, 6, - 12, 36, 32, 8, 9, 23, 25, 33, 35, 37, - 39, 40, 22, 22, 22, 10, 22, 27, 22, 24, - 22 + 0, 29, 30, 0, 3, 33, 12, 34, 4, 31, + 35, 7, 5, 9, 33, 35, 38, 22, 12, 6, + 10, 36, 12, 32, 8, 9, 23, 25, 33, 35, + 37, 39, 40, 22, 22, 22, 10, 22, 27, 22, + 24, 22 }; #define yyerrok (yyerrstatus = 0) diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 8ea702e..70286d1 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -34,7 +34,7 @@ static struct device *cur_parent, *cur_bus; %% devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ; -chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; +chipchildren: chipchildren device | device | chipchildren chip | chipchildren registers ; devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | /* empty */ ;

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Patch set updated for coreboot: e093b07 Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary.
by Ronald G. Minnich 03 May '13

03 May '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3188 -gerrit commit e093b075359576f1220daa7433525ddf6074a723 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri May 3 18:25:27 2013 +0200 Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary. This option has never had much if any use. It solved a problem over 10 years ago that resulted from an argument over the value or lack thereof of including all the debug strings in a coreboot image. The answer is in: it's a good idea to maintain the capabilty to print all messages, for many reasons. This option is also misleading people, as in a recent discussion, to believe that log messges are controlled at build time in a way they are not. For the record, from this day forward, we can print messages at all log levels and the default log level is set at boot time, as directed by DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and if you are having trouble override it in CMOS and get more messages. Besides, a quick glance shows it's always set to max (9 in this case) in the very few cases (1) in which it is set. Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- documentation/LinuxBIOS-AMD64.tex | 5 --- src/console/Kconfig | 79 ---------------------------------- src/include/console/console.h | 10 +---- src/mainboard/msi/ms9652_fam10/Kconfig | 4 -- util/abuild/abuild | 2 - 5 files changed, 2 insertions(+), 98 deletions(-) diff --git a/documentation/LinuxBIOS-AMD64.tex b/documentation/LinuxBIOS-AMD64.tex index 19a6f59..5847dab 100644 --- a/documentation/LinuxBIOS-AMD64.tex +++ b/documentation/LinuxBIOS-AMD64.tex @@ -408,11 +408,6 @@ machine. Use new \textit{chip\_configure} method for configuring (nonpci) devices. Set to \texttt{1} for all AMD64 mainboards. -\item \begin{verbatim}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL\end{verbatim} - -Errors or log messages up to this level can be printed. Default is -\texttt{8}, minimum is \texttt{0}, maximum is \texttt{10}. - \item \begin{verbatim}CONFIG_DEFAULT_CONSOLE_LOGLEVEL\end{verbatim} Console will log at this level unless changed. Default is \texttt{7}, diff --git a/src/console/Kconfig b/src/console/Kconfig index 6251589..a613477 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -250,119 +250,40 @@ config CONSOLE_CAR_BUFFER_SIZE in the DCACHE based RAM to keep console output before it can be saved in a CBMEM buffer. 3K bytes should be enough even for the BIOS_SPEW level. - - -choice - prompt "Maximum console log level" - default MAXIMUM_CONSOLE_LOGLEVEL_8 - -config MAXIMUM_CONSOLE_LOGLEVEL_8 - bool "8: SPEW" - help - Way too many details. -config MAXIMUM_CONSOLE_LOGLEVEL_7 - bool "7: DEBUG" - help - Debug-level messages. -config MAXIMUM_CONSOLE_LOGLEVEL_6 - bool "6: INFO" - help - Informational messages. -config MAXIMUM_CONSOLE_LOGLEVEL_5 - bool "5: NOTICE" - help - Normal but significant conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_4 - bool "4: WARNING" - help - Warning conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_3 - bool "3: ERR" - help - Error conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_2 - bool "2: CRIT" - help - Critical conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_1 - bool "1: ALERT" - help - Action must be taken immediately. -config MAXIMUM_CONSOLE_LOGLEVEL_0 - bool "0: EMERG" - help - System is unusable. - -endchoice - -config MAXIMUM_CONSOLE_LOGLEVEL - int - default 0 if MAXIMUM_CONSOLE_LOGLEVEL_0 - default 1 if MAXIMUM_CONSOLE_LOGLEVEL_1 - default 2 if MAXIMUM_CONSOLE_LOGLEVEL_2 - default 3 if MAXIMUM_CONSOLE_LOGLEVEL_3 - default 4 if MAXIMUM_CONSOLE_LOGLEVEL_4 - default 5 if MAXIMUM_CONSOLE_LOGLEVEL_5 - default 6 if MAXIMUM_CONSOLE_LOGLEVEL_6 - default 7 if MAXIMUM_CONSOLE_LOGLEVEL_7 - default 8 if MAXIMUM_CONSOLE_LOGLEVEL_8 - help - Map the log level config names to an integer. - choice prompt "Default console log level" default DEFAULT_CONSOLE_LOGLEVEL_8 config DEFAULT_CONSOLE_LOGLEVEL_8 bool "8: SPEW" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8) help Way too many details. config DEFAULT_CONSOLE_LOGLEVEL_7 bool "7: DEBUG" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7) help Debug-level messages. config DEFAULT_CONSOLE_LOGLEVEL_6 bool "6: INFO" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6) help Informational messages. config DEFAULT_CONSOLE_LOGLEVEL_5 bool "5: NOTICE" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5) help Normal but significant conditions. config DEFAULT_CONSOLE_LOGLEVEL_4 bool "4: WARNING" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4) help Warning conditions. config DEFAULT_CONSOLE_LOGLEVEL_3 bool "3: ERR" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4 || MAXIMUM_CONSOLE_LOGLEVEL_3) help Error conditions. config DEFAULT_CONSOLE_LOGLEVEL_2 bool "2: CRIT" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4 || MAXIMUM_CONSOLE_LOGLEVEL_3 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_2) help Critical conditions. config DEFAULT_CONSOLE_LOGLEVEL_1 bool "1: ALERT" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4 || MAXIMUM_CONSOLE_LOGLEVEL_3 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_2 || MAXIMUM_CONSOLE_LOGLEVEL_1) help Action must be taken immediately. config DEFAULT_CONSOLE_LOGLEVEL_0 diff --git a/src/include/console/console.h b/src/include/console/console.h index d320093..031c25d 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -104,20 +104,14 @@ static inline void printk(int LEVEL, const char *fmt, ...) { #define printk(LEVEL, fmt, args...) \ do { \ - if (CONFIG_MAXIMUM_CONSOLE_LOGLEVEL >= LEVEL) { \ - do_printk(LEVEL, fmt, ##args); \ - } \ + do_printk(LEVEL, fmt, ##args); \ } while(0) #else #define printk(LEVEL, fmt, args...) \ do { \ - if (CONFIG_MAXIMUM_CONSOLE_LOGLEVEL >= LEVEL) { \ - do_printk(LEVEL, fmt, ##args); \ - } else { \ - do_printk(BIOS_NEVER, fmt, ##args); \ - } \ + do_printk(LEVEL, fmt, ##args); \ } while(0) #endif diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 852efd4..58cafa2 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -97,10 +97,6 @@ config DEFAULT_CONSOLE_LOGLEVEL int default 9 -config MAXIMUM_CONSOLE_LOGLEVEL - int - default 9 - config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default y diff --git a/util/abuild/abuild b/util/abuild/abuild index 1c69eec..aad066c 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -596,8 +596,6 @@ while true ; do -C|--config) shift; configureonly=1;; -l|--loglevel) shift customizing="${customizing}, loglevel $1" - configoptions="${configoptions}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$1=y\n" - configoptions="${configoptions}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$1\n" configoptions="${configoptions}CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$1=y\n" configoptions="${configoptions}CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$1\n" shift;;

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New patch to review for coreboot: 8cac2c5 Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary.
by Ronald G. Minnich 03 May '13

03 May '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3188 -gerrit commit 8cac2c5658930441158638db1f7d692f82201fe3 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri May 3 18:25:27 2013 +0200 Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary. This option has never had much if any use. It solved a problem over 10 years ago that resulted from an argument over the value or lack thereof of including all the debug strings in a coreboot image. The answer is in: it's a good idea to maintain the capabilty of print all messages, for many reasons. It's also misleading people, as in a recent discussion, to believe that log messges are controlled at build time in a way they are not. For the record, from this day forward, we can print messages at all log levels and the maximum log level is set at boot time, as directed by DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 and if you are having trouble override it in CMOS and get more messages.. Besides, a quick glance shows it's always set to max (9 in this case) in the very few cases (1) in which it is set. Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- documentation/LinuxBIOS-AMD64.tex | 5 --- src/console/Kconfig | 79 ---------------------------------- src/include/console/console.h | 10 +---- src/mainboard/msi/ms9652_fam10/Kconfig | 4 -- util/abuild/abuild | 2 - 5 files changed, 2 insertions(+), 98 deletions(-) diff --git a/documentation/LinuxBIOS-AMD64.tex b/documentation/LinuxBIOS-AMD64.tex index 19a6f59..5847dab 100644 --- a/documentation/LinuxBIOS-AMD64.tex +++ b/documentation/LinuxBIOS-AMD64.tex @@ -408,11 +408,6 @@ machine. Use new \textit{chip\_configure} method for configuring (nonpci) devices. Set to \texttt{1} for all AMD64 mainboards. -\item \begin{verbatim}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL\end{verbatim} - -Errors or log messages up to this level can be printed. Default is -\texttt{8}, minimum is \texttt{0}, maximum is \texttt{10}. - \item \begin{verbatim}CONFIG_DEFAULT_CONSOLE_LOGLEVEL\end{verbatim} Console will log at this level unless changed. Default is \texttt{7}, diff --git a/src/console/Kconfig b/src/console/Kconfig index 6251589..a613477 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -250,119 +250,40 @@ config CONSOLE_CAR_BUFFER_SIZE in the DCACHE based RAM to keep console output before it can be saved in a CBMEM buffer. 3K bytes should be enough even for the BIOS_SPEW level. - - -choice - prompt "Maximum console log level" - default MAXIMUM_CONSOLE_LOGLEVEL_8 - -config MAXIMUM_CONSOLE_LOGLEVEL_8 - bool "8: SPEW" - help - Way too many details. -config MAXIMUM_CONSOLE_LOGLEVEL_7 - bool "7: DEBUG" - help - Debug-level messages. -config MAXIMUM_CONSOLE_LOGLEVEL_6 - bool "6: INFO" - help - Informational messages. -config MAXIMUM_CONSOLE_LOGLEVEL_5 - bool "5: NOTICE" - help - Normal but significant conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_4 - bool "4: WARNING" - help - Warning conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_3 - bool "3: ERR" - help - Error conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_2 - bool "2: CRIT" - help - Critical conditions. -config MAXIMUM_CONSOLE_LOGLEVEL_1 - bool "1: ALERT" - help - Action must be taken immediately. -config MAXIMUM_CONSOLE_LOGLEVEL_0 - bool "0: EMERG" - help - System is unusable. - -endchoice - -config MAXIMUM_CONSOLE_LOGLEVEL - int - default 0 if MAXIMUM_CONSOLE_LOGLEVEL_0 - default 1 if MAXIMUM_CONSOLE_LOGLEVEL_1 - default 2 if MAXIMUM_CONSOLE_LOGLEVEL_2 - default 3 if MAXIMUM_CONSOLE_LOGLEVEL_3 - default 4 if MAXIMUM_CONSOLE_LOGLEVEL_4 - default 5 if MAXIMUM_CONSOLE_LOGLEVEL_5 - default 6 if MAXIMUM_CONSOLE_LOGLEVEL_6 - default 7 if MAXIMUM_CONSOLE_LOGLEVEL_7 - default 8 if MAXIMUM_CONSOLE_LOGLEVEL_8 - help - Map the log level config names to an integer. - choice prompt "Default console log level" default DEFAULT_CONSOLE_LOGLEVEL_8 config DEFAULT_CONSOLE_LOGLEVEL_8 bool "8: SPEW" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8) help Way too many details. config DEFAULT_CONSOLE_LOGLEVEL_7 bool "7: DEBUG" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7) help Debug-level messages. config DEFAULT_CONSOLE_LOGLEVEL_6 bool "6: INFO" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6) help Informational messages. config DEFAULT_CONSOLE_LOGLEVEL_5 bool "5: NOTICE" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5) help Normal but significant conditions. config DEFAULT_CONSOLE_LOGLEVEL_4 bool "4: WARNING" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4) help Warning conditions. config DEFAULT_CONSOLE_LOGLEVEL_3 bool "3: ERR" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4 || MAXIMUM_CONSOLE_LOGLEVEL_3) help Error conditions. config DEFAULT_CONSOLE_LOGLEVEL_2 bool "2: CRIT" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4 || MAXIMUM_CONSOLE_LOGLEVEL_3 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_2) help Critical conditions. config DEFAULT_CONSOLE_LOGLEVEL_1 bool "1: ALERT" - depends on (MAXIMUM_CONSOLE_LOGLEVEL_8 || MAXIMUM_CONSOLE_LOGLEVEL_7 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_6 || MAXIMUM_CONSOLE_LOGLEVEL_5 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_4 || MAXIMUM_CONSOLE_LOGLEVEL_3 ||\ - MAXIMUM_CONSOLE_LOGLEVEL_2 || MAXIMUM_CONSOLE_LOGLEVEL_1) help Action must be taken immediately. config DEFAULT_CONSOLE_LOGLEVEL_0 diff --git a/src/include/console/console.h b/src/include/console/console.h index d320093..031c25d 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -104,20 +104,14 @@ static inline void printk(int LEVEL, const char *fmt, ...) { #define printk(LEVEL, fmt, args...) \ do { \ - if (CONFIG_MAXIMUM_CONSOLE_LOGLEVEL >= LEVEL) { \ - do_printk(LEVEL, fmt, ##args); \ - } \ + do_printk(LEVEL, fmt, ##args); \ } while(0) #else #define printk(LEVEL, fmt, args...) \ do { \ - if (CONFIG_MAXIMUM_CONSOLE_LOGLEVEL >= LEVEL) { \ - do_printk(LEVEL, fmt, ##args); \ - } else { \ - do_printk(BIOS_NEVER, fmt, ##args); \ - } \ + do_printk(LEVEL, fmt, ##args); \ } while(0) #endif diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 852efd4..58cafa2 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -97,10 +97,6 @@ config DEFAULT_CONSOLE_LOGLEVEL int default 9 -config MAXIMUM_CONSOLE_LOGLEVEL - int - default 9 - config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default y diff --git a/util/abuild/abuild b/util/abuild/abuild index 1c69eec..aad066c 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -596,8 +596,6 @@ while true ; do -C|--config) shift; configureonly=1;; -l|--loglevel) shift customizing="${customizing}, loglevel $1" - configoptions="${configoptions}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$1=y\n" - configoptions="${configoptions}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$1\n" configoptions="${configoptions}CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$1=y\n" configoptions="${configoptions}CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$1\n" shift;;

1 0

Patch merged into coreboot/master: 2fde966 exynos5250/snow: deprecate time.h
by gerrit＠coreboot.org 03 May '13

03 May '13

the following patch was just integrated into master: commit 2fde9668b47e74d1bfad2f1688a4481e6b966d04 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu May 2 16:47:54 2013 -0700 exynos5250/snow: deprecate time.h time.h We Hardly Knew Ye. This deprecates time.h which is currently only used by Exynos5250 and Snow. The original idea was to try and unify some of the various timer interfaces and has been supplanted by the monotonic timer API. timer_us() is now obsolete. timer_start() is now mct_start() and is exposed in exynos5250/clk.h. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I14ebf75649d101491252c9aafea12f73ccf446b5 Reviewed-on: http://review.coreboot.org/3177 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri May 3 05:47:46 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri May 3 17:27:28 2013, giving +2 See http://review.coreboot.org/3177 for details. -gerrit

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Patch merged into coreboot/master: 37714f3 crossgcc: update to gcc 4.7.3
by gerrit＠coreboot.org 03 May '13

03 May '13

the following patch was just integrated into master: commit 37714f33a6ac922c8e3a8e5761c0c7ac505acad1 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Fri Apr 19 00:56:57 2013 +0200 crossgcc: update to gcc 4.7.3 Update crossgcc to use gcc 4.7.3 The resulting coreboot.rom is not runtime tested (any volunteers?). Drop the texinfo patch, rename the armv7a patch. Some Linux distributions have moved on to gcc 4.8, under certain circumstances this version can't (cross-)compile gcc 4.7.2 Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927 Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-on: http://review.coreboot.org/3112 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Apr 22 14:27:40 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri May 3 17:26:47 2013, giving +2 See http://review.coreboot.org/3112 for details. -gerrit

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Patch set updated for coreboot: 61b79b4 x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c`
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3184 -gerrit commit 61b79b4d96ef1cdedb9e79cce9d16d8689449185 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:49:41 2013 +0200 x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c` Moving the code from the southbridges to `src/arch/x86/lib/ioapic.c` all boards using the function `set_ioapic_id()` get the debug feature. Change-Id: Ic59c4c2213ed97bdf3798b3dc6e7cecc30e135d8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/lib/ioapic.c | 6 ++++++ src/southbridge/intel/bd82x6x/lpc.c | 6 ------ src/southbridge/intel/i82801gx/lpc.c | 7 ------- src/southbridge/intel/lynxpoint/lpc.c | 6 ------ 4 files changed, 6 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 4964af6..74b734d 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -90,6 +90,12 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | (ioapic_id << 24)); } + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); + } static void load_vectors(u32 ioapic_base) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 181d36c..70a41a4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -60,7 +60,6 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -69,11 +68,6 @@ static void i82801gx_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index afd9a33..6785456 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -60,15 +60,8 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; - set_ioapic_id(IO_APIC_ADDR, 0x02); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 72347dc..5808222 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -64,7 +64,6 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -73,11 +72,6 @@ static void i82801gx_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ }

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Patch set updated for coreboot: 2e66108 Intel 82801Gx: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3181 -gerrit commit 2e66108d5e73d07184facf8a7d625d0b9cfefe32 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:40:23 2013 +0200 Intel 82801Gx: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 58 +++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 777a6d7..afd9a33 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -39,37 +39,38 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static void i82801gx_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) { - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ + /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} - *ioapic_index = 0; - *ioapic_data = (2 << 24); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) +{ + int i; - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + set_ioapic_id(IO_APIC_ADDR, 0x02); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); + + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void i82801gx_enable_serial_irqs(struct device *dev) @@ -421,8 +422,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + i82801gx_enable_acpi(dev); + /* IO APIC initialization. */ - i82801gx_enable_apic(dev); + i82801gx_enable_ioapic(dev); i82801gx_enable_serial_irqs(dev);

1 0

Patch set updated for coreboot: c1adf78 x86 I/O APIC: Make functions `io_apic_{read, write}()` public
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3180 -gerrit commit c1adf7805899a6f1c824358f4cd0a700e5edda8b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:34:43 2013 +0200 x86 I/O APIC: Make functions `io_apic_{read,write}()` public Some LPC initialiation can save some lines of code when being able to use the functions `io_apic_read()` and `io_apic_write()`. Change-Id: Id600007573ff011576967339cc66e6c883a2ed5a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/include/arch/ioapic.h | 2 ++ src/arch/x86/lib/ioapic.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index b989e52..7ff47bb 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -39,6 +39,8 @@ #define SMI (2 << 8) #define INT (1 << 8) +u32 io_apic_read(u32 ioapic_base, u32 reg); +void io_apic_write(u32 ioapic_base, u32 reg, u32 value); void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 389c48c..4964af6 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -22,13 +22,13 @@ #include <console/console.h> #include <cpu/x86/lapic.h> -static u32 io_apic_read(u32 ioapic_base, u32 reg) +u32 io_apic_read(u32 ioapic_base, u32 reg) { write32(ioapic_base, reg); return read32(ioapic_base + 0x10); } -static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) +void io_apic_write(u32 ioapic_base, u32 reg, u32 value) { write32(ioapic_base, reg); write32(ioapic_base + 0x10, value);

1 0

Patch set updated for coreboot: fb41d55 Intel BD82x6x: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3183 -gerrit commit fb41d55d65ad89de7a71dac80f1f03c76a9281b0 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:23:39 2013 +0200 Intel BD82x6x: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/bd82x6x/lpc.c | 65 +++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7bcadc9..181d36c 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -39,43 +39,43 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -537,8 +537,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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Patch set updated for coreboot: a98e2ef Intel Lynx Point: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3182 -gerrit commit a98e2ef173faa6de78e65e0143d32795bfd9d2a4 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:17:02 2013 +0200 Intel Lynx Point: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/lpc.c | 65 ++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 40e0468..72347dc 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -43,43 +43,43 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -546,8 +546,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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coreboot-gerrit May 2013