coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: f64c6a7 x86: add TSC_CONSTANT_RATE option
by Aaron Durbin 03 May '13

03 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3168 -gerrit commit f64c6a715c716adc9236c2157141b3259fca5e5a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:27:09 2013 -0500 x86: add TSC_CONSTANT_RATE option Some boards use the local apic for udelay(), but they also provide their own implementation of udelay() for SMM. The reason for using the local apic for udelay() in ramstage is to not have to pay the penalty of calibrating the TSC frequency. Therefore provide a TSC_CONSTANT_RATE option to indicate that TSC calibration is not needed. Instead it relies on the presence of a tsc_freq_mhz() function provided by the cpu/board. Additionally, assume that if TSC_CONSTANT_RATE is selected the udelay() function in SMM will be the tsc. Change-Id: I1629c2fbe3431772b4e80495160584fb6f599e9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 7 +++++++ src/cpu/x86/tsc/Makefile.inc | 4 ++++ src/cpu/x86/tsc/delay_tsc.c | 27 ++++++++++++++++++++++++--- src/include/cpu/x86/tsc.h | 4 ++++ 4 files changed, 39 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5cf40fa..c64a8e4 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -25,6 +25,13 @@ config UDELAY_TSC bool default n +config TSC_CONSTANT_RATE + def_bool n + depends on UDELAY_TSC + help + This option asserts that the TSC ticks at a known constant rate. + Therefore, no TSC calibration is required. + config TSC_MONOTONIC_TIMER def_bool n depends on UDELAY_TSC diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 44bfe85..3bbae84 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,2 +1,6 @@ ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) +smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +endif diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index e4993d0..0540496 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -5,8 +5,16 @@ #include <smp/spinlock.h> #include <delay.h> +#if !defined(__PRE_RAM__) + static unsigned long clocks_per_usec; +#if CONFIG_TSC_CONSTANT_RATE +static unsigned long calibrate_tsc(void) +{ + return tsc_freq_mhz(); +} +#else /* CONFIG_TSC_CONSTANT_RATE */ #if !CONFIG_TSC_CALIBRATE_WITH_IO #define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ @@ -139,6 +147,7 @@ static unsigned long long calibrate_tsc(void) #endif /* CONFIG_TSC_CALIBRATE_WITH_IO */ +#endif /* CONFIG_TSC_CONSTANT_RATE */ void init_timer(void) { @@ -148,15 +157,27 @@ void init_timer(void) } } +static inline unsigned long get_clocks_per_usec(void) +{ + init_timer(); + return clocks_per_usec; +} +#else /* !defined(__PRE_RAM__) */ +/* romstage calls into cpu/board specific function every time. */ +static inline unsigned long get_clocks_per_usec(void) +{ + return tsc_freq_mhz(); +} +#endif /* !defined(__PRE_RAM__) */ + void udelay(unsigned us) { unsigned long long count; unsigned long long stop; unsigned long long clocks; - init_timer(); clocks = us; - clocks *= clocks_per_usec; + clocks *= get_clocks_per_usec(); count = rdtscll(); stop = clocks + count; while(stop > count) { @@ -165,7 +186,7 @@ void udelay(unsigned us) } } -#if CONFIG_TSC_MONOTONIC_TIMER +#if CONFIG_TSC_MONOTONIC_TIMER && !defined(__PRE_RAM__) && !defined(__SMM__) #include <timer.h> static struct monotonic_counter { diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 6ce7f5f..8e49a66 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -40,4 +40,8 @@ static inline unsigned long long rdtscll(void) } #endif +#if CONFIG_TSC_CONSTANT_RATE +unsigned long tsc_freq_mhz(void); +#endif + #endif /* CPU_X86_TSC_H */

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Patch set updated for coreboot: 54c5429 x86: harden tsc udelay() function
by Aaron Durbin 03 May '13

03 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3171 -gerrit commit 54c54297f582c3187a1f5f6c357b817901996ed0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:55:14 2013 -0500 x86: harden tsc udelay() function Since the TSC udelay() fucntion can be used in SMM that means the TSC can count up to whatever value. The current loop was not handling TSC rollover properly. In most cases this should not matter as the TSC typically starts ticking at value 0, and it would take a very long time to roll it over. However, it is my understanding that this behavior is not guaranteed. Theoretically the TSC could start or be be written to with a large value that would cause the rollover. Change-Id: I2f11a5bc4f27d5543e74f8224811fa91e4a55484 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/tsc/delay_tsc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 0540496..0e2a9c0 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -172,18 +172,18 @@ static inline unsigned long get_clocks_per_usec(void) void udelay(unsigned us) { - unsigned long long count; - unsigned long long stop; - unsigned long long clocks; + unsigned long long start; + unsigned long long current; + unsigned long long clocks; + start = rdtscll(); clocks = us; clocks *= get_clocks_per_usec(); - count = rdtscll(); - stop = clocks + count; - while(stop > count) { + current = rdtscll(); + while((current - start) < clocks) { cpu_relax(); - count = rdtscll(); - } + current = rdtscll(); + } } #if CONFIG_TSC_MONOTONIC_TIMER && !defined(__PRE_RAM__) && !defined(__SMM__)

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Patch set updated for coreboot: 2151fea timer.h: add mono_time_diff_microseconds()
by David Hendricks 03 May '13

03 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3190 -gerrit commit 2151feacbf67dd3ce50e254903e28274f89399e3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri May 3 12:28:11 2013 -0700 timer.h: add mono_time_diff_microseconds() The current way to get a simple mono_time difference is: 1. Declare a rela_time struct 2. Assign it the value of mono_time_diff(t1, t2) 3. Get microseconds from it using rela_time_in_microseconds(). This patch adds a simpler method. Now one only needs to call mono_time_diff_microseconds(t1, t2) to obtain the same value which is produced from the above three steps. Change-Id: Ibfc9cd211e48e8e60a0a7703bff09cee3250e88b Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/timer.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/include/timer.h b/src/include/timer.h index e950c81..c32effe 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -155,4 +155,12 @@ static inline long rela_time_in_microseconds(const struct rela_time *rt) return rt->microseconds; } +static inline long mono_time_diff_microseconds(const struct mono_time *t1, + const struct mono_time *t2) +{ + struct rela_time rt; + rt = mono_time_diff(t1, t2); + return rela_time_in_microseconds(&rt); +} + #endif /* TIMER_H */

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Patch set updated for coreboot: 834d93a x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c`
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3184 -gerrit commit 834d93aa15b9a4f5c2af8eff2306ed5800ef0956 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:49:41 2013 +0200 x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c` Moving the code from the southbridges to `src/arch/x86/lib/ioapic.c` all boards using the function `set_ioapic_id()` get the debug feature. Change-Id: Ic59c4c2213ed97bdf3798b3dc6e7cecc30e135d8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/lib/ioapic.c | 7 +++++++ src/southbridge/intel/bd82x6x/lpc.c | 6 ------ src/southbridge/intel/i82801gx/lpc.c | 7 ------- src/southbridge/intel/lynxpoint/lpc.c | 6 ------ 4 files changed, 7 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 4964af6..7fb25ba 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -77,6 +77,7 @@ void clear_ioapic(u32 ioapic_base) void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) { u32 bsp_lapicid = lapicid(); + int i; printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); @@ -90,6 +91,12 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | (ioapic_id << 24)); } + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); + } static void load_vectors(u32 ioapic_base) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 3e5b653..bb47dc6 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -60,7 +60,6 @@ static void pch_enable_acpi(struct device *dev) */ static void pch_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -69,11 +68,6 @@ static void pch_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9d6224b..9285080 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -46,18 +46,11 @@ typedef struct southbridge_intel_i82801gx_config config_t; */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; - /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); set_ioapic_id(IO_APIC_ADDR, 0x02); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 2d1bd5e..35181ae 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -64,7 +64,6 @@ static void pch_enable_acpi(struct device *dev) */ static void pch_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -73,11 +72,6 @@ static void pch_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ }

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Patch set updated for coreboot: bbe85bb Intel 82801Gx: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3181 -gerrit commit bbe85bb4ded9615bbc781986b6f23bb1249cf22f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:40:23 2013 +0200 Intel 82801Gx: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. As commented by Aaron Durbin, a separate `i82801gx_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 45 +++++++++++++++--------------------- 1 file changed, 19 insertions(+), 26 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 777a6d7..9d6224b 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -39,37 +39,30 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static void i82801gx_enable_apic(struct device *dev) +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) { int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ + /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - *ioapic_index = 0; - *ioapic_data = (2 << 24); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + set_ioapic_id(IO_APIC_ADDR, 0x02); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void i82801gx_enable_serial_irqs(struct device *dev) @@ -422,7 +415,7 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ - i82801gx_enable_apic(dev); + i82801gx_enable_ioapic(dev); i82801gx_enable_serial_irqs(dev);

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Patch set updated for coreboot: d7aeafa x86 I/O APIC: Make functions `io_apic_{read, write}()` public
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3180 -gerrit commit d7aeafab0f3444a25d173160ddb4f4439cc4f5fd Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:34:43 2013 +0200 x86 I/O APIC: Make functions `io_apic_{read,write}()` public Some LPC initialiation can save some lines of code when being able to use the functions `io_apic_read()` and `io_apic_write()`. Change-Id: Id600007573ff011576967339cc66e6c883a2ed5a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/include/arch/ioapic.h | 2 ++ src/arch/x86/lib/ioapic.c | 4 ++-- src/drivers/generic/ioapic/ioapic.c | 4 ++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index b989e52..7ff47bb 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -39,6 +39,8 @@ #define SMI (2 << 8) #define INT (1 << 8) +u32 io_apic_read(u32 ioapic_base, u32 reg); +void io_apic_write(u32 ioapic_base, u32 reg, u32 value); void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 389c48c..4964af6 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -22,13 +22,13 @@ #include <console/console.h> #include <cpu/x86/lapic.h> -static u32 io_apic_read(u32 ioapic_base, u32 reg) +u32 io_apic_read(u32 ioapic_base, u32 reg) { write32(ioapic_base, reg); return read32(ioapic_base + 0x10); } -static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) +void io_apic_write(u32 ioapic_base, u32 reg, u32 value) { write32(ioapic_base, reg); write32(ioapic_base + 0x10, value); diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 9a93c78..379a415 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -12,13 +12,13 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> -static u32 io_apic_read(u32 ioapic_base, u32 reg) +u32 io_apic_read(u32 ioapic_base, u32 reg) { write32(ioapic_base, reg); return read32(ioapic_base + 0x10); } -static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) +void io_apic_write(u32 ioapic_base, u32 reg, u32 value) { write32(ioapic_base, reg); write32(ioapic_base + 0x10, value);

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Patch set updated for coreboot: a336858 Intel BD82x6x: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3183 -gerrit commit a33685814867072f2680839a05a794a979e9fe53 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:23:39 2013 +0200 Intel BD82x6x: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/bd82x6x/lpc.c | 65 +++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7bcadc9..3e5b653 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -39,43 +39,43 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void pch_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void pch_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -537,8 +537,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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Patch set updated for coreboot: bdaa1de Intel Lynx Point: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3182 -gerrit commit bdaa1de714cf1e05009417c636130dd436aa6789 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:17:02 2013 +0200 Intel Lynx Point: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/lpc.c | 65 ++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 40e0468..2d1bd5e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -43,43 +43,43 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void pch_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void pch_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -546,8 +546,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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New patch to review for coreboot: eb8b819 timer.h: add mono_time_diff_microseconds()
by David Hendricks 03 May '13

03 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3190 -gerrit commit eb8b8199b803774d5e65ca66d2e54db94bbc5c57 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri May 3 12:28:11 2013 -0700 timer.h: add mono_time_diff_microseconds() The current way to get a simple mono_time difference is: 1. Declare a rela_time struct 2. Assign it the value of mono_time_diff(t1, t2) 3. Get microseconds from it using rela_time_in_microseconds(). This patch adds a simpler method. Now one only needs to call mono_time_diff_microseconds(t1, t2) to obtain the same value which is produced from the above three steps. Change-Id: Ibfc9cd211e48e8e60a0a7703bff09cee3250e88b Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/timer.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/include/timer.h b/src/include/timer.h index e950c81..e755a90 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -153,6 +153,15 @@ static inline struct rela_time current_time_from(const struct mono_time *t) static inline long rela_time_in_microseconds(const struct rela_time *rt) { return rt->microseconds; + +} + +static inline long mono_time_diff_microseconds(const struct mono_time *t1, + const struct mono_time *t2) +{ + struct rela_time rt; + rt = mono_time_diff(t1, t2); + return rela_time_in_microseconds(&rt); } #endif /* TIMER_H */

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Patch set updated for coreboot: 381e3d2 exynos5/5250: Update timer call sites to use monotonic timer API
by David Hendricks 03 May '13

03 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3176 -gerrit commit 381e3d24c2ac388f28e76603a74edf48937e5146 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu May 2 14:23:51 2013 -0700 exynos5/5250: Update timer call sites to use monotonic timer API This goes thru various call sites where we used timer_us() and updates them to use the new monotonic timer API. udelay() changed substantially and now gracefully handles wraparound. Change-Id: Ie2cc86a4125cf0de12837fd7d337a11aed25715c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 17 +++++++++-------- src/cpu/samsung/exynos5-common/timer.c | 23 +++++++++++++---------- src/cpu/samsung/exynos5250/Makefile.inc | 3 +++ 3 files changed, 25 insertions(+), 18 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 00ff19e..b2e926f 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,7 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> -#include <time.h> +#include <timer.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -212,9 +212,8 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, struct video_info *video_info) { int timeout = 0; - u32 start, end; struct exynos5_dp *base = dp->base; - + struct mono_time start, current, end; s5p_dp_config_video_slave_mode(dp, video_info); s5p_dp_set_video_color_format(dp, video_info->color_depth, @@ -227,18 +226,20 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } - start = timer_us(); - end = start + STREAM_ON_TIMEOUT*1000; + timer_monotonic_get(&start); + end = current = start; + mono_time_add_usecs(&end, STREAM_ON_TIMEOUT * USECS_PER_MSEC); do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { timeout++; break; } - } while (timer_us() < end); + timer_monotonic_get(&current); + } while (mono_time_before(&current, &end)); if (!timeout) { - printk(BIOS_ERR, "Video Clock Not ok after %uus.\n", - timer_us() - start); + printk(BIOS_ERR, "Video Clock Not ok after %ldus.\n", + mono_time_diff_microseconds(&start, &end)); return -ERR_VIDEO_CLOCK_BAD; } diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index ca15501..b1ddd1a 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -25,7 +25,7 @@ #include <common.h> #include <arch/io.h> -#include <time.h> +#include <timer.h> #include <console/console.h> #include <cpu/samsung/exynos5-common/pwm.h> #include <cpu/samsung/exynos5-common/clk.h> @@ -121,16 +121,19 @@ unsigned long timer_get_us(void) /* delay x useconds */ void udelay(unsigned long usec) { - unsigned long start; + struct mono_time current, end; - start = timer_us(); - if ((start + usec) < start){ - printk(BIOS_EMERG, "udelay: %08lx is impossibly large\n", - usec); - usec = 1000000; - } - while ((timer_us() - start) < usec) - ; + timer_monotonic_get(&current); + end = current; + mono_time_add_usecs(&end, usec); + + if (mono_time_cmp(&current, &end) == 1) + printk(BIOS_WARNING, "udelay(%lu) will wraparound\n", usec); + while (mono_time_cmp(&current, &end) == 1) + timer_monotonic_get(&current); + + while (mono_time_cmp(&current, &end) == -1) + timer_monotonic_get(&current); } /* diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 403c198..2cd3428 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += pinmux.c mct.c power.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c +bootblock-$(CONFIG_EARLY_CONSOLE) += monotonic_timer.c bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c @@ -17,6 +18,7 @@ romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c +romstage-y += monotonic_timer.c romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c @@ -30,6 +32,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c ramstage-y += exynos5250-tmu.c ramstage-y += mct.c +ramstage-y += monotonic_timer.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c

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coreboot-gerrit May 2013