coreboot-gerrit May 2013

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Patch set updated for coreboot: 0adc10c Intel BD82x6x: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3183 -gerrit commit 0adc10c4848b3d2bdcd28a40da2be2468cb8ae64 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:23:39 2013 +0200 Intel BD82x6x: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/include/arch/ioapic.h | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 65 +++++++++++++++++++------------------ 2 files changed, 35 insertions(+), 32 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 0d5d076..8463269 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -39,7 +39,7 @@ #define SMI (2 << 8) #define INT (1 << 8) -void u32 io_apic_read(u32 ioapic_base, u32 reg); +void io_apic_read(u32 ioapic_base, u32 reg); void io_apic_write(u32 ioapic_base, u32 reg, u32 value); void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); void setup_ioapic(u32 ioapic_base, u8 ioapic_id); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7bcadc9..181d36c 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -39,43 +39,43 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -537,8 +537,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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Patch set updated for coreboot: 09d8e33 Intel Lynx Point: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3182 -gerrit commit 09d8e3341bb7e3f6df1ea0404c1729bccf5c0b00 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:17:02 2013 +0200 Intel Lynx Point: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/lpc.c | 65 ++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 40e0468..72347dc 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -43,43 +43,43 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -546,8 +546,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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Patch merged into coreboot/master: fe9f0f4 cpu/amd/agesa/family15tn/Kconfig: Remove unneeded `UDELAY_LAPIC`
by gerrit＠coreboot.org 03 May '13

03 May '13

the following patch was just integrated into master: commit fe9f0f4734fa9072b1d1aa45dbbdd56ee11c9bf8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 08:48:45 2013 +0200 cpu/amd/agesa/family15tn/Kconfig: Remove unneeded `UDELAY_LAPIC` Commit commit 825c78b5da98c7155ff6be3322cdaae0e5a060e8 Author: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Date: Thu May 2 18:06:03 2013 -0600 mainboard/{asus/f2a85-m,amd/thatcher}: move UDELAY_LAPIC Reviewed-on: http://review.coreboot.org/3178 adds `UDELAY_LAPIC` to `cpu/amd/agesa/family15tn/Kconfig`. This is not needed, because since commit commit e135ac5a7ea69b6edcb89345019212f5de412b1e Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 20 11:53:47 2012 +0100 Remove AMD special case for LAPIC based udelay() Reviewed-on: http://review.coreboot.org/1618 `select UDELAY_LAPIC` is present in `src/cpu/amd/agesa/Kconfig` which applies also to AMD Family 15tn. Therefore remove `select UDELAY_LAPIC` again from `cpu/amd/agesa/family15tn/Kconfig`. Change-Id: I98b783a97c4a1e45ecb29b776cb3d3877bad9c0f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3179 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Fri May 3 09:55:31 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Fri May 3 12:52:11 2013, giving +2 See http://review.coreboot.org/3179 for details. -gerrit

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New patch to review for coreboot: ecb467e x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c`
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3184 -gerrit commit ecb467ea212df74e1cf42692a66c35c048f5080d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:49:41 2013 +0200 x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c` Moving the code from the southbridges to `src/arch/x86/lib/ioapic.c` all boards using the function `set_ioapic_id()` get the debug feature. Change-Id: Ic59c4c2213ed97bdf3798b3dc6e7cecc30e135d8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/lib/ioapic.c | 6 ++++++ src/southbridge/intel/bd82x6x/lpc.c | 6 ------ src/southbridge/intel/i82801gx/lpc.c | 7 ------- src/southbridge/intel/lynxpoint/lpc.c | 6 ------ 4 files changed, 6 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 8528dd8..cc35ae3 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -90,6 +90,12 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | (ioapic_id << 24)); } + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); + } static void load_vectors(u32 ioapic_base) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 181d36c..70a41a4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -60,7 +60,6 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -69,11 +68,6 @@ static void i82801gx_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 8be8afc..6785456 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -60,15 +60,8 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; - set_ioapic_id(IO_APIC_ADDR, 0x02); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 72347dc..5808222 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -64,7 +64,6 @@ static void i82801gx_enable_acpi(struct device *dev) */ static void i82801gx_enable_ioapic(struct device *dev) { - int i; u32 reg32; set_ioapic_id(IO_APIC_ADDR, 0x02); @@ -73,11 +72,6 @@ static void i82801gx_enable_ioapic(struct device *dev) reg32 = io_apic_read(IO_APIC_ADDR, 0x01); io_apic_write(IO_APIC_ADDR, reg32); - printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); - for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ 0x01); /* Use Processor System Bus to deliver interrupts. */ }

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New patch to review for coreboot: 7652589 Intel BD82x6x: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3183 -gerrit commit 76525890636d94187d34caed1e46199e3cac1b62 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:23:39 2013 +0200 Intel BD82x6x: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/bd82x6x/lpc.c | 65 +++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7bcadc9..181d36c 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -39,43 +39,43 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -537,8 +537,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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New patch to review for coreboot: 1de6dcc Intel Lynx Point: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3182 -gerrit commit 1de6dcc51e9a274c34605ef07171fe1ea120b89e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:17:02 2013 +0200 Intel Lynx Point: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/lpc.c | 65 ++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 40e0468..72347dc 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -43,43 +43,43 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static void pch_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) +{ + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - *ioapic_index = 0; - *ioapic_data = (2 << 24); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + io_apic_write(IO_APIC_ADDR, reg32); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void pch_enable_serial_irqs(struct device *dev) @@ -546,8 +546,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + pch_enable_acpi(dev); + /* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_ioapic(dev); pch_enable_serial_irqs(dev);

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New patch to review for coreboot: da8d329 Intel 82801Gx: LPC: Unify I/O APIC setup
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3181 -gerrit commit da8d329c5f7ceee820f20e68cc2b7e3646ad540b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:40:23 2013 +0200 Intel 82801Gx: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 58 +++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 777a6d7..8be8afc 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -39,37 +39,38 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static void i82801gx_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) { - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + /* Set ACPI base address (I/O space). */ + /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */ - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ + /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} - *ioapic_index = 0; - *ioapic_data = (2 << 24); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (2 << 24)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801gx_enable_ioapic(struct device *dev) +{ + int i; - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + set_ioapic_id(IO_APIC_ADDR, 0x02); + + printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); + for (i = 0; i < 3; i++) + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, + io_apic_read(ioapic_base, i)); + + io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */ + 0x01); /* Use Processor System Bus to deliver interrupts. */ } static void i82801gx_enable_serial_irqs(struct device *dev) @@ -421,8 +422,11 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* ACPI initialization. */ + i82801gx_enable_acpi(dev); + /* IO APIC initialization. */ - i82801gx_enable_apic(dev); + i82801gx_enable_ioapic(dev); i82801gx_enable_serial_irqs(dev);

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New patch to review for coreboot: 1e8f04c x86 I/O APIC: Make functions `io_apic_{read, write}()` public
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3180 -gerrit commit 1e8f04c886aaaf93a2212342bb8c0d7409bbf227 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 14:34:43 2013 +0200 x86 I/O APIC: Make functions `io_apic_{read,write}()` public Some LPC initialiation can save some lines of code when being able to use the functions `io_apic_read()` and `io_apic_write()`. Change-Id: Id600007573ff011576967339cc66e6c883a2ed5a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/include/arch/ioapic.h | 2 ++ src/arch/x86/lib/ioapic.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index b989e52..0d5d076 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -39,6 +39,8 @@ #define SMI (2 << 8) #define INT (1 << 8) +void u32 io_apic_read(u32 ioapic_base, u32 reg); +void io_apic_write(u32 ioapic_base, u32 reg, u32 value); void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 389c48c..8528dd8 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -22,13 +22,13 @@ #include <console/console.h> #include <cpu/x86/lapic.h> -static u32 io_apic_read(u32 ioapic_base, u32 reg) +void u32 io_apic_read(u32 ioapic_base, u32 reg) { write32(ioapic_base, reg); return read32(ioapic_base + 0x10); } -static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) +void io_apic_write(u32 ioapic_base, u32 reg, u32 value) { write32(ioapic_base, reg); write32(ioapic_base + 0x10, value);

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New patch to review for coreboot: 96cebf7 cpu/amd/agesa/family15tn/Kconfig: Remove unneeded `UDELAY_LAPIC`
by Paul Menzel 03 May '13

03 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3179 -gerrit commit 96cebf7da195fb8d278fc32f74837b144424912d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 08:48:45 2013 +0200 cpu/amd/agesa/family15tn/Kconfig: Remove unneeded `UDELAY_LAPIC` Commit commit 825c78b5da98c7155ff6be3322cdaae0e5a060e8 Author: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Date: Thu May 2 18:06:03 2013 -0600 mainboard/{asus/f2a85-m,amd/thatcher}: move UDELAY_LAPIC Reviewed-on: http://review.coreboot.org/3178 adds `UDELAY_LAPIC` to `cpu/amd/agesa/family15tn/Kconfig`. This is not needed, because since commit commit e135ac5a7ea69b6edcb89345019212f5de412b1e Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 20 11:53:47 2012 +0100 Remove AMD special case for LAPIC based udelay() Reviewed-on: http://review.coreboot.org/1618 `select UDELAY_LAPIC` is present in `src/cpu/amd/agesa/Kconfig` which applies also to AMD Family 15tn. Therefore remove `select UDELAY_LAPIC` again from `cpu/amd/agesa/family15tn/Kconfig`. Change-Id: I98b783a97c4a1e45ecb29b776cb3d3877bad9c0f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/agesa/family15tn/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 57045cd..d2f5a8c 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -21,7 +21,6 @@ config CPU_AMD_AGESA_FAMILY15_TN bool select PCI_IO_CFG_EXT select X86_AMD_FIXED_MTRRS - select UDELAY_LAPIC config CPU_ADDR_BITS int

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Patch merged into coreboot/master: 5ec69ed exynos5250: monotonic timer implementation (using MCT)
by gerrit＠coreboot.org 03 May '13

03 May '13

the following patch was just integrated into master: commit 5ec69ed884852426e17439263e3678c5dfbc71e7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu May 2 13:23:08 2013 -0700 exynos5250: monotonic timer implementation (using MCT) This implements the new monotonic timer API using the global multi-core timer (MCT). Change-Id: Id56249ff5d3e0f85808f5754954c83c0bc75f1c1 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3175 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri May 3 06:19:27 2013, giving +1 See http://review.coreboot.org/3175 for details. -gerrit

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