coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: df4c40c x86: add TSC_CONSTANT_RATE option
by Aaron Durbin 01 May '13

01 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3168 -gerrit commit df4c40cfb03887bce5acceeeab1904b68ca4f14b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:27:09 2013 -0500 x86: add TSC_CONSTANT_RATE option Some boards use the local apic for udelay(), but they also provide their own implementation of udelay() for SMM. The reason for using the local apic for udelay() in ramstage is to not have to pay the penalty of calibrating the TSC frequency. Therefore provide a TSC_CONSTANT_RATE option to bypass calibration. Instead it relies on the presence of a tsc_freq_mhz() function provided by the cpu/board. Additionally, assume that if TSC_CONSTANT_RATE is selected the udelay() function in SMM will be the tsc. Change-Id: I1629c2fbe3431772b4e80495160584fb6f599e9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 4 ++++ src/cpu/x86/tsc/Makefile.inc | 4 ++++ src/cpu/x86/tsc/delay_tsc.c | 27 ++++++++++++++++++++++++--- src/include/cpu/x86/tsc.h | 4 ++++ 4 files changed, 36 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5cf40fa..3d2840b 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -25,6 +25,10 @@ config UDELAY_TSC bool default n +config TSC_CONSTANT_RATE + def_bool n + depends on UDELAY_TSC + config TSC_MONOTONIC_TIMER def_bool n depends on UDELAY_TSC diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 44bfe85..3bbae84 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,2 +1,6 @@ ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) +smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +endif diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index e4993d0..0540496 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -5,8 +5,16 @@ #include <smp/spinlock.h> #include <delay.h> +#if !defined(__PRE_RAM__) + static unsigned long clocks_per_usec; +#if CONFIG_TSC_CONSTANT_RATE +static unsigned long calibrate_tsc(void) +{ + return tsc_freq_mhz(); +} +#else /* CONFIG_TSC_CONSTANT_RATE */ #if !CONFIG_TSC_CALIBRATE_WITH_IO #define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ @@ -139,6 +147,7 @@ static unsigned long long calibrate_tsc(void) #endif /* CONFIG_TSC_CALIBRATE_WITH_IO */ +#endif /* CONFIG_TSC_CONSTANT_RATE */ void init_timer(void) { @@ -148,15 +157,27 @@ void init_timer(void) } } +static inline unsigned long get_clocks_per_usec(void) +{ + init_timer(); + return clocks_per_usec; +} +#else /* !defined(__PRE_RAM__) */ +/* romstage calls into cpu/board specific function every time. */ +static inline unsigned long get_clocks_per_usec(void) +{ + return tsc_freq_mhz(); +} +#endif /* !defined(__PRE_RAM__) */ + void udelay(unsigned us) { unsigned long long count; unsigned long long stop; unsigned long long clocks; - init_timer(); clocks = us; - clocks *= clocks_per_usec; + clocks *= get_clocks_per_usec(); count = rdtscll(); stop = clocks + count; while(stop > count) { @@ -165,7 +186,7 @@ void udelay(unsigned us) } } -#if CONFIG_TSC_MONOTONIC_TIMER +#if CONFIG_TSC_MONOTONIC_TIMER && !defined(__PRE_RAM__) && !defined(__SMM__) #include <timer.h> static struct monotonic_counter { diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 6ce7f5f..8e49a66 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -40,4 +40,8 @@ static inline unsigned long long rdtscll(void) } #endif +#if CONFIG_TSC_CONSTANT_RATE +unsigned long tsc_freq_mhz(void); +#endif + #endif /* CPU_X86_TSC_H */

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Patch set updated for coreboot: 15da48c Asus F2A85X-M Verb Table for ALC887-VD
by Rudolf Marek 01 May '13

01 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3170 -gerrit commit 15da48cf76b6920c8846f12f3145f509e9f6c8ff Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue Apr 2 20:51:15 2013 +0200 Asus F2A85X-M Verb Table for ALC887-VD Verbs taken from /sys/class/sound/hwC1D0/init_pin_configs Change-Id: I17fa2d4ab1e1a6bfd84de94e9e4a91bd67b6a0c0 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 38 +++++++++++++++---------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index f976001..050a8cc 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -63,29 +63,29 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /** - * AMD Thatcher Platform ALC272 Verb Table + * Verb Table for ALC887-VD, listed from /sys/class/sound/hwC1D0/init_pin_configs */ -const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, - {0x12, 0x411111F0}, - {0x13, 0x411111F0}, - {0x14, 0x411111F0}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x17, 0x411111F0}, - {0x18, 0x01a19840}, - {0x19, 0x411111F0}, - {0x1a, 0x01813030}, - {0x1b, 0x411111F0}, - {0x1d, 0x40130605}, - {0x1e, 0x01441120}, - {0x21, 0x01211010}, +const CODEC_ENTRY alc887_VerbTbl[] = { + {0x11, 0x99430140}, + {0x12, 0x411111f0}, + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01012014}, + {0x18, 0x01a19850}, + {0x19, 0x02a19c60}, + {0x1a, 0x0181305f}, + {0x1b, 0x02214c20}, + {0x1c, 0x411111f0}, + {0x1d, 0x4005e601}, + {0x1e, 0x01456130}, + {0x1f, 0x411111f0}, {0xff, 0xffffffff} }; -const CODEC_TBL_LIST ThatcherCodecTableList[] = +static const CODEC_TBL_LIST CodecTableList[] = { - {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, + {0x10ec0887, (CODEC_ENTRY*)&alc887_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} }; @@ -110,7 +110,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); /* Azalia Controller Front Panel OEM Table Pointer */ FchParams_env->Imc.ImcEnable = FALSE; FchParams_env->Hwm.HwMonitorEnable = FALSE;

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New patch to review for coreboot: 79b737e Verb Table for ALC887-VD
by Rudolf Marek 01 May '13

01 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3170 -gerrit commit 79b737e8ed63deaf58ab5fa18288142d4e0dfd38 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue Apr 2 20:51:15 2013 +0200 Verb Table for ALC887-VD Verbs taken from /sys/class/sound/hwC1D0/init_pin_configs Change-Id: I17fa2d4ab1e1a6bfd84de94e9e4a91bd67b6a0c0 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 38 +++++++++++++++---------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index f976001..050a8cc 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -63,29 +63,29 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /** - * AMD Thatcher Platform ALC272 Verb Table + * Verb Table for ALC887-VD, listed from /sys/class/sound/hwC1D0/init_pin_configs */ -const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, - {0x12, 0x411111F0}, - {0x13, 0x411111F0}, - {0x14, 0x411111F0}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x17, 0x411111F0}, - {0x18, 0x01a19840}, - {0x19, 0x411111F0}, - {0x1a, 0x01813030}, - {0x1b, 0x411111F0}, - {0x1d, 0x40130605}, - {0x1e, 0x01441120}, - {0x21, 0x01211010}, +const CODEC_ENTRY alc887_VerbTbl[] = { + {0x11, 0x99430140}, + {0x12, 0x411111f0}, + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01012014}, + {0x18, 0x01a19850}, + {0x19, 0x02a19c60}, + {0x1a, 0x0181305f}, + {0x1b, 0x02214c20}, + {0x1c, 0x411111f0}, + {0x1d, 0x4005e601}, + {0x1e, 0x01456130}, + {0x1f, 0x411111f0}, {0xff, 0xffffffff} }; -const CODEC_TBL_LIST ThatcherCodecTableList[] = +static const CODEC_TBL_LIST CodecTableList[] = { - {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, + {0x10ec0887, (CODEC_ENTRY*)&alc887_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} }; @@ -110,7 +110,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); /* Azalia Controller Front Panel OEM Table Pointer */ FchParams_env->Imc.ImcEnable = FALSE; FchParams_env->Hwm.HwMonitorEnable = FALSE;

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New patch to review for coreboot: 2aa6de9 haswell: use tsc for udelay()
by Aaron Durbin 01 May '13

01 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3169 -gerrit commit 2aa6de938617deeaed1c04e1d2c119cb9896fbe1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:39:28 2013 -0500 haswell: use tsc for udelay() Instead of using the local apic timer for udelay() use the tsc. That way SMM, romstage, and ramstage all use the same delay functionality. Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 3 +- src/cpu/intel/haswell/Makefile.inc | 3 ++ src/cpu/intel/haswell/tsc_freq.c | 31 +++++++++++++++ src/northbridge/intel/haswell/Makefile.inc | 1 - src/northbridge/intel/haswell/udelay.c | 63 ------------------------------ 5 files changed, 36 insertions(+), 65 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 13861f9..152059f 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE select SMM_TSEG select SMM_MODULES select RELOCATABLE_MODULES diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 90ffd66..60c061d 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,7 +1,9 @@ ramstage-y += haswell_init.c subdirs-y += ../../x86/name ramstage-y += mp_init.c +ramstage-y += tsc_freq.c romstage-y += romstage.c +romstage-y += tsc_freq.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c @@ -10,6 +12,7 @@ ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc diff --git a/src/cpu/intel/haswell/tsc_freq.c b/src/cpu/intel/haswell/tsc_freq.c new file mode 100644 index 0000000..0a78053 --- /dev/null +++ b/src/cpu/intel/haswell/tsc_freq.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include "cpu/intel/haswell/haswell.h" + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff); +} diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 896360d..b2ac85e 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail diff --git a/src/northbridge/intel/haswell/udelay.c b/src/northbridge/intel/haswell/udelay.c deleted file mode 100644 index f5d541e..0000000 --- a/src/northbridge/intel/haswell/udelay.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include "cpu/intel/haswell/haswell.h" - -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_PLATFORM_INFO); - divisor = (msr.lo >> 8) & 0xff; - - d = HASWELL_BCLK * divisor; - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); -}

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New patch to review for coreboot: 9c37bbb x86: add TSC_CONSTANT_RATE option
by Aaron Durbin 01 May '13

01 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3168 -gerrit commit 9c37bbb822f522eaa227366e16264eed45284910 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 15:27:09 2013 -0500 x86: add TSC_CONSTANT_RATE option Some boards use the local apic for udelay(), but they also provide their own implementation of udelay() for SMM. The reason for using the local apic for udelay() in ramstage is to not have to pay the penalty of calibrating the TSC frequency. Therefore provide a TSC_CONSTANT_RATE option to bypass calibration. Instead it relies on the presence of a tsc_freq_mhz() function provided by the cpu/board. Additionally, assume that if TSC_CONSTANT_RATE is selected the udelay() function in SMM will be the tsc. Change-Id: I1629c2fbe3431772b4e80495160584fb6f599e9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 4 ++++ src/cpu/x86/tsc/Makefile.inc | 2 ++ src/cpu/x86/tsc/delay_tsc.c | 27 ++++++++++++++++++++++++--- src/include/cpu/x86/tsc.h | 4 ++++ 4 files changed, 34 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5cf40fa..3d2840b 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -25,6 +25,10 @@ config UDELAY_TSC bool default n +config TSC_CONSTANT_RATE + def_bool n + depends on UDELAY_TSC + config TSC_MONOTONIC_TIMER def_bool n depends on UDELAY_TSC diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 44bfe85..20db9fe 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,2 +1,4 @@ ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += delay_tsc.c diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index e4993d0..0540496 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -5,8 +5,16 @@ #include <smp/spinlock.h> #include <delay.h> +#if !defined(__PRE_RAM__) + static unsigned long clocks_per_usec; +#if CONFIG_TSC_CONSTANT_RATE +static unsigned long calibrate_tsc(void) +{ + return tsc_freq_mhz(); +} +#else /* CONFIG_TSC_CONSTANT_RATE */ #if !CONFIG_TSC_CALIBRATE_WITH_IO #define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ @@ -139,6 +147,7 @@ static unsigned long long calibrate_tsc(void) #endif /* CONFIG_TSC_CALIBRATE_WITH_IO */ +#endif /* CONFIG_TSC_CONSTANT_RATE */ void init_timer(void) { @@ -148,15 +157,27 @@ void init_timer(void) } } +static inline unsigned long get_clocks_per_usec(void) +{ + init_timer(); + return clocks_per_usec; +} +#else /* !defined(__PRE_RAM__) */ +/* romstage calls into cpu/board specific function every time. */ +static inline unsigned long get_clocks_per_usec(void) +{ + return tsc_freq_mhz(); +} +#endif /* !defined(__PRE_RAM__) */ + void udelay(unsigned us) { unsigned long long count; unsigned long long stop; unsigned long long clocks; - init_timer(); clocks = us; - clocks *= clocks_per_usec; + clocks *= get_clocks_per_usec(); count = rdtscll(); stop = clocks + count; while(stop > count) { @@ -165,7 +186,7 @@ void udelay(unsigned us) } } -#if CONFIG_TSC_MONOTONIC_TIMER +#if CONFIG_TSC_MONOTONIC_TIMER && !defined(__PRE_RAM__) && !defined(__SMM__) #include <timer.h> static struct monotonic_counter { diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 6ce7f5f..8e49a66 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -40,4 +40,8 @@ static inline unsigned long long rdtscll(void) } #endif +#if CONFIG_TSC_CONSTANT_RATE +unsigned long tsc_freq_mhz(void); +#endif + #endif /* CPU_X86_TSC_H */

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Patch set updated for coreboot: e55196f libpayload: make searching for a file less verbose
by Aaron Durbin 01 May '13

01 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3164 -gerrit commit e55196fad1562ff240c7a4da7c8890f67cb803f8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 1 08:40:13 2013 -0500 libpayload: make searching for a file less verbose The cbfs core code would print out all unmatched file names when searching for a file. This contributes to a lot of unnecessary messages in the boot log. Change this message to a DEBUG one so that it will only be printed when CONFIG_DEBUG_CBFS is enabled. Change-Id: I34c747e0d3406351318abf70994dbc0bb3fa6c01 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/libcbfs/cbfs_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index a714b91..3fe6971 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -158,7 +158,8 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) media->close(media); return file_ptr; } else { - LOG(" (unmatched file @0x%x: %s)\n", offset, file_name); + DEBUG(" (unmatched file @0x%x: %s)\n", offset, + file_name); media->unmap(media, file_name); }

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Patch set updated for coreboot: 02d17e9 cbfs: make searching for a file less verbose
by Aaron Durbin 01 May '13

01 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3131 -gerrit commit 02d17e93bc9a8e9fc4f95f45a53a4d74e99dfca2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 25 08:42:23 2013 -0500 cbfs: make searching for a file less verbose The cbfs core code would print out all unmatched file names when searching for a file. This contributes to a lot of unnecessary messages in the boot log. Change this message to a DEBUG one so that it will only be printed when CONFIG_DEBUG_CBFS is enabled. Change-Id: I1e46a4b21d80e5d2f9b511a163def7f5d4e0fb99 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/cbfs_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 9732b82..1220d48 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -158,7 +158,8 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) media->close(media); return file_ptr; } else { - LOG(" (unmatched file @0x%x: %s)\n", offset, file_name); + DEBUG(" (unmatched file @0x%x: %s)\n", offset, + file_name); media->unmap(media, file_name); }

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New patch to review for coreboot: c81c69a Enable the SD controller for F2A85-M
by Rudolf Marek 01 May '13

01 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3167 -gerrit commit c81c69ad4aedbeef72df649efdaf16dc4304c35d Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Wed May 1 22:29:13 2013 +0200 Enable the SD controller for F2A85-M If the SD controller is "off" hudson.c won't disable that. The PCI device is still visible and PCI BAR will be allocated by Linux. Unfortunately it may happen that the particular address is used by non-standard BAR for SPI controller. Change-Id: Ied7c581727541e2c81b0b1c2b70fd32de0014730 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 8272964..0014381 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -102,7 +102,8 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. device pci 14.5 on end # USB 2 device pci 14.6 off end # Gec - device pci 14.7 off end + # SD, make it on so the BAR is assigned (if proper hudson on/off handling is implemented this may go away) + device pci 14.7 on end device pci 15.0 on end # PCIe 0 - onboard PCIe 1x device pci 15.1 on end # PCIe 1 onboard gigabit device pci 15.2 off end # unused

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Patch merged into coreboot/master: 0529429 device tree: track init times
by gerrit＠coreboot.org 01 May '13

01 May '13

the following patch was just integrated into master: commit 052942923b2320ee9cb2a1bcc2d2689c179ad4f5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 30 15:41:13 2013 -0500 device tree: track init times With the introduction of a monotonic timer it is possible to track the individual times of each device's init() call. Add this ability behind a HAVE_MONOTONIC_TIMER option. Example log messages: Root Device init 5 usecs CPU_CLUSTER: 0 init 66004 usecs PCI: 00:00.0 init 1020 usecs PCI: 00:02.0 init 456941 usecs PCI: 00:13.0 init 3 usecs PCI: 00:14.0 init 3 usecs PCI: 00:15.0 init 92 usecs PCI: 00:15.1 init 37 usecs PCI: 00:15.2 init 36 usecs PCI: 00:15.3 init 35 usecs PCI: 00:15.4 init 35 usecs PCI: 00:15.5 init 36 usecs PCI: 00:15.6 init 35 usecs PCI: 00:16.0 init 3666 usecs PCI: 00:17.0 init 63 usecs PCI: 00:1b.0 init 3 usecs PCI: 00:1c.0 init 89 usecs PCI: 00:1c.1 init 15 usecs PCI: 00:1c.2 init 15 usecs PCI: 00:1c.3 init 15 usecs PCI: 00:1c.4 init 15 usecs PCI: 00:1c.5 init 16 usecs PCI: 00:1d.0 init 4 usecs PCI: 00:1f.0 init 495 usecs PCI: 00:1f.2 init 29 usecs PCI: 00:1f.3 init 4 usecs PCI: 00:1f.6 init 4 usecs Change-Id: Ibe499848432c7ab20166ab10d6dfb07db03eab01 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3162 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Wed May 1 21:30:20 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 19:33:39 2013, giving +2 See http://review.coreboot.org/3162 for details. -gerrit

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Patch set updated for coreboot: 03096da armv7: invalidate TLB entries as they are added/modified
by David Hendricks 01 May '13

01 May '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3166 -gerrit commit 03096dad4a904692603b84df67241b9668d0c765 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Apr 30 16:01:50 2013 -0700 armv7: invalidate TLB entries as they are added/modified The old approach was to invalidate the entire TLB every time we set up a table entry. This worked because we didn't turn the MMU on until after we had set everything up. This patch uses the TLBIMVAA wrapper to invalidate each entry as it's added/modified. Change-Id: I27654a543a2015574d910e15d48b3d3845fdb6d1 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/mmu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c index 82c7358..d4e08f7 100644 --- a/src/arch/armv7/lib/mmu.c +++ b/src/arch/armv7/lib/mmu.c @@ -99,11 +99,10 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n", start_mb << 20, ((start_mb + size_mb) << 20) - 1, str); - for (i = start_mb; i < start_mb + size_mb; i++) + for (i = start_mb; i < start_mb + size_mb; i++) { ttb_entry[i] = (i << 20) | attr; - - /* TODO: add helper to invalidate TLB by MVA */ - tlb_invalidate_all(); + tlbimvaa(start_mb); + } } void mmu_init(void)

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coreboot-gerrit May 2013