the following patch was just integrated into master:
commit fd8291c9d438917e334f4211fb1142b6a7bb7e32
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Apr 29 17:18:49 2013 -0500
lapic: monotonic time implementation
Implement the timer_monotonic_get() functionality based off of
the local apic timer.
Change-Id: I1aa1ff64d15a3056d6abd1372be13da682c5ee2e
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3154
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Wed May 1 01:46:26 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:15:17 2013, giving +2
See http://review.coreboot.org/3154 for details.
-gerrit
the following patch was just integrated into master:
commit c46cc6f149c42653344d6e9f3656a4212fc46cef
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Apr 29 16:57:10 2013 -0500
haswell: 24MHz monotonic time implementation
Haswell ULT devices have a 24MHz package-level counter. Use
this counter to provide a timer_monotonic_get() implementation.
Change-Id: Ic79843fcbfbbb6462ee5ebd12b39502307750dbb
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3153
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Wed May 1 00:47:58 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:14:36 2013, giving +2
See http://review.coreboot.org/3153 for details.
-gerrit
the following patch was just integrated into master:
commit a421791db815fb2e2da9b1ce4bec78c97665b62f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Apr 29 22:31:51 2013 -0500
coreboot: introduce monotonic timer API
The notion of a monotonic timer is introduced. Along with it
are helper functions and other types for comparing times. This
is just the framework where it is the responsibility of the
chipset/board to provide the implementation of timer_monotonic_get().
The reason structs are used instead of native types is to allow
for future changes to the data structure without chaning all the
call sites.
Change-Id: Ie56b9ab9dedb0da69dea86ef87ca744004eb1ae3
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3152
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Apr 30 21:58:10 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:13:43 2013, giving +2
See http://review.coreboot.org/3152 for details.
-gerrit
the following patch was just integrated into master:
commit 001de1aeb00e604e4664659b831ca99d1a940d57
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Apr 24 22:59:45 2013 -0500
boot state: rebalance payload load vs actual boot
The notion of loading a payload in the current boot state
machine isn't actually loading the payload. The reason is
that cbfs is just walked to find the payload. The actual
loading and booting were occuring in selfboot(). Change this
balance so that loading occurs in one function and actual
booting happens in another. This allows for ample opportunity
to delay work until just before booting.
Change-Id: Ic91ed6050fc5d8bb90c8c33a44eea3b1ec84e32d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3139
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Apr 30 01:44:50 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:13:16 2013, giving +2
See http://review.coreboot.org/3139 for details.
-gerrit
the following patch was just integrated into master:
commit bebf66909a11201a1bbfbdf7f1af40285d76a457
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Apr 24 20:59:43 2013 -0500
x86: use boot state callbacks to disable rom cache
On x86 systems there is a concept of cachings the ROM. However,
the typical policy is that the boot cpu is the only one with
it enabled. In order to ensure the MTRRs are the same across cores
the rom cache needs to be disabled prior to OS resume or boot handoff.
Therefore, utilize the boot state callbacks to schedule the disabling
of the ROM cache at the ramstage exit points.
Change-Id: I4da5886d9f1cf4c6af2f09bb909f0d0f0faa4e62
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3138
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Apr 30 01:13:51 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:12:14 2013, giving +2
See http://review.coreboot.org/3138 for details.
-gerrit
the following patch was just integrated into master:
commit 243aa44b74935cfc969106dbbe2420ee4a2c39b2
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Apr 24 17:31:49 2013 -0500
boot: remove cbmem_post_handling()
The cbmem_post_handling() function was implemented by 2
chipsets in order to save memory configuration in flash. Convert
both of these chipsets to use the boot state machine callbacks
to perform the saving of the memory configuration.
Change-Id: I697e5c946281b85a71d8533437802d7913135af3
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3137
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Apr 30 00:41:44 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:11:21 2013, giving +2
See http://review.coreboot.org/3137 for details.
-gerrit
the following patch was just integrated into master:
commit 40131cfa46bc195ad3bdf2ce9b9af67dcbfd71ca
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Apr 24 16:39:08 2013 -0500
cbmem: use boot state machine
There were previously 2 functions, init_cbmem_pre_device() and
init_cbmem_post_device(), where the 2 cbmem implementations
implemented one or the other. These 2 functions are no longer
needed to be called in the boot flow once the boot state callbacks
are utilized.
Change-Id: Ida71f1187bdcc640ae600705ddb3517e1410a80d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3136
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Apr 30 00:08:40 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:10:01 2013, giving +2
See http://review.coreboot.org/3136 for details.
-gerrit
the following patch was just integrated into master:
commit 4dd87fb2d852a61fd1677dd81e0a5573e9023eb1
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Apr 24 16:28:52 2013 -0500
coverage: use boot state callbacks
Utilize the static boot state callback scheduling to initialize
and tear down the coverage infrastructure at the appropriate points.
The coverage initialization is performed at BS_PRE_DEVICE which is the
earliest point a callback can be called. The tear down occurs at the
2 exit points of ramstage: OS resume and payload boot.
Change-Id: Ie5ee51268e1f473f98fa517710a266e38dc01b6d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3135
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Mon Apr 29 21:49:00 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:08:43 2013, giving +2
See http://review.coreboot.org/3135 for details.
-gerrit
the following patch was just integrated into master:
commit 0a6c20a2a3bc16aa12b04dd3db1d1260777edf0e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Apr 24 22:33:08 2013 -0500
acpi: split resume check and actual resume code
It's helpful to provide a distinct state that affirmatively
describes that OS resume will occur. The previous code included
the check and the actual resuming in one function. Because of this
grouping one had to annotate the innards of the ACPI resume
path to perform specific actions before OS resume. By providing
a distinct state in the boot state machine the necessary actions
can be scheduled accordingly without modifying the ACPI code.
Change-Id: I8b00aacaf820cbfbb21cb851c422a143371878bd
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3134
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Mon Apr 29 22:19:39 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:07:32 2013, giving +2
See http://review.coreboot.org/3134 for details.
-gerrit
the following patch was just integrated into master:
commit a4feddf897023b37cfac2af529e787504849f985
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Apr 24 16:12:52 2013 -0500
boot state: schedule static callbacks
Many of the boot state callbacks can be scheduled at compile time.
Therefore, provide a way for a compilation unit to inform the
boot state machine when its callbacks should be called. Each C
module can export the callbacks and their scheduling requirements
without changing the shared boot flow code.
Change-Id: Ibc4cea4bd5ad45b2149c2d4aa91cbea652ed93ed
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3133
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Mon Apr 29 22:50:42 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:06:11 2013, giving +2
See http://review.coreboot.org/3133 for details.
-gerrit