coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: dd5ff36 CPU: Define a config variable for 64-bit address capability
by Paul Menzel 01 May '13

01 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3157 -gerrit commit dd5ff365e3607e60d7b260730c1705acc19d8c8c Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Apr 30 08:38:16 2013 -0700 CPU: Define a config variable for 64-bit address capability For the most part, we don't need 64-bit addressing. In the future, it will be more important, but it's useful to have an indicator that a CPU can even run in that mode. Change-Id: I59e4061e07c16c5def7d9950749a55083612f6af Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index ed7d6ab..2edca98 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -1,6 +1,17 @@ # Warning: This file is included whether or not the if is here. # The if controls how the evaluation occurs. # (See also src/Kconfig) + +config HAVE_64BIT + bool + default n + help + Many of the CPUs in our tree can support 64-bit addresses. + Currently, we don't use this capability on any of them. + This variable indicates whether it is even possible, + for a given CPU, to run in 64-bit mode. For the subset of + CPUs which can support 64-bit mode it can be overridden. + if ARCH_ARMV7 source src/cpu/armltd/Kconfig

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Patch set updated for coreboot: 385bd6f ARMV7: add a function to disable MMU entries
by Paul Menzel 01 May '13

01 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3160 -gerrit commit 385bd6f069309d07c50a103651305ae8d7212e05 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Apr 30 10:11:30 2013 -0700 ARMV7: add a function to disable MMU entries It is useful to be able to lock out certain address ranges, NULL being the most important example. void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) will allow us to lock out selected virtual addresses on MiB boundaries. As in other ARM mmu functions, the addresses and quantities are in units of MiB. Change-Id: If516ce955ee2d12c5a409f25acbb5a4b424f699b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/include/arch/cache.h | 2 ++ src/arch/armv7/lib/mmu.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 028cf18..d5c3a5b 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -303,6 +303,8 @@ enum dcache_policy { DCACHE_WRITETHROUGH, }; +/* disable the mmu for a range. Primarily useful to lock out address 0. */ +void mmu_disable_range(unsigned long start_mb, unsigned long size_mb); /* mmu range configuration (set dcache policy) */ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, enum dcache_policy policy); diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c index 224b566..82c7358 100644 --- a/src/arch/armv7/lib/mmu.c +++ b/src/arch/armv7/lib/mmu.c @@ -39,6 +39,19 @@ static uintptr_t ttb_addr; +void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) +{ + unsigned int i; + uint32_t *ttb_entry = (uint32_t *)ttb_addr; + printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n", + start_mb << 20, ((start_mb + size_mb) << 20) - 1); + + for (i = start_mb; i < start_mb + size_mb; i++) { + ttb_entry[i] = 0; + tlbimvaa(i); + } +} + void mmu_config_range(unsigned long start_mb, unsigned long size_mb, enum dcache_policy policy) {

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Patch set updated for coreboot: 5c0855a ARMV7: add a function to disable MMU entries
by Ronald G. Minnich 01 May '13

01 May '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3160 -gerrit commit 5c0855abead284f3ef4d3d0e6505f8bff7795cab Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Apr 30 10:11:30 2013 -0700 ARMV7: add a function to disable MMU entries It is useful to be able to lock out certain address ranges, NULL being the most important example. void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) Will allow us to lock out selected virtual addresses on MiB boundaries. As in other ARM mmu functions, the addresses and quantities are in units of MiB. Change-Id: If516ce955ee2d12c5a409f25acbb5a4b424f699b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/include/arch/cache.h | 2 ++ src/arch/armv7/lib/mmu.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 028cf18..d5c3a5b 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -303,6 +303,8 @@ enum dcache_policy { DCACHE_WRITETHROUGH, }; +/* disable the mmu for a range. Primarily useful to lock out address 0. */ +void mmu_disable_range(unsigned long start_mb, unsigned long size_mb); /* mmu range configuration (set dcache policy) */ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, enum dcache_policy policy); diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c index 224b566..d7a0203 100644 --- a/src/arch/armv7/lib/mmu.c +++ b/src/arch/armv7/lib/mmu.c @@ -39,6 +39,20 @@ static uintptr_t ttb_addr; +void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) +{ + unsigned int i; + uint32_t *ttb_entry = (uint32_t *)ttb_addr; + printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n", + start_mb << 20, ((start_mb + size_mb) << 20) - 1); + + for (i = start_mb; i < start_mb + size_mb; i++){ + ttb_entry[i] = 0; + tlbimvaa(i); + } + +} + void mmu_config_range(unsigned long start_mb, unsigned long size_mb, enum dcache_policy policy) {

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Patch merged into coreboot/master: c99ae5d armv7: add wrapper for tlbimvaa
by gerrit＠coreboot.org 01 May '13

01 May '13

the following patch was just integrated into master: commit c99ae5d9a93212cbecff0d10a1710b68f26e966e Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Apr 30 12:20:53 2013 -0700 armv7: add wrapper for tlbimvaa This adds an inline wrapper for the TLBIMVAA instruction (invalidate unified TLB by MVA, all address space identifiers). Change-Id: Ibcd289ecedaba8586ade26e36c177ff1fcaf91d3 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3161 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Wed May 1 08:16:19 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Apr 30 22:59:18 2013, giving +2 See http://review.coreboot.org/3161 for details. -gerrit

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Patch set updated for coreboot: a40faa7 Google/Snow: Revise bootblock initialization.
by Ronald G. Minnich 01 May '13

01 May '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3151 -gerrit commit a40faa72aec099fa4b48ed66d08ed450de6fe099 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Apr 30 16:14:35 2013 +0800 Google/Snow: Revise bootblock initialization. It's fine to always start timer even in suspend/resume mode, so we can move the timer_start() back to the very beginning of boot procedure. That provides more precise boot time information. With that timer change, the wake up state test procedure can be simplified. Verified by building and booting firmware image on Google/Snow successfully, and then suspend-resume without problem (suspend_stress_test). Change-Id: I0d739650dbff4eb3a75acbbf1e4356f2569b487d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 4a78946..4464042 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -30,17 +30,14 @@ void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - switch (snow_get_wakeup_state()) { - case SNOW_WAKEUP_DIRECT: - snow_wakeup(); - break; + /* kick off the microsecond timer. + * We want to do this as early as we can. + */ + timer_start(); - case SNOW_IS_NOT_WAKEUP: - /* kick off the microsecond timer. - * We want to do this as early as we can. - */ - timer_start(); - break; + if (snow_get_wakeup_state() == SNOW_WAKEUP_DIRECT) { + snow_wakeup(); + /* Never returns. */ } /* For most ARM systems, we have to initialize firmware media source

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Patch merged into coreboot/master: 0004c0d Google/Snow: Remove duplicated SPI1 initialization in bootblock.
by gerrit＠coreboot.org 01 May '13

01 May '13

the following patch was just integrated into master: commit 0004c0deec8d60cf952426746e2d9519f6de38d6 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Apr 30 16:11:32 2013 +0800 Google/Snow: Remove duplicated SPI1 initialization in bootblock. The firmware media source (SPI1) is already initialized by Exynos iROM. There is no need to do it again. Verified by building and booting Google/Snow successfully. Change-Id: I89390506aa825397c0d7e52ad7503f1cb808f7db Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/3147 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed May 1 07:40:36 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:43:31 2013, giving +2 See http://review.coreboot.org/3147 for details. -gerrit

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Patch merged into coreboot/master: 8fc41e1 boot state: run timers on state entry
by gerrit＠coreboot.org 01 May '13

01 May '13

the following patch was just integrated into master: commit 8fc41e1b84301e76921730caa4e6b8e8bf27cc35 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 29 23:22:01 2013 -0500 boot state: run timers on state entry When TIMER_QUEUE is configured on call the timer callbacks on entry into a state but before its entry callbacks. In addition provide a barrier to the following states so that timers are drained before proceeding. This allows for blocking state traversal for key components of boot. BS_OS_RESUME BS_WRITE_TABLES BS_PAYLOAD_LOAD BS_PAYLOAD_BOOT Future functionality consists of evaluating the timer callbacks within the device tree. One example is dev_initialize() as that seems state seems to take 90% of the boot time. The timer callbacks could then be ran in a more granular manner. Change-Id: Idb549ea17c5ec38eb57b4f6f366a1c2183f4a6dd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3159 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed May 1 06:22:52 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:19:52 2013, giving +2 See http://review.coreboot.org/3159 for details. -gerrit

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Patch merged into coreboot/master: 340ca91 coreboot: add timer queue implementation
by gerrit＠coreboot.org 01 May '13

01 May '13

the following patch was just integrated into master: commit 340ca91f18a448e09973341f60bb6f46102d2410 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 30 09:58:12 2013 -0500 coreboot: add timer queue implementation A timer queue provides the mechanism for calling functions in the future by way of a callback. It utilizes the MONOTONIC_TIMER to track time through the boot. The implementation is a min-heap for keeping track of the next-to-expire callback. Change-Id: Ia56bab8444cd6177b051752342f53b53d5f6afc1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3158 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed May 1 06:57:11 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:19:12 2013, giving +2 See http://review.coreboot.org/3158 for details. -gerrit

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Patch merged into coreboot/master: 6b0fb0d boot state: track times for each state
by gerrit＠coreboot.org 01 May '13

01 May '13

the following patch was just integrated into master: commit 6b0fb0dc3c1cb89af52224a1610daf7b9e943aa6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 26 20:54:16 2013 -0500 boot state: track times for each state When the MONOTONIC_TIMER is available track the entry, run, and exit times for each state. It should be noted that the times for states that vector to OS or a payload do not have their times reported. Change-Id: I6af23fe011609e0b1e019f35ee40f1fbebd59c9d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3156 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed May 1 00:17:13 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:16:52 2013, giving +2 See http://review.coreboot.org/3156 for details. -gerrit

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Patch merged into coreboot/master: e850164 tsc: provide monotonic timer
by gerrit＠coreboot.org 01 May '13

01 May '13

the following patch was just integrated into master: commit e850164bac08a5b3b4cd09f587775e68ad1b40c2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 29 22:22:55 2013 -0500 tsc: provide monotonic timer Implement the timer_monotonic_get() using the TSC. Change-Id: I5118da6fb9bccc75d2ce012317612e0ab20a2cac Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3155 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed May 1 01:16:29 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed May 1 07:15:55 2013, giving +2 See http://review.coreboot.org/3155 for details. -gerrit

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coreboot-gerrit May 2013