coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: be2c634 superiotool: Allow to override Makefile variables `CC`, `INSTALL` and `PREFIX`
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit be2c6340b3ce8e48a40724ef8136eb3c80ef4448 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Mar 28 11:44:19 2013 +0100 superiotool: Allow to override Makefile variables `CC`, `INSTALL` and `PREFIX` This way for example a different compiler can easily be used. CC=clang make Change-Id: I50b83554fd4826d00d87e60a30eb1f6a88834397 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2935 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Mar 28 12:27:10 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Mar 29 21:32:48 2013, giving +2 See http://review.coreboot.org/2935 for details. -gerrit

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Patch set updated for coreboot: 6abadf3 exynos5250: Add function for configuring L2 cache
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2949 -gerrit commit 6abadf3b9e2f090a4472b854789f3eed045c82b0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 19:04:58 2013 -0700 exynos5250: Add function for configuring L2 cache This adds a new function to configure L2 cache for the exynos5250 and deprecates the old function. Change-Id: I9562f3301aa1e2911dae3856ab57bb6beec2e224 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 3 -- src/cpu/samsung/exynos5250/cpu.c | 16 +++++++ src/cpu/samsung/exynos5250/cpu.h | 2 + src/cpu/samsung/exynos5250/exynos_cache.c | 80 ------------------------------- 4 files changed, 18 insertions(+), 83 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 961b719..74bc871 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,12 +9,10 @@ bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c -bootblock-y += exynos_cache.c romstage-y += clock.c romstage-y += clock_init.c romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. -romstage-y += exynos_cache.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c @@ -24,7 +22,6 @@ romstage-$(CONFIG_EARLY_CONSOLE) += uart.c #ramstage-y += tzpc_init.c ramstage-y += clock.c ramstage-y += clock_init.c -ramstage-y += exynos_cache.c ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index b6eae46..4bb06e8 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,5 +1,7 @@ #include <console/console.h> #include <device/device.h> +#include <arch/cache.h> +#include <cpu/samsung/exynos5250/cpu.h> #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) @@ -33,3 +35,17 @@ struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") .enable_dev = enable_dev, }; + +void exynos5250_config_l2_cache(void) +{ + uint32_t val; + + /* + * Bit 9 - L2 tag RAM setup (1 cycle) + * Bits 8:6 - L2 tag RAM latency (3 cycles) + * Bit 5 - L2 data RAM setup (1 cycle) + * Bits 2:0 - L2 data RAM latency (3 cycles) + */ + val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); + write_l2ctlr(val); +} diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index 772e591..a356e19 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -118,4 +118,6 @@ /* helper function to map mmio address to peripheral id */ enum periph_id exynos5_get_periph_id(unsigned base_addr); +void exynos5250_config_l2_cache(void); + #endif /* _EXYNOS5250_CPU_H */ diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c deleted file mode 100644 index 2cb918d..0000000 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2012 Samsung Electronics. - * Arun Mankuzhi <arun.m(a)samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <system.h> - -#include <armv7.h> - -enum l2_cache_params { - CACHE_TAG_RAM_SETUP = (1<<9), - CACHE_DATA_RAM_SETUP = (1<<5), - CACHE_TAG_RAM_LATENCY = (2<<6), - CACHE_DATA_RAM_LATENCY = (2<<0) -}; - -/* - * Set L2 cache parameters - */ -static void exynos5_set_l2cache_params(void) -{ - unsigned int val = 0; - - asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); - - val |= CACHE_TAG_RAM_SETUP | - CACHE_DATA_RAM_SETUP | - CACHE_TAG_RAM_LATENCY | - CACHE_DATA_RAM_LATENCY; - - asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); -} - -/* - * Sets L2 cache related parameters before enabling data cache - */ -void v7_outer_cache_enable(void) -{ - exynos5_set_l2cache_params(); -} - -/* stubs so we don't need weak symbols in cache_v7.c */ -void v7_outer_cache_disable(void) -{ -} - -void v7_outer_cache_flush_all(void) -{ -} - -void v7_outer_cache_inval_all(void) -{ -} - -void v7_outer_cache_flush_range(u32 start, u32 end) -{ -} - -void v7_outer_cache_inval_range(u32 start, u32 end) -{ -}

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Patch set updated for coreboot: f465637 snow: explicitly configure L2 cache
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2950 -gerrit commit f465637bb42a04f50b0c56909faf54f6065bf39d Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 19:05:29 2013 -0700 snow: explicitly configure L2 cache This adds a call to explicitly configure L2 cache (though defaults should be set correctly). Change-Id: I120e29c986918c2904a0332e46fcf9f1c5380d85 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/ramstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 1751a1b..9081629 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -21,6 +21,7 @@ #include <cbmem.h> #include <arch/exception.h> #include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> #include <arch/cache.h> @@ -45,6 +46,7 @@ void main(void) /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ + exynos5250_config_l2_cache(); mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);

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Patch merged into coreboot/master: e85f4eb armv7: update sync barrier usage in dcache_op_set_way()
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit e85f4eb1b0f63535ceb36315712a03d7d7f656ac Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 26 21:34:01 2013 -0700 armv7: update sync barrier usage in dcache_op_set_way() This moves the dsb() before the loop to sync any outstanding memory accesses, and adds an isb() after the loop to ensure all outstanding instructions are completed. Change-Id: I1a11b39f104ae780370cfd2db3badcf4e91dc017 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2929 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Mar 27 09:37:00 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 21:12:54 2013, giving +2 See http://review.coreboot.org/2929 for details. -gerrit

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Patch merged into coreboot/master: dc82fc5 wtm2: auto-select CACHE_ROM
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit dc82fc563486794005ada364f498167df9b686d6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 29 14:36:10 2013 -0500 wtm2: auto-select CACHE_ROM The WTM2 board has a fairly static configuration. As such it's been tested to properly handle CACHE_ROM given the number of MTRRs the boards' CPUs supports. Change-Id: Ic67cd1eebce580003dc6b6655cac2b2a92dd1b5f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2964 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 21:08:05 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 21:11:27 2013, giving +2 See http://review.coreboot.org/2964 for details. -gerrit

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Patch merged into coreboot/master: b5146b3 AMD Inagua: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errors
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit b5146b394a11642649d7645be97ad5c5f8e2892e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 11:17:25 2013 +0100 AMD Inagua: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errors Now that the AMD Inagua builds without any warnigs, remove the config option `WARNINGS_ARE_ERRORS` set to no by default from the file `Kconfig` so warnings are treated as errors to prevent code from being added in the future introducing warnings. Change-Id: I0b58bd74b06dc54d180b16d6a207354b5fea0d0f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2953 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 11:50:15 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 21:11:01 2013, giving +2 See http://review.coreboot.org/2953 for details. -gerrit

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Patch merged into coreboot/master: 5d74156 AMD Inagua: broadcom.c: Add missing prototype for `broadcom_init()`
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 5d7415673f93ddac743de71fb2272fccdd7300fb Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 11:07:22 2013 +0100 AMD Inagua: broadcom.c: Add missing prototype for `broadcom_init()` Building the AMD Inagua board, the following warning is thrown. CC mainboard/amd/inagua/get_bus_conf.ramstage.o src/mainboard/amd/inagua/broadcom.c:319:6: warning: no previous prototype for 'broadcom_init' [-Wmissing-prototypes] This warning was introduced by commit 3926b4c5. commit 3926b4c520e74da9dc22e3d136a8a178483e0d25 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Fri Mar 1 19:41:41 2013 +0100 AMD Inagua: add GEC firmware, document Broadcom BCM57xx Selfboot Patch format Reviewed-on: http://review.coreboot.org/2831 Adding the prototype to `broadcom.c` and removing it from `mainboard.c` fixes the warning. Change-Id: I1da0c4e972e129047dd8230d573f1c43fd71eb20 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2952 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 11:36:26 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 21:10:34 2013, giving +2 See http://review.coreboot.org/2952 for details. -gerrit

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Patch merged into coreboot/master: 6983a68 inteltool: Support GPIO registers on Cougar/Panther Point
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 6983a6829ab20f31f351f39e6421710935c6a744 Author: Nico Huber <nico.h(a)gmx.de> Date: Fri Mar 29 18:08:13 2013 +0100 inteltool: Support GPIO registers on Cougar/Panther Point This adds the GPIO register definitions for Intel's Cougar Point and Panther Point platform controller hubs (PCH). All information is taken from the public specifications in [1] and [2]. I've tested it with an H77 PCH. NM70 is missing in [1]. Therefore, I didn't add it here. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 Change-Id: I31711e24f852e68b3c113e3bd9243dc7e89ac197 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/2961 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 19:10:13 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 21:07:55 2013, giving +2 See http://review.coreboot.org/2961 for details. -gerrit

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Patch merged into coreboot/master: 76d6049 inteltool: Add definitions for Cougar/Panther Point PCI IDs
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 76d60494ef97399d4233f398be5814574f1d4a1b Author: Nico Huber <nico.h(a)gmx.de> Date: Fri Mar 29 17:57:15 2013 +0100 inteltool: Add definitions for Cougar/Panther Point PCI IDs This adds correspondings #defines for the PCI IDs of the LPC device on Intel's Cougar Point and Panther Point platform controller hubs. Those will be used more in later commits. I've checked all those IDs against the specification updates [1] and [2]. [1] Intel 6 Series Chipset and Intel C200 Series Chipset Specification Update Document-Number: 324646-019 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) Family - Datasheet Specification Update Document-Number: 326777-010 Change-Id: Ibef5a30d283c568c345eb8d8149723e7a3049272 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/2960 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 18:56:25 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 21:07:29 2013, giving +2 See http://review.coreboot.org/2960 for details. -gerrit

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Patch merged into coreboot/master: 2c2a85f google boards: auto-select CACHE_ROM
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 2c2a85fc6d107265716bad930e7505fc87a52a1f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 29 14:33:03 2013 -0500 google boards: auto-select CACHE_ROM Automatically select CACHE_ROM for all Google boards. Tested by generating a config for the link board. CACHE_ROM was selected and was unable to unselect it using 'make oldconfig'. Change-Id: I8e34207e3929a020bb0280657f95ba7a000ad024 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2963 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 29 20:54:18 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Mar 29 21:01:51 2013, giving +2 See http://review.coreboot.org/2963 for details. -gerrit

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coreboot-gerrit March 2013