coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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443 discussions

Patch merged into coreboot/master: 1877cee armv7: change some unsigned ints to uint32_t
by gerrit＠coreboot.org 30 Mar '13

30 Mar '13

the following patch was just integrated into master: commit 1877ceed212b586f13277b4b2057598d39b78894 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Mar 29 15:40:34 2013 -0700 armv7: change some unsigned ints to uint32_t Use register-sized types in case the inline assembler doesn't do so automatically. Change-Id: I3202ba972ef2548323fe557f45dc4b0b1cf6c818 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2983 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Gabe Black <gabe.black(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Sat Mar 30 03:30:46 2013, giving +1 See http://review.coreboot.org/2983 for details. -gerrit

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New patch to review for coreboot: 88b7ef0 spkmodem console
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2987 -gerrit commit 88b7ef04e6b0bde33d20c8bea41991f06cdd8aa5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 02:02:13 2013 +0100 spkmodem console Change-Id: Ie497e4c8da05001ffe67c4a541bd24aa859ac0e2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 7 +++++++ src/console/Kconfig | 6 ++++++ src/console/Makefile.inc | 1 + src/console/console.c | 4 ++++ src/include/console/console.h | 3 +++ src/lib/Makefile.inc | 3 +++ 6 files changed, 24 insertions(+) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index f53f5a9..2013bb7 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -28,6 +28,10 @@ #if CONFIG_CONSOLE_NE2K #include <console/ne2k.h> #endif +#if CONFIG_SPKMODEM +#include <console/spkmodem.h> +#endif + void console_tx_byte(unsigned char byte) { @@ -52,6 +56,9 @@ void console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_CBMEM cbmemc_tx_byte(byte); #endif +#if CONFIG_SPKMODEM + spkmodem_tx_byte(byte); +#endif } void console_tx_flush(void) diff --git a/src/console/Kconfig b/src/console/Kconfig index d2cff57..a6f130a 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -119,6 +119,12 @@ config TTYS0_LCS default 3 depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM +config SPKMODEM + bool "Spkmodem (console on speaker) console output" + default n + help + Send coreboot debug output through speaker + # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. config HAVE_USBDEBUG def_bool n diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 40bf357..15034cb 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -20,6 +20,7 @@ bootblock-y += die.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c +ramstage-$(CONFIG_SPKMODEM) += spkmodem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug_console.c ramstage-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c diff --git a/src/console/console.c b/src/console/console.c index 34a26ec..6069892 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -119,6 +119,10 @@ void console_init(void) #if CONFIG_CONSOLE_CBMEM cbmemc_init(); #endif +#if CONFIG_SPKMODEM + spkmodem_init(); +#endif + static const char console_test[] = "\n\ncoreboot-" COREBOOT_VERSION diff --git a/src/include/console/console.h b/src/include/console/console.h index 0b63644..d320093 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -36,6 +36,9 @@ #if CONFIG_CONSOLE_CBMEM #include <console/cbmem_console.h> #endif +#if CONFIG_SPKMODEM +#include <console/spkmodem.h> +#endif #ifndef __PRE_RAM__ unsigned char console_rx_byte(void); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9d3588e..e8b1485 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -47,6 +47,8 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c +romstage-$(CONFIG_SPKMODEM) += spkmodem.c + romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c romstage-y += compute_ip_checksum.c @@ -81,6 +83,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c +ramstage-$(CONFIG_SPKMODEM) += spkmodem.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c

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New patch to review for coreboot: adb83e8 inteltool: Add Cougar/Panther Point IDs to rootcmplx.c
by Nico Huber 30 Mar '13

30 Mar '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2986 -gerrit commit adb83e8bc9c678f6c9613847b3e893eef46ab016 Author: Nico Huber <nico.h(a)gmx.de> Date: Fri Mar 29 19:08:39 2013 +0100 inteltool: Add Cougar/Panther Point IDs to rootcmplx.c This adds the PCI IDs of Intel's Cougar Point and Panther Point platform controller hubs (PCH) to the dumping of the root complex configuration under the root complex base address (RCBA). Those PCHs are handled exactly as the older ICHs which can be seen in [1] and [2]. I've tested dumping with an H77 PCH. NM70 is missing in [1]. Therefore, I didn't add it here. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 Change-Id: I2296caae57e614171300362d41715deecec77762 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/inteltool/rootcmplx.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index a478731..7cc55de 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -47,6 +47,35 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: case PCI_DEVICE_ID_INTEL_I63XX: + case PCI_DEVICE_ID_INTEL_Z68: + case PCI_DEVICE_ID_INTEL_P67: + case PCI_DEVICE_ID_INTEL_UM67: + case PCI_DEVICE_ID_INTEL_HM65: + case PCI_DEVICE_ID_INTEL_H67: + case PCI_DEVICE_ID_INTEL_HM67: + case PCI_DEVICE_ID_INTEL_Q65: + case PCI_DEVICE_ID_INTEL_QS67: + case PCI_DEVICE_ID_INTEL_Q67: + case PCI_DEVICE_ID_INTEL_QM67: + case PCI_DEVICE_ID_INTEL_B65: + case PCI_DEVICE_ID_INTEL_C202: + case PCI_DEVICE_ID_INTEL_C204: + case PCI_DEVICE_ID_INTEL_C206: + case PCI_DEVICE_ID_INTEL_H61: + case PCI_DEVICE_ID_INTEL_Z77: + case PCI_DEVICE_ID_INTEL_Z75: + case PCI_DEVICE_ID_INTEL_Q77: + case PCI_DEVICE_ID_INTEL_Q75: + case PCI_DEVICE_ID_INTEL_B75: + case PCI_DEVICE_ID_INTEL_H77: + case PCI_DEVICE_ID_INTEL_C216: + case PCI_DEVICE_ID_INTEL_QM77: + case PCI_DEVICE_ID_INTEL_QS77: + case PCI_DEVICE_ID_INTEL_HM77: + case PCI_DEVICE_ID_INTEL_UM77: + case PCI_DEVICE_ID_INTEL_HM76: + case PCI_DEVICE_ID_INTEL_HM75: + case PCI_DEVICE_ID_INTEL_HM70: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH:

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New patch to review for coreboot: 9406a77 inteltool: Support PM registers on Cougar/Panther Point
by Nico Huber 30 Mar '13

30 Mar '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2985 -gerrit commit 9406a774a07429eb51923e357c2f90999ef7c7c6 Author: Nico Huber <nico.h(a)gmx.de> Date: Fri Mar 29 19:00:37 2013 +0100 inteltool: Support PM registers on Cougar/Panther Point This adds the power management register definitions for Intel's Cougar Point and Panther Point platform controller hubs (PCH). The definitions are actually a subset of the older ICH10R registers: I've added just those that are mentioned in the public specifications in [1] and [2]. I've tested dumping with an H77 PCH. NM70 is missing in [1]. Therefore, I didn't add it here. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/inteltool/powermgt.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 71dfc49..306e20d 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -21,6 +21,57 @@ #include <stdio.h> #include "inteltool.h" +static const io_register_t pch_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK + { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 + { 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK + { 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "RESERVED" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK + { 0x28, 8, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8 + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x38, 2, "ALT_GP_SMI_EN" }, + { 0x3a, 2, "ALT_GP_SMI_STS" }, + { 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control; + { 0x3d, 1, "RESERVED" }, + { 0x3e, 2, "RESERVED" }, + { 0x40, 2, "RESERVED" }, + { 0x42, 1, "GPE_CNTL" }, + { 0x43, 1, "RESERVED" }, + { 0x44, 2, "DEVACT_STS" }, // Device Activity Status + { 0x46, 2, "RESERVED" }, + { 0x48, 4, "RESERVED" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 1, "PM2_CNT" }, + { 0x51, 1, "RESERVED" }, + { 0x52, 2, "RESERVED" }, + { 0x54, 4, "RESERVED" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + /* Here start the TCO registers */ + { 0x60, 2, "TCO_RLD" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 2, "TCO_MESSAGE" }, + { 0x6e, 1, "TCO_WDCNT" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 1, "SW_IRQ_GEN" }, + { 0x71, 1, "RESERVED" }, + { 0x72, 2, "TCO_TMR" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + static const io_register_t ich10_pm_registers[] = { { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 @@ -605,6 +656,39 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) printf("\n============= PMBASE ============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_Z68: + case PCI_DEVICE_ID_INTEL_P67: + case PCI_DEVICE_ID_INTEL_UM67: + case PCI_DEVICE_ID_INTEL_HM65: + case PCI_DEVICE_ID_INTEL_H67: + case PCI_DEVICE_ID_INTEL_HM67: + case PCI_DEVICE_ID_INTEL_Q65: + case PCI_DEVICE_ID_INTEL_QS67: + case PCI_DEVICE_ID_INTEL_Q67: + case PCI_DEVICE_ID_INTEL_QM67: + case PCI_DEVICE_ID_INTEL_B65: + case PCI_DEVICE_ID_INTEL_C202: + case PCI_DEVICE_ID_INTEL_C204: + case PCI_DEVICE_ID_INTEL_C206: + case PCI_DEVICE_ID_INTEL_H61: + case PCI_DEVICE_ID_INTEL_Z77: + case PCI_DEVICE_ID_INTEL_Z75: + case PCI_DEVICE_ID_INTEL_Q77: + case PCI_DEVICE_ID_INTEL_Q75: + case PCI_DEVICE_ID_INTEL_B75: + case PCI_DEVICE_ID_INTEL_H77: + case PCI_DEVICE_ID_INTEL_C216: + case PCI_DEVICE_ID_INTEL_QM77: + case PCI_DEVICE_ID_INTEL_QS77: + case PCI_DEVICE_ID_INTEL_HM77: + case PCI_DEVICE_ID_INTEL_UM77: + case PCI_DEVICE_ID_INTEL_HM76: + case PCI_DEVICE_ID_INTEL_HM75: + case PCI_DEVICE_ID_INTEL_HM70: + pmbase = pci_read_word(sb, 0x40) & 0xff80; + pm_registers = pch_pm_registers; + size = ARRAY_SIZE(pch_pm_registers); + break; case PCI_DEVICE_ID_INTEL_ICH10R: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = ich10_pm_registers;

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New patch to review for coreboot: 4ce1ef5 ASRock E350M1: Provide HD Audio verb table for Realtek ALC892
by Paul Menzel 30 Mar '13

30 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2984 -gerrit commit 4ce1ef5b5cf64e7457e2dd86db4c1cbdea959f55 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 21:41:56 2013 +0100 ASRock E350M1: Provide HD Audio verb table for Realtek ALC892 Use the same HD Audio [1] verb table for the Realtek ALC892 audio chip [2] as the proprietary vendor BIOS version P1.60 sets up [2], which Linux exposes under its virtual filesystem sysfs. /sys/class/sound/hwC1D0/init_pin_configs The difference between the verb table between the vendor BIOS and coreboot is shown in the following output [3]. (Beware of the ordering!) $ wdiff vendorbios_vt coreboot_vt # init_pin_config 0x11 [-0x411111f0-] {+0x411110f0+} 0x12 0x411111f0 0x14 [-0x01014010-] {+0x01014030+} 0x15 [-0x01011012-] {+0x01011031+} 0x16 [-0x01016011-] {+0x01016032+} 0x17 [-0x411111f0-] {+0x01012033+} 0x18 [-0x01a19840-] {+0x01a19850+} 0x19 [-0x02a19950-] {+0x02a19c80+} 0x1a [-0x0181304f-] {+0x01813051+} 0x1b [-0x02214120-] {+0x02214c40+} 0x1c [-0x411111f0-] {+0x9933105f+} 0x1d [-0x4005e601-] {+0x00000100+} 0x1e [-0x01452130-] {+0x01441070+} 0x1f [-0x411111f0-] {+0x41c46060+} Note, that currently no problems are know with the default verb table used with coreboot. Sound over HDMI works fine and stereo out too. More thorough tests would need to be performed to test each connector for the front and back panel. Additionally, I was not able to find out, where the values for the default verb table under coreboot come from. Searching for »6032« – a substring used in the default table – did not yield any results in coreboot and the Linux kernel (ALSA). Additionally the script `alsa-info.sh` [5] seems to be able to decode the table. The differences of the section HDA-Intel Codec information are pasted to the comments of the Gerrit page, where this patch is reviewed on. [1] http://en.wikipedia.org/wiki/Intel_High_Definition_Audio [2] http://www.realtek.com.tw/products/productsView.aspx?Langid=1&PNid=24&PFid=… [3] http://www.coreboot.org/pipermail/coreboot/2013-March/075559.html [4] http://mailman.alsa-project.org/pipermail/alsa-devel/2013-March/060717.html [5] http://alsa-project.org/main/index.php/Help_To_Debug Change-Id: I03cb1ffc86554ebf55c355f5363f490a3ca58260 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/platform_cfg.h | 39 ++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 24a66dd..a54e561 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -227,6 +227,45 @@ */ #define GEC_CONFIG 0 +static const CODECENTRY e350m1_codec_alc892[] = /* Realtek ALC892 */ +{ + /* + * The comments after each entry are taken from the block + * diagram (figure 1) in the ALC892 datasheet + * (Rev. 1.3, Track ID: JATR-2265-11) on page 5 which is available for download + * on the Realtek Web site. + */ + + /* NID, PinConfig (Verbs 71F..C) */ + {0x11, 0x411111F0}, /* S/PDIF-OUT 2 */ + {0x12, 0x411111F0}, /* DMIC-L/R */ + {0x14, 0x01014010}, /* FRONT (Port-D) */ + {0x15, 0x01011012}, /* SURR (Port-A) */ + {0x16, 0x01016011}, /* CEN/LFE (Port-G) */ + {0x17, 0x411111F0}, /* SIDESURR (Port-H) */ + {0x18, 0x01A19840}, /* MIC1 (Port-B) */ + {0x19, 0x02A19950}, /* MIC2 (Port-F) */ + {0x1A, 0x0181304F}, /* LINE1 (Port-C) */ + {0x1B, 0x02214120}, /* LINE2 (Port-E) */ + {0x1C, 0x411111F0}, /* CD-IN */ + {0x1D, 0x4005E601}, /* BEEP-IN */ + {0x1E, 0x01452130}, /* S/PDIF-OUT */ + {0x1F, 0x411111F0}, /* S/PDIF-IN */ + {0xff, 0xffffffff} /* end of table */ +}; + +static const CODECTBLLIST codec_tablelist[] = +{ + {0x10ec0892, (CODECENTRY*)&e350m1_codec_alc892[0]}, + {0xFFFFFFFF, (CODECENTRY*)0xFFFFFFFFL} +}; + +/** + * @def AZALIA_OEM_VERB_TABLE + * Mainboard specific codec verb table list + */ +#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) + /** * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address */

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Patch set updated for coreboot: d68a434 armv7: change some unsigned ints to uint32_t
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2983 -gerrit commit d68a4348e91afe99eb7c311458d33ace228e2793 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Mar 29 15:40:34 2013 -0700 armv7: change some unsigned ints to uint32_t Use register-sized types in case the inline assembler doesn't do so automatically. Change-Id: I3202ba972ef2548323fe557f45dc4b0b1cf6c818 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/arch/cache.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 3e0ff2e..1db86dc 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -220,9 +220,9 @@ static inline void write_csselr(uint32_t val) } /* read L2 control register (L2CTLR) */ -static inline unsigned int read_l2ctlr(void) +static inline uint32_t read_l2ctlr(void) { - unsigned int val = 0; + uint32_t val = 0; asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); return val; } @@ -239,9 +239,9 @@ static inline void write_l2ctlr(uint32_t val) } /* read system control register (SCTLR) */ -static inline unsigned int read_sctlr(void) +static inline uint32_t read_sctlr(void) { - unsigned int val; + uint32_t val; asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val)); return val; }

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New patch to review for coreboot: e11f15d armv7: change some unsigned ints to uint32_t
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2983 -gerrit commit e11f15d9c6c21901048d3b8bd7f714b89b65e015 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Mar 29 15:40:34 2013 -0700 armv7: change some unsigned ints to uint32_t Use register-sized types in case the inline assembler somehow doesn't. Change-Id: I3202ba972ef2548323fe557f45dc4b0b1cf6c818 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/arch/cache.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 3e0ff2e..1db86dc 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -220,9 +220,9 @@ static inline void write_csselr(uint32_t val) } /* read L2 control register (L2CTLR) */ -static inline unsigned int read_l2ctlr(void) +static inline uint32_t read_l2ctlr(void) { - unsigned int val = 0; + uint32_t val = 0; asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); return val; } @@ -239,9 +239,9 @@ static inline void write_l2ctlr(uint32_t val) } /* read system control register (SCTLR) */ -static inline unsigned int read_sctlr(void) +static inline uint32_t read_sctlr(void) { - unsigned int val; + uint32_t val; asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val)); return val; }

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Patch set updated for coreboot: 9cf8910 x86: Drop BOARD_HAS_FADT
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2940 -gerrit commit 9cf8910b958d4f680d1b2d2259a023e22955d6ab Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 28 16:30:56 2013 +0200 x86: Drop BOARD_HAS_FADT There is a wildcard rule to include mainboard/fadt.c. Change-Id: I7f59d6b241c683b62c2c41c5795e45184882635e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/Makefile.inc | 3 --- src/mainboard/google/butterfly/Kconfig | 1 - src/mainboard/google/link/Kconfig | 1 - src/mainboard/google/parrot/Kconfig | 1 - src/mainboard/google/stout/Kconfig | 1 - src/mainboard/intel/baskingridge/Kconfig | 1 - src/mainboard/intel/wtm1/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/mainboard/roda/rk9/Kconfig | 1 - 9 files changed, 11 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index dec0b3f..fbf1cba 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -181,9 +181,6 @@ endif ifeq ($(CONFIG_ACPI_SSDTX_NUM),5) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt5.asl endif -ifeq ($(CONFIG_BOARD_HAS_FADT),y) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c -endif endif ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 0813042..b0ebe78 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_ENE_KB3940Q - select BOARD_HAS_FADT select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index c171390..9d8b779 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select BOARD_HAS_FADT select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 96f1b4f..d400c88 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_COMPAL_ENE932 - select BOARD_HAS_FADT select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index f6ac5b9..a15d933 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_IT8518 - select BOARD_HAS_FADT select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 830c650..2463079 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select BOARD_ROMSIZE_KB_8192 - select BOARD_HAS_FADT select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/wtm1/Kconfig b/src/mainboard/intel/wtm1/Kconfig index 7485e10..65db03f 100644 --- a/src/mainboard/intel/wtm1/Kconfig +++ b/src/mainboard/intel/wtm1/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 - select BOARD_HAS_FADT select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 16b5373..e5438ff 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 - select BOARD_HAS_FADT select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index dd9e940..4bf9088 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVERS_GENERIC_IOAPIC select HAVE_MP_TABLE select CARDBUS_PLUGIN_SUPPORT - select BOARD_HAS_FADT select HAVE_ACPI_TABLES #select HAVE_ACPI_RESUME select EC_ACPI

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Patch merged into coreboot/master: 5877935 armv7: remove loop from dcache_mmu_disable()
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 58779358362ef0c9ed433c310416a93c8b9c9211 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Mar 29 13:40:09 2013 -0700 armv7: remove loop from dcache_mmu_disable() dcache_mmu_disable() no longer needs to have its own iterative loop to select each cache level of cache since dcache_clean_invalidate_all() does that now. Change-Id: I5ca273f98943981b943c1c1622f4574d7133fb50 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2967 Reviewed-by: Gabe Black <gabe.black(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Mar 29 22:38:04 2013, giving +1 See http://review.coreboot.org/2967 for details. -gerrit

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New patch to review for coreboot: 1bd852b link: select write-combining memory for graphics
by Aaron Durbin 29 Mar '13

29 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2982 -gerrit commit 1bd852b247db46dff4302f8020930b46a83a3c87 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 29 16:38:01 2013 -0500 link: select write-combining memory for graphics Auto-select marking the graphics memory as write-combining. Change-Id: I0b913f0b318bf57275643d3cfb5bc54ca8a005f5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/link/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index c171390..a2e4ac3 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT + select MARK_GRAPHICS_MEM_WRCOMB config MAINBOARD_DIR string

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coreboot-gerrit March 2013