coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: d546254 spkmodem console
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2987 -gerrit commit d5462547df60fdd1d7459c697f9acde1e9ed1d6b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 02:02:13 2013 +0100 spkmodem console Change-Id: Ie497e4c8da05001ffe67c4a541bd24aa859ac0e2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 7 ++ src/console/Kconfig | 6 ++ src/console/Makefile.inc | 1 + src/console/console.c | 4 ++ src/console/spkmodem_console.c | 46 +++++++++++++ src/include/console/console.h | 3 + src/include/console/spkmodem.h | 7 ++ src/lib/Makefile.inc | 3 + src/lib/spkmodem.c | 128 ++++++++++++++++++++++++++++++++++++ 9 files changed, 205 insertions(+) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index f53f5a9..2013bb7 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -28,6 +28,10 @@ #if CONFIG_CONSOLE_NE2K #include <console/ne2k.h> #endif +#if CONFIG_SPKMODEM +#include <console/spkmodem.h> +#endif + void console_tx_byte(unsigned char byte) { @@ -52,6 +56,9 @@ void console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_CBMEM cbmemc_tx_byte(byte); #endif +#if CONFIG_SPKMODEM + spkmodem_tx_byte(byte); +#endif } void console_tx_flush(void) diff --git a/src/console/Kconfig b/src/console/Kconfig index d2cff57..6251589 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -119,6 +119,12 @@ config TTYS0_LCS default 3 depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM +config SPKMODEM + bool "spkmodem (console on speaker) console output" + default n + help + Send coreboot debug output through speaker + # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. config HAVE_USBDEBUG def_bool n diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 40bf357..15034cb 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -20,6 +20,7 @@ bootblock-y += die.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c +ramstage-$(CONFIG_SPKMODEM) += spkmodem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug_console.c ramstage-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c diff --git a/src/console/console.c b/src/console/console.c index 34a26ec..6069892 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -119,6 +119,10 @@ void console_init(void) #if CONFIG_CONSOLE_CBMEM cbmemc_init(); #endif +#if CONFIG_SPKMODEM + spkmodem_init(); +#endif + static const char console_test[] = "\n\ncoreboot-" COREBOOT_VERSION diff --git a/src/console/spkmodem_console.c b/src/console/spkmodem_console.c new file mode 100644 index 0000000..814a1ac --- /dev/null +++ b/src/console/spkmodem_console.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/spkmodem.h> + +static void spkmodem_tx_flush(void) +{ +} + +static unsigned char spkmodem_rx_byte(void) +{ + return 0; +} + +static int spkmodem_tst_byte(void) +{ + return 0; +} + + +static const struct console_driver spkmodem_console __console = { + .init = spkmodem_init, + .tx_byte = spkmodem_tx_byte, + .tx_flush = spkmodem_tx_flush, + .rx_byte = spkmodem_rx_byte, + .tst_byte = spkmodem_tst_byte, +}; + diff --git a/src/include/console/console.h b/src/include/console/console.h index 0b63644..d320093 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -36,6 +36,9 @@ #if CONFIG_CONSOLE_CBMEM #include <console/cbmem_console.h> #endif +#if CONFIG_SPKMODEM +#include <console/spkmodem.h> +#endif #ifndef __PRE_RAM__ unsigned char console_rx_byte(void); diff --git a/src/include/console/spkmodem.h b/src/include/console/spkmodem.h new file mode 100644 index 0000000..450dbe8 --- /dev/null +++ b/src/include/console/spkmodem.h @@ -0,0 +1,7 @@ +#ifndef SPKMODEM_H +#define SPKMODEM_H 1 + +void spkmodem_init(void); +void spkmodem_tx_byte(unsigned char c); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9d3588e..e8b1485 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -47,6 +47,8 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c +romstage-$(CONFIG_SPKMODEM) += spkmodem.c + romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c romstage-y += compute_ip_checksum.c @@ -81,6 +83,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c +ramstage-$(CONFIG_SPKMODEM) += spkmodem.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c diff --git a/src/lib/spkmodem.c b/src/lib/spkmodem.c new file mode 100644 index 0000000..89773b1 --- /dev/null +++ b/src/lib/spkmodem.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <console/spkmodem.h> +#include <cpu/x86/tsc.h> + +#define SPEAKER_PIT_FREQUENCY 0x1234dd + + +enum { + PIT_COUNTER_0 = 0x40, + PIT_COUNTER_1 = 0x41, + PIT_COUNTER_2 = 0x42, + PIT_CTRL = 0x43, + PIT_SPEAKER_PORT = 0x61, +}; + + +enum { + PIT_SPK_TMR2 = 0x01, + PIT_SPK_DATA = 0x02, + PIT_SPK_TMR2_LATCH = 0x20 +}; + +enum { + PIT_CTRL_SELECT_MASK = 0xc0, + PIT_CTRL_SELECT_0 = 0x00, + PIT_CTRL_SELECT_1 = 0x40, + PIT_CTRL_SELECT_2 = 0x80, + + PIT_CTRL_READLOAD_MASK= 0x30, + PIT_CTRL_COUNTER_LATCH = 0x00, + PIT_CTRL_READLOAD_LSB = 0x10, + PIT_CTRL_READLOAD_MSB = 0x20, + PIT_CTRL_READLOAD_WORD = 0x30, + + PIT_CTRL_MODE_MASK = 0x0e, + PIT_CTRL_INTR_ON_TERM = 0x00, + PIT_CTRL_PROGR_ONE_SHOT = 0x02, + + PIT_CTRL_RATE_GEN = 0x04, + + PIT_CTRL_SQUAREWAVE_GEN = 0x06, + PIT_CTRL_SOFTSTROBE = 0x08, + + PIT_CTRL_HARDSTROBE = 0x0a, + + + PIT_CTRL_COUNT_MASK = 0x01, + PIT_CTRL_COUNT_BINARY = 0x00, + PIT_CTRL_COUNT_BCD = 0x01 +}; + + +static void +make_tone (uint16_t freq_count, unsigned int duration) +{ + outb (PIT_CTRL_SELECT_2 + | PIT_CTRL_READLOAD_WORD + | PIT_CTRL_SQUAREWAVE_GEN + | PIT_CTRL_COUNT_BINARY, PIT_CTRL); + + outb (freq_count & 0xff, PIT_COUNTER_2); + + outb ((freq_count >> 8) & 0xff, PIT_COUNTER_2); + + outb (inb (PIT_SPEAKER_PORT) + | PIT_SPK_TMR2 | PIT_SPK_DATA, + PIT_SPEAKER_PORT); + + for (; duration; duration--) { + unsigned short counter, previous_counter = 0xffff; + while (1) { + counter = inb (PIT_COUNTER_2); + counter |= ((uint16_t) inb (PIT_COUNTER_2)) << 8; + if (counter > previous_counter) + { + previous_counter = counter; + break; + } + previous_counter = counter; + } + } +} + +void spkmodem_tx_byte(unsigned char c) +{ + int i; + + make_tone (SPEAKER_PIT_FREQUENCY / 200, 4); + for (i = 7; i >= 0; i--) { + if ((c >> i) & 1) + make_tone (SPEAKER_PIT_FREQUENCY / 2000, 20); + else + make_tone (SPEAKER_PIT_FREQUENCY / 4000, 40); + make_tone (SPEAKER_PIT_FREQUENCY / 1000, 10); + } + make_tone (SPEAKER_PIT_FREQUENCY / 200, 0); +} + +void spkmodem_init(void) +{ + /* Some cards need time to come online. Output some message to get it started. */ + spkmodem_tx_byte('S'); + spkmodem_tx_byte('P'); + spkmodem_tx_byte('K'); + spkmodem_tx_byte('\r'); + spkmodem_tx_byte('\n'); +}

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Patch set updated for coreboot: 8b7337e Don't attempt to use null pointer (happens when no cpu_microcode_blob.bin is available) as microcode update
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2990 -gerrit commit 8b7337e8f43c5d3536b8556116406e207c05aea3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:04:23 2013 +0100 Don't attempt to use null pointer (happens when no cpu_microcode_blob.bin is available) as microcode update Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/microcode/microcode.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index d908c25..0cf480d 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -130,6 +130,9 @@ const void *intel_microcode_find(void) CBFS_TYPE_MICROCODE); #endif + /* No need for explicit error message since the user already gets + "file not found" from cbfs. + */ if (!microcode_updates) return microcode_updates; @@ -202,6 +205,9 @@ void intel_update_microcode(const void *microcode_updates) const char *c; msr_t msr; + if (!microcode_updates) + return; + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0;

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Patch set updated for coreboot: 73125e1 Don't attempt to use null pointer (happens when no cpu_microcode_blob.bin is available) as microcode update
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2990 -gerrit commit 73125e1648e82f9b0cbe3c5e6c40a7aa3a798995 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:04:23 2013 +0100 Don't attempt to use null pointer (happens when no cpu_microcode_blob.bin is available) as microcode update Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/microcode/microcode.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index d908c25..327559b 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -202,6 +202,9 @@ void intel_update_microcode(const void *microcode_updates) const char *c; msr_t msr; + if (!microcode_updates) + return; + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0;

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Patch set updated for coreboot: 1a39973 Don't output trailing garbage for cbmemc
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2991 -gerrit commit 1a399731c7dfe35d7e2665e251850e3e5cd6bd7d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:15:12 2013 +0100 Don't output trailing garbage for cbmemc Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/cbmem/cbmem.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index bc6bd6b..f47db1d 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -308,12 +308,21 @@ static void dump_timestamps(void) unmap_memory(); } +static const char *future_ngettext (const char *sing, const char *plural, + unsigned long int n) +{ + if (n == 1) + return sing; + return plural; +} + /* dump the cbmem console */ static void dump_console(void) { void *console_p; char *console_c; uint32_t size; + uint32_t cursor; if (console.tag != LB_TAG_CBMEM_CONSOLE) { fprintf(stderr, "No console found in coreboot table.\n"); @@ -328,6 +337,12 @@ static void dump_console(void) * Hence we have to add 8 to get to the actual console string. */ size = *(uint32_t *)console_p; + cursor = *(uint32_t *) (console_p + 4); + /* Cursor continues to go on even after no more data fits in + the buffer but the data is dropped in this case. + */ + if (size > cursor) + size = cursor; console_c = malloc(size + 1); if (!console_c) { fprintf(stderr, "Not enough memory for console.\n"); @@ -337,7 +352,12 @@ static void dump_console(void) memcpy(console_c, console_p + 8, size); console_c[size] = 0; - printf("%s", console_c); + printf("%s\n", console_c); + if (size < cursor) + /* Make it easy to use ng*/ + printf (future_ngettext ("1 byte lost\n" : + "%d bytes lost\n", cursor - size), + cursor - size); free(console_c);

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New patch to review for coreboot: c98ba8d Don't output trailing garbage for cbmemc
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2991 -gerrit commit c98ba8d709dc81889d5318f7f79167b725a23b99 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:15:12 2013 +0100 Don't output trailing garbage for cbmemc Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/cbmem/cbmem.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index bc6bd6b..56c7237 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -328,6 +328,8 @@ static void dump_console(void) * Hence we have to add 8 to get to the actual console string. */ size = *(uint32_t *)console_p; + if (size > *(uint32_t *) (console_p + 4)) + size = *(uint32_t *) (console_p + 4); console_c = malloc(size + 1); if (!console_c) { fprintf(stderr, "Not enough memory for console.\n"); @@ -337,7 +339,9 @@ static void dump_console(void) memcpy(console_c, console_p + 8, size); console_c[size] = 0; - printf("%s", console_c); + printf("%s\n", console_c); + if (size < *(uint32_t *) (console_p + 4)) + printf ("%dB lost\n", *(uint32_t *) (console_p + 4) - size); free(console_c);

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New patch to review for coreboot: 4feff8e Don't attempt to use null pointer (happens when no update is available) as microcode update
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2990 -gerrit commit 4feff8eed45d70fe1aec65dcadf83fbce7297b6b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:04:23 2013 +0100 Don't attempt to use null pointer (happens when no update is available) as microcode update Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/microcode/microcode.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index d908c25..327559b 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -202,6 +202,9 @@ void intel_update_microcode(const void *microcode_updates) const char *c; msr_t msr; + if (!microcode_updates) + return; + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0;

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New patch to review for coreboot: c351565 spkmodem console
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2989 -gerrit commit c351565627554eb0ff9ff3dcc84ee93f6245ab2b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 02:02:13 2013 +0100 spkmodem console Change-Id: Id1e1ffa8fde8d86b776ed2ac1b51d05bce13aa26 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 7 ++ src/console/Kconfig | 6 ++ src/console/Makefile.inc | 1 + src/console/console.c | 4 ++ src/console/spkmodem_console.c | 46 +++++++++++++ src/include/console/console.h | 3 + src/include/console/spkmodem.h | 7 ++ src/lib/Makefile.inc | 3 + src/lib/spkmodem.c | 128 ++++++++++++++++++++++++++++++++++++ 9 files changed, 205 insertions(+) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index f53f5a9..2013bb7 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -28,6 +28,10 @@ #if CONFIG_CONSOLE_NE2K #include <console/ne2k.h> #endif +#if CONFIG_SPKMODEM +#include <console/spkmodem.h> +#endif + void console_tx_byte(unsigned char byte) { @@ -52,6 +56,9 @@ void console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_CBMEM cbmemc_tx_byte(byte); #endif +#if CONFIG_SPKMODEM + spkmodem_tx_byte(byte); +#endif } void console_tx_flush(void) diff --git a/src/console/Kconfig b/src/console/Kconfig index d2cff57..6251589 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -119,6 +119,12 @@ config TTYS0_LCS default 3 depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM +config SPKMODEM + bool "spkmodem (console on speaker) console output" + default n + help + Send coreboot debug output through speaker + # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. config HAVE_USBDEBUG def_bool n diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 40bf357..15034cb 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -20,6 +20,7 @@ bootblock-y += die.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c +ramstage-$(CONFIG_SPKMODEM) += spkmodem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug_console.c ramstage-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c diff --git a/src/console/console.c b/src/console/console.c index 34a26ec..6069892 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -119,6 +119,10 @@ void console_init(void) #if CONFIG_CONSOLE_CBMEM cbmemc_init(); #endif +#if CONFIG_SPKMODEM + spkmodem_init(); +#endif + static const char console_test[] = "\n\ncoreboot-" COREBOOT_VERSION diff --git a/src/console/spkmodem_console.c b/src/console/spkmodem_console.c new file mode 100644 index 0000000..814a1ac --- /dev/null +++ b/src/console/spkmodem_console.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/spkmodem.h> + +static void spkmodem_tx_flush(void) +{ +} + +static unsigned char spkmodem_rx_byte(void) +{ + return 0; +} + +static int spkmodem_tst_byte(void) +{ + return 0; +} + + +static const struct console_driver spkmodem_console __console = { + .init = spkmodem_init, + .tx_byte = spkmodem_tx_byte, + .tx_flush = spkmodem_tx_flush, + .rx_byte = spkmodem_rx_byte, + .tst_byte = spkmodem_tst_byte, +}; + diff --git a/src/include/console/console.h b/src/include/console/console.h index 0b63644..d320093 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -36,6 +36,9 @@ #if CONFIG_CONSOLE_CBMEM #include <console/cbmem_console.h> #endif +#if CONFIG_SPKMODEM +#include <console/spkmodem.h> +#endif #ifndef __PRE_RAM__ unsigned char console_rx_byte(void); diff --git a/src/include/console/spkmodem.h b/src/include/console/spkmodem.h new file mode 100644 index 0000000..450dbe8 --- /dev/null +++ b/src/include/console/spkmodem.h @@ -0,0 +1,7 @@ +#ifndef SPKMODEM_H +#define SPKMODEM_H 1 + +void spkmodem_init(void); +void spkmodem_tx_byte(unsigned char c); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9d3588e..e8b1485 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -47,6 +47,8 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c +romstage-$(CONFIG_SPKMODEM) += spkmodem.c + romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c romstage-y += compute_ip_checksum.c @@ -81,6 +83,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c +ramstage-$(CONFIG_SPKMODEM) += spkmodem.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c diff --git a/src/lib/spkmodem.c b/src/lib/spkmodem.c new file mode 100644 index 0000000..89773b1 --- /dev/null +++ b/src/lib/spkmodem.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <console/spkmodem.h> +#include <cpu/x86/tsc.h> + +#define SPEAKER_PIT_FREQUENCY 0x1234dd + + +enum { + PIT_COUNTER_0 = 0x40, + PIT_COUNTER_1 = 0x41, + PIT_COUNTER_2 = 0x42, + PIT_CTRL = 0x43, + PIT_SPEAKER_PORT = 0x61, +}; + + +enum { + PIT_SPK_TMR2 = 0x01, + PIT_SPK_DATA = 0x02, + PIT_SPK_TMR2_LATCH = 0x20 +}; + +enum { + PIT_CTRL_SELECT_MASK = 0xc0, + PIT_CTRL_SELECT_0 = 0x00, + PIT_CTRL_SELECT_1 = 0x40, + PIT_CTRL_SELECT_2 = 0x80, + + PIT_CTRL_READLOAD_MASK= 0x30, + PIT_CTRL_COUNTER_LATCH = 0x00, + PIT_CTRL_READLOAD_LSB = 0x10, + PIT_CTRL_READLOAD_MSB = 0x20, + PIT_CTRL_READLOAD_WORD = 0x30, + + PIT_CTRL_MODE_MASK = 0x0e, + PIT_CTRL_INTR_ON_TERM = 0x00, + PIT_CTRL_PROGR_ONE_SHOT = 0x02, + + PIT_CTRL_RATE_GEN = 0x04, + + PIT_CTRL_SQUAREWAVE_GEN = 0x06, + PIT_CTRL_SOFTSTROBE = 0x08, + + PIT_CTRL_HARDSTROBE = 0x0a, + + + PIT_CTRL_COUNT_MASK = 0x01, + PIT_CTRL_COUNT_BINARY = 0x00, + PIT_CTRL_COUNT_BCD = 0x01 +}; + + +static void +make_tone (uint16_t freq_count, unsigned int duration) +{ + outb (PIT_CTRL_SELECT_2 + | PIT_CTRL_READLOAD_WORD + | PIT_CTRL_SQUAREWAVE_GEN + | PIT_CTRL_COUNT_BINARY, PIT_CTRL); + + outb (freq_count & 0xff, PIT_COUNTER_2); + + outb ((freq_count >> 8) & 0xff, PIT_COUNTER_2); + + outb (inb (PIT_SPEAKER_PORT) + | PIT_SPK_TMR2 | PIT_SPK_DATA, + PIT_SPEAKER_PORT); + + for (; duration; duration--) { + unsigned short counter, previous_counter = 0xffff; + while (1) { + counter = inb (PIT_COUNTER_2); + counter |= ((uint16_t) inb (PIT_COUNTER_2)) << 8; + if (counter > previous_counter) + { + previous_counter = counter; + break; + } + previous_counter = counter; + } + } +} + +void spkmodem_tx_byte(unsigned char c) +{ + int i; + + make_tone (SPEAKER_PIT_FREQUENCY / 200, 4); + for (i = 7; i >= 0; i--) { + if ((c >> i) & 1) + make_tone (SPEAKER_PIT_FREQUENCY / 2000, 20); + else + make_tone (SPEAKER_PIT_FREQUENCY / 4000, 40); + make_tone (SPEAKER_PIT_FREQUENCY / 1000, 10); + } + make_tone (SPEAKER_PIT_FREQUENCY / 200, 0); +} + +void spkmodem_init(void) +{ + /* Some cards need time to come online. Output some message to get it started. */ + spkmodem_tx_byte('S'); + spkmodem_tx_byte('P'); + spkmodem_tx_byte('K'); + spkmodem_tx_byte('\r'); + spkmodem_tx_byte('\n'); +}

1 0

Patch set updated for coreboot: afce66c ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite`
by Paul Menzel 30 Mar '13

30 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2957 -gerrit commit afce66c5752ed824553361730dbd09225893b8e3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 15:39:54 2013 +0100 ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/mainboard.ramstage.o src/mainboard/asrock/e350m1/mainboard.c: In function 'mainboard_enable': src/mainboard/asrock/e350m1/mainboard.c:63:2: warning: implicit declaration of function 'pm_iowrite' [-Wimplicit-function-declaration] […] This warning was introduced by moving the initialization of the ASF registers using `pm_iowrite` to `mainboard.c` in commit db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Thu Mar 21 22:21:28 2013 +0100 Asrock E350M1: Use SPD read code from F14 wrapper Reviewed-on: http://review.coreboot.org/2875 and is fixed by including `southbridge/amd/cimx/cimx_util.h` declaring `pm_iowrite`. Note, that the other AMD SB800 based boards seem to use the header file `southbridge/amd/sb800/sb800.h`, so no warning is shown for those. But since the CIMx SB800 code is used, the routines from the CIMx directory are more appropriate to declare these functions. Change-Id: I179aad5157c5a91294339a3e7b6c4c1715c6f099 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/mainboard.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index be5c36c..cdac2be 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -25,6 +25,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> //#include <southbridge/amd/sb800/sb800.h> +#include <southbridge/amd/cimx/cimx_util.h> //#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void);

1 0

New patch to review for coreboot: 1de35e1 armv7: hacky backlight enable stuff (WIP)
by David Hendricks 30 Mar '13

30 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2988 -gerrit commit 1de35e1de3720c66c015ffc3ccfabd0791386f4a Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Mar 27 14:16:23 2013 -0700 armv7: hacky backlight enable stuff (WIP) ** do not submit ** Change-Id: I5f3bf32601bf9fce3f9d783d6b4691a233f9616d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/cpu.c | 64 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 61 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 32aa033..25e3acd 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <arch/io.h> #include <device/device.h> +#include <device/i2c.h> /* FIXME: for backlight FET enable */ #include <cbmem.h> #include <cpu/samsung/exynos5250/fimd.h> #include <cpu/samsung/exynos5-common/s5p-dp-core.h> @@ -53,7 +54,7 @@ static void exynos_displayport_init(device_t dev) vi.vl_row = conf->yres; vi.vl_bpix = conf->bpp; /* The size is a magic number from hardware. */ - lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, 64*KiB); + lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, 16*MiB + 64*KiB); printk(BIOS_SPEW, "lcd colormap base is %p\n", (void *)(lcdbase)); // mmio_resource(dev, 0, conf->lcdbase/KiB, 64); // vi.cmap = (void *)conf->lcdbase; @@ -61,14 +62,71 @@ static void exynos_displayport_init(device_t dev) vi.cmap = (void *)lcdbase; // lcdbase = conf->lcdbase + 64*KiB; - lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, 16*MiB); + /* FIXME: We had to do a single cbmem_add() above due to weirdness when + * the adjacent regions were being merged... */ +// lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, 16*MiB); + lcdbase += 64*KiB; printk(BIOS_SPEW, "lcd framebuffer base is %p\n", (void *)(lcdbase)); + printk(BIOS_SPEW, "conf->xres is: %u\n", conf->xres); /* FIXME: remove this */ mmio_resource(dev, 1, lcdbase/KiB, (conf->xres*conf->yres*4 + (KiB-1))/KiB); printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); + + /* enable backlight FETs (TODO: move all the stuff below to Snow) */ + i2c_set_bus_num(0); + uint8_t val; + +#define TPS69050_ADDR 0x48 +#define FET6_CTRL 0x14 + printk(BIOS_DEBUG, "attempting to enable FET6\n"); + //ret = board_dp_lcd_vdd(blob, &wait_ms); + i2c_read(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val)); + val |= 1; + i2c_write(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val)); + + exynos_pinmux_config(PERIPH_ID_DPHPD, 0); + + /* Setup the GPIOs */ #if 0 - ret = board_dp_lcd_vdd(blob, &wait_ms); ret = board_dp_bridge_setup(blob, &wait_ms); +#endif + enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */ + enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */ + enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */ + + /* De-assert PD (and possibly RST) to power up the bridge */ + gpio_set_value(dp_pd_l, 1); + gpio_set_value(dp_rst_l, 1); + + /* + * We need to wait for 90ms after bringing up the bridge since there + * is a phantom "high" on the HPD chip during its bootup. The phantom + * high comes within 7ms of de-asserting PD and persists for at least + * 15ms. The real high comes roughly 50ms after PD is de-asserted. The + * phantom high makes it hard for us to know when the NXP chip is up. + */ + *wait_ms = 90; + + + gpio_cfg_pin(dp_pd_l, EXYNOS_GPIO_OUTPUT); + gpio_set_pull(dp_pd_l, EXYNOS_GPIO_PULL_NONE); + +#if 0 + if (fdt_gpio_isvalid(&local.dp_rst)) { + fdtdec_set_gpio(&local.dp_rst, 1); + gpio_cfg_pin(local.dp_rst.gpio, EXYNOS_GPIO_OUTPUT); + gpio_set_pull(local.dp_rst.gpio, EXYNOS_GPIO_PULL_NONE); + udelay(10); + fdtdec_set_gpio(&local.dp_rst, 0); + } +#endif + gpio_set_value(dp_rst_l, 0); + gpio_cfg_pin(dp_rst_l, EXYNOS_GPIO_OUTPUT); + gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE); + udelay(10); + gpio_set_value(dp_rst, 1); + +#if 0 while (tries < 5) { ret = board_dp_bridge_init(blob, &wait_ms); ret = board_dp_hotplug(blob, &wait_ms);

1 0

Patch set updated for coreboot: 12a9920 samsung/exynos5: add resource functions for the display port (2nd try)
by David Hendricks 30 Mar '13

30 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2931 -gerrit commit 12a992038e603e2b3da468548c442505da22c851 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 18 09:49:54 2013 -0700 samsung/exynos5: add resource functions for the display port (2nd try) This does NOT turn on the graphics. The device tree has been changed enough so that, at the very least, the correct functions are called at the correct time, with the correct paramaters. We decided to yank the I2C entries as they did not obvious function and might not even have been correct. Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. We realized that the display code should be part of the cpu -- that's how the hardware works! (Note: this is a re-hash of Ron's previous attempt, but hopefully we do not break the cbmem tables in this version) Change-Id: I2caa350f8c0e681f71e9646898dcdb36e10115b2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/Makefile.inc | 1 - src/cpu/samsung/exynos5-common/displayport/Kconfig | 2 - .../exynos5-common/displayport/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/displayport/chip.h | 40 -------- .../exynos5-common/displayport/displayport.c | 107 --------------------- src/cpu/samsung/exynos5-common/exynos-fb.c | 4 +- src/cpu/samsung/exynos5250/Kconfig | 2 +- src/cpu/samsung/exynos5250/chip.h | 40 ++++++++ src/cpu/samsung/exynos5250/cpu.c | 88 ++++++++++++++++- src/mainboard/google/snow/devicetree.cb | 38 +++----- 10 files changed, 141 insertions(+), 183 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/Makefile.inc b/src/cpu/samsung/exynos5-common/Makefile.inc index 7abd75c..eb08fb6 100644 --- a/src/cpu/samsung/exynos5-common/Makefile.inc +++ b/src/cpu/samsung/exynos5-common/Makefile.inc @@ -22,4 +22,3 @@ ramstage-y += i2c.c ramstage-y += s5p-dp-reg.c ramstage-y += exynos-fb.c -subdirs-y += displayport diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig deleted file mode 100644 index 26d1422..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config EXYNOS_DISPLAYPORT - bool diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc deleted file mode 100644 index 7c52eaf..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c - diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h deleted file mode 100644 index 53b7836..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/chip.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H -#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H - -struct cpu_samsung_exynos5_common_displayport_config { - /* special magic numbers! */ - int clkval_f; - int upper_margin; - int lower_margin; - int vsync; - int left_margin; - int right_margin; - int hsync; - - int xres; - int yres; - int bpp; - - u32 lcdbase; -}; - -#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c deleted file mode 100644 index 1c08bc7..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/displayport.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <delay.h> -#include <arch/io.h> -#include <device/device.h> - -/* we distinguish a display port device from a raw graphics device because there are - * dramatic differences in startup depending on graphics usage. To make startup fast - * and easier to understand and debug we explicitly name this common case. The alternate - * approach, involving lots of machine and callbacks, is hard to debug and verify. - */ -static void exynos_displayport_init(void) -{ - struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; - /* put these on the stack. If, at some point, we want to move this code to a - * pre-ram stage, it will be much easier. - */ - vidinfo_t vi; - struct exynos5_fimd_panel panel; - void *lcdbase; - - memset(vi, 0, sizeof(vi)); - memset(panel, 0, sizeof(panel)); - - panel.is_dp = 1; /* Display I/F is eDP */ - /* while it is true that we did a memset to zero, - * we leave some 'set to zero' entries here to make - * it clear what's going on. Graphics is confusing. - */ - panel.is_mipi = 0; - panel.fixvclk = 0; - panel.ivclk = 0; - panel.clkval_f = conf->clkval_f; - panel.upper_margin = conf->upper_margin; - panel.lower_margin = conf->lower_margin; - panel.vsync = conf->vsync; - panel.left_margin = conf->left_margin; - panel.right_margin = conf->right_margin; - panel.hsync = conf->hsync; - - vi->vl_col = conf->xres; - vi->fl_row = conf->yres; - vi->vl_bpix = conf->bpp; - vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */ - - lcdbase = conf->lcdbase; - printk(BIOS_DEBUG, "Initializing exynos VGA\n"); - ret = lcd_ctrl_init(&vi, &panel, lcdbase); -#if 0 - ret = board_dp_lcd_vdd(blob, &wait_ms); - ret = board_dp_bridge_setup(blob, &wait_ms); - while (tries < 5) { - ret = board_dp_bridge_init(blob, &wait_ms); - ret = board_dp_hotplug(blob, &wait_ms); - if (ret) { - ret = board_dp_bridge_reset(blob, &wait_ms); - continue; - } - ret = dp_controller_init(blob, &wait_ms); - ret = board_dp_backlight_vdd(blob, &wait_ms); - ret = board_dp_backlight_pwm(blob, &wait_ms); - ret = board_dp_backlight_en(blob, &wait_ms); - } -#endif -} - -static void exynos_displayport_noop(device_t dummy) -{ -} - -static struct device_operations exynos_displayport_operations = { - .read_resources = exynos_displayport_noop, - .set_resources = exynos_displayport_noop, - .enable_resources = exynos_displayport_noop, - .init = exynos_displayport_init, - .scan_bus = exynos_displayport_noop, -}; - -static void exynos_displayport_enable(struct device *dev) -{ - if (dev->link_list != NULL) - dev->ops = &exynos_displayport_operations; -} - -struct chip_operations drivers_i2c_exynos_displayport_ops = { - CHIP_NAME("exynos displayport") - .enable_dev = exynos_displayport_enable; -}; diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 30d0767..990a313 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -100,7 +100,7 @@ static void fimd_bypass(void) { struct exynos5_sysreg *sysreg = samsung_get_base_sysreg(); - /*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/ + setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } @@ -586,7 +586,9 @@ int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, //vi->yres = panel_info->vl_row; fimd_bypass(); + printk(BIOS_SPEW, "fimd_bypass\n"); fb_init(panel_info, lcdbase, panel_data); + printk(BIOS_SPEW, "fb_init(%p, %p, %p\n",panel_info, lcdbase, panel_data); /* Enable flushing after LCD writes if requested */ // forget it. lcd_set_flush_dcache(1); diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index ca306b6..cc67abd 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -96,4 +96,4 @@ config SYS_TEXT_BASE config COREBOOT_TABLES_SIZE hex - default 0x100000 + default 0x4000000 diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h new file mode 100644 index 0000000..798cd26 --- /dev/null +++ b/src/cpu/samsung/exynos5250/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5250_H +#define CPU_SAMSUNG_EXYNOS5250_H + +struct cpu_samsung_exynos5250_config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5250_H */ diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 4bb06e8..32aa033 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,13 +1,92 @@ +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <delay.h> #include <console/console.h> +#include <arch/io.h> #include <device/device.h> -#include <arch/cache.h> -#include <cpu/samsung/exynos5250/cpu.h> +#include <cbmem.h> +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> +#include "chip.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(device_t dev) +{ + int ret; + struct cpu_samsung_exynos5250_config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + u32 lcdbase; + + printk(BIOS_SPEW, "%s: dev %p, conf %p\n", __func__, dev, conf); + memset(&vi, 0, sizeof(vi)); + memset(&panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi.vl_col = conf->xres; + vi.vl_row = conf->yres; + vi.vl_bpix = conf->bpp; + /* The size is a magic number from hardware. */ + lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, 64*KiB); + printk(BIOS_SPEW, "lcd colormap base is %p\n", (void *)(lcdbase)); +// mmio_resource(dev, 0, conf->lcdbase/KiB, 64); +// vi.cmap = (void *)conf->lcdbase; + mmio_resource(dev, 0, lcdbase/KiB, 64); + vi.cmap = (void *)lcdbase; +// lcdbase = conf->lcdbase + 64*KiB; + + lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, 16*MiB); + printk(BIOS_SPEW, "lcd framebuffer base is %p\n", (void *)(lcdbase)); + mmio_resource(dev, 1, lcdbase/KiB, (conf->xres*conf->yres*4 + (KiB-1))/KiB); + printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); +#if 0 + ret = board_dp_lcd_vdd(blob, &wait_ms); + ret = board_dp_bridge_setup(blob, &wait_ms); + while (tries < 5) { + ret = board_dp_bridge_init(blob, &wait_ms); + ret = board_dp_hotplug(blob, &wait_ms); + if (ret) { + ret = board_dp_bridge_reset(blob, &wait_ms); + continue; + } + ret = dp_controller_init(blob, &wait_ms); + ret = board_dp_backlight_vdd(blob, &wait_ms); + ret = board_dp_backlight_pwm(blob, &wait_ms); + ret = board_dp_backlight_en(blob, &wait_ms); + } +#endif +} + static void cpu_init(device_t dev) { + exynos_displayport_init(dev); ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); } @@ -23,17 +102,18 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_exynos5250_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + printk(BIOS_SPEW, "%s: CPU_CLUSTER\n", __func__); dev->ops = &cpu_ops; } } struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") - .enable_dev = enable_dev, + .enable_dev = enable_exynos5250_dev, }; void exynos5250_config_l2_cache(void) diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 5ad786e..4cdf47d 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -17,30 +17,18 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# FIXME: this is just a stub for now chip cpu/samsung/exynos5250 - -device cpu_cluster 0 on -end - -device domain 0 on - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # ? - device i2c 9 on end # ? - end - chip cpu/samsung/exynos5-common/displayport - register "xres" = "1366" - register "yres" = "768" - register "bpp" = "16" - # complex magic timing! - register "clkval_f" = "2" - register "upper_margin" = "14" - register "lower_margin" = "3" - register "vsync" = "5" - register "left_margin" = "80" - register "right_margin" = "48" - register "hsync" = "32" - register "lcdbase" = "0x10000000" - end -end + device cpu_cluster 0 on end + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" + # register "lcdbase" = "0x50000000" end

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coreboot-gerrit March 2013