coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: d3e1d75 wtm2: select write-combining memory for graphics
by Aaron Durbin 29 Mar '13

29 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2981 -gerrit commit d3e1d75eadaf1da924d8c57d5c93a29e21ce5cbf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 29 16:37:18 2013 -0500 wtm2: select write-combining memory for graphics Auto-select marking the graphics memory as write-combining. Change-Id: Icf61c5cbd129a97a106f0aaeca4e010d4799b4b8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/wtm2/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 16b5373..b486910 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB config MAINBOARD_DIR string

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New patch to review for coreboot: e91d920 boot: add disable_cache_rom() function
by Aaron Durbin 29 Mar '13

29 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2980 -gerrit commit e91d920c248d18f99af1ef602b9c98ffc53bf3ba Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 29 16:23:23 2013 -0500 boot: add disable_cache_rom() function On certain architectures such as x86 the bootstrap processor does most of the work. When CACHE_ROM is employed it's appropriate to ensure that the caching enablement of the ROM is disabled so that the caching settings are symmetric before booting the payload or OS. Tested this on an x86 machine that turned on ROM caching. Linux did not complain about asymmetric MTRR settings nor did the ROM show up as cached in the MTRR settings. Change-Id: Ia32ff9fdb1608667a0e9a5f23b9c8af27d589047 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/boot/acpi.c | 4 ++++ src/cpu/x86/mtrr/mtrr.c | 6 ++++++ src/include/cpu/cpu.h | 3 +++ src/lib/selfboot.c | 5 +++++ 4 files changed, 18 insertions(+) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index b04cbe5..7b207b4 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -646,6 +646,10 @@ void suspend_resume(void) #if CONFIG_COVERAGE coverage_exit(); #endif + /* Tear down the caching of the ROM. */ + if (disable_cache_rom) + disable_cache_rom(); + post_code(POST_OS_RESUME); acpi_jump_to_wakeup(wake_vec); } diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 253a7c3..6089127 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -29,6 +29,7 @@ #include <string.h> #include <console/console.h> #include <device/device.h> +#include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> @@ -406,6 +407,11 @@ void x86_mtrr_disable_rom_caching(void) wrmsr(MTRRphysBase_MSR(index), msr_val); enable_cache(); } + +void disable_cache_rom(void) +{ + x86_mtrr_disable_rom_caching(); +} #endif struct var_mtrr_state { diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index bed77de..a2272f3 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -9,6 +9,9 @@ struct bus; void initialize_cpus(struct bus *cpu_bus); void asmlinkage secondary_cpu_init(unsigned int cpu_index); +/* If a ROM cache was set up disable it before jumping to the payload or OS. */ +void __attribute__((weak)) disable_cache_rom(void); + #if CONFIG_HAVE_SMI_HANDLER void smm_init(void); void smm_lock(void); diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index f933142..be03b85 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -20,6 +20,7 @@ #include <arch/byteorder.h> #include <console/console.h> +#include <cpu/cpu.h> #include <fallback.h> #include <boot/elf.h> #include <boot/elf_boot.h> @@ -540,6 +541,10 @@ int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) coverage_exit(); #endif + /* Tear down the caching of the ROM. */ + if (disable_cache_rom) + disable_cache_rom(); + /* Before we go off to run the payload, see if * we stayed within our bounds. */

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Patch set updated for coreboot: df4bdf8 lynxpoint: fix enable_pm1() function
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2978 -gerrit commit df4bdf845632cc016baa0b892b6c7ff8a4b0d2ec Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 27 21:13:02 2013 -0500 lynxpoint: fix enable_pm1() function The new enable_pm1() function was doing 2 things wrong: 1. It was doing a RMW of the pm1 register. This means we were keeping around the enables from the OS during S3 resume. This is bad in the face of the RTC alarm waking us up because it would cause an infinite stream of SMIs. 2. The register size of PM1_EN is 16-bits. However, the previous implementation was accessing it as a 32-bit register. The PM1 enables should only be set to what we expect to handle in the firmware before the OS changes to ACPI mode. Change-Id: Ib1d3caf6c84a1670d9456ed159420c6cb64f555e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/pch.h | 2 +- src/southbridge/intel/lynxpoint/pmutil.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a48e0a4..7246739 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -139,7 +139,7 @@ void enable_pm1_control(u32 mask); void disable_pm1_control(u32 mask); /* PM1 */ u16 clear_pm1_status(void); -void enable_pm1(u32 mask); +void enable_pm1(u16 events); u32 clear_smi_status(void); /* SMI */ void enable_smi(u32 mask); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 3a0b70b..386705f 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -29,6 +29,7 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> +#include <pc80/mc146818rtc.h> #include "pch.h" #if CONFIG_INTEL_LYNXPOINT_LP @@ -104,6 +105,7 @@ static u16 reset_pm1_status(void) { u16 pm1_sts = inw(get_pmbase() + PM1_STS); outw(pm1_sts, get_pmbase() + PM1_STS); + return pm1_sts; } @@ -137,12 +139,10 @@ u16 clear_pm1_status(void) return print_pm1_status(reset_pm1_status()); } -/* Enable PM1 event */ -void enable_pm1(u32 mask) +/* Set the PM1 register to events */ +void enable_pm1(u16 events) { - u32 pm1_en = inl(get_pmbase() + PM1_EN); - pm1_en |= mask; - outl(pm1_en, get_pmbase() + PM1_EN); + outw(events, get_pmbase() + PM1_EN); }

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Patch set updated for coreboot: 55536d7 pci: don't load vga option rom before S3 check
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2979 -gerrit commit 55536d7ec62ad495adc8e4851bfc264344c68436 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 28 15:59:19 2013 -0500 pci: don't load vga option rom before S3 check The pci device code was probing and loading the option rom before it did the S3 resume check for VGA option roms. Instead move this check before probing and loading so that we don't unnecessarily do work. Change-Id: If2e62d0c0e4b34b4f1bcd56ebcb9d3f54c6d0d24 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/device/pci_device.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index ff334fe..4c5a814 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -685,14 +685,6 @@ void pci_dev_init(struct device *dev) } #endif - rom = pci_rom_probe(dev); - if (rom == NULL) - return; - - ram = pci_rom_load(dev, rom); - if (ram == NULL) - return; - #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN /* If S3_VGA_ROM_RUN is disabled, skip running VGA option * ROMs when coming out of an S3 resume. @@ -701,6 +693,15 @@ void pci_dev_init(struct device *dev) ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) return; #endif + + rom = pci_rom_probe(dev); + if (rom == NULL) + return; + + ram = pci_rom_load(dev, rom); + if (ram == NULL) + return; + run_bios(dev, (unsigned long)ram); #if CONFIG_CHROMEOS oprom_is_loaded = 1;

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Patch merged into coreboot/master: 26e8f2f snow: explicitly configure L2 cache
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 26e8f2fe0125cc6e7727d024bf4bfbd6231c8b27 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 19:05:29 2013 -0700 snow: explicitly configure L2 cache This adds a call to explicitly configure L2 cache (though defaults should be set correctly). Change-Id: I120e29c986918c2904a0332e46fcf9f1c5380d85 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2950 Reviewed-by: Gabe Black <gabe.black(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Mar 29 22:08:39 2013, giving +1 See http://review.coreboot.org/2950 for details. -gerrit

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Patch merged into coreboot/master: c01d138 exynos5250: Add function for configuring L2 cache
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit c01d1380138e807fa941976d9f102fb1b200ad01 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 19:04:58 2013 -0700 exynos5250: Add function for configuring L2 cache This adds a new function to configure L2 cache for the exynos5250 and deprecates the old function. Change-Id: I9562f3301aa1e2911dae3856ab57bb6beec2e224 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2949 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Gabe Black <gabe.black(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Mar 29 22:23:07 2013, giving +1 See http://review.coreboot.org/2949 for details. -gerrit

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New patch to review for coreboot: 5b47d81 pci: don't load vga option rom before S3 check
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2979 -gerrit commit 5b47d81ad6206c56d03303b2bcf89ebd1d811dad Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 28 15:59:19 2013 -0500 pci: don't load vga option rom before S3 check The pci device code was probing and loading the option rom before it did the S3 resume check for VGA option roms. Instead move this check before probing and loading so that we don't unnecessarily do work. Change-Id: If2e62d0c0e4b34b4f1bcd56ebcb9d3f54c6d0d24 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/device/pci_device.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index ff334fe..4c5a814 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -685,14 +685,6 @@ void pci_dev_init(struct device *dev) } #endif - rom = pci_rom_probe(dev); - if (rom == NULL) - return; - - ram = pci_rom_load(dev, rom); - if (ram == NULL) - return; - #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN /* If S3_VGA_ROM_RUN is disabled, skip running VGA option * ROMs when coming out of an S3 resume. @@ -701,6 +693,15 @@ void pci_dev_init(struct device *dev) ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) return; #endif + + rom = pci_rom_probe(dev); + if (rom == NULL) + return; + + ram = pci_rom_load(dev, rom); + if (ram == NULL) + return; + run_bios(dev, (unsigned long)ram); #if CONFIG_CHROMEOS oprom_is_loaded = 1;

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New patch to review for coreboot: 2fcd2d1 lynxpoint: fix enable_pm1() function
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2978 -gerrit commit 2fcd2d1ba16f3daf28be2b6c685e2b91842debd6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 27 21:13:02 2013 -0500 lynxpoint: fix enable_pm1() function The new enable_pm1() function was doing 2 things wrong: 1. It was doing a RMW of the pm1 register. This means we were keeping around the enables from the OS during S3 resume. This is bad in the face of the RTC alarm waking us up because it would cause an infinite stream of SMIs. 2. The register size of PM1_EN is 16-bits. However, the previous implementation was accessing it as a 32-bit register. The PM1 enables should only be set to what we expect to handle in the firmware before the OS changes to ACPI mode. Change-Id: Ib1d3caf6c84a1670d9456ed159420c6cb64f555e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/pch.h | 2 +- src/southbridge/intel/lynxpoint/pmutil.c | 22 +++++++++++++++++----- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a48e0a4..7246739 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -139,7 +139,7 @@ void enable_pm1_control(u32 mask); void disable_pm1_control(u32 mask); /* PM1 */ u16 clear_pm1_status(void); -void enable_pm1(u32 mask); +void enable_pm1(u16 events); u32 clear_smi_status(void); /* SMI */ void enable_smi(u32 mask); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 3a0b70b..ea1dc65 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -29,6 +29,7 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> +#include <pc80/mc146818rtc.h> #include "pch.h" #if CONFIG_INTEL_LYNXPOINT_LP @@ -104,6 +105,19 @@ static u16 reset_pm1_status(void) { u16 pm1_sts = inw(get_pmbase() + PM1_STS); outw(pm1_sts, get_pmbase() + PM1_STS); + +#if 0 + if (pm1_sts & RTC_STS) { + u8 cmos_status; + + cmos_status = cmos_read(RTC_REG_B); + printk(BIOS_DEBUG, "RTC REG B: %02X\n", cmos_status); + /* read RTC status register to disable the interrupt */ + cmos_status = cmos_read(RTC_REG_C); + printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status); + } +#endif + return pm1_sts; } @@ -137,12 +151,10 @@ u16 clear_pm1_status(void) return print_pm1_status(reset_pm1_status()); } -/* Enable PM1 event */ -void enable_pm1(u32 mask) +/* Set the PM1 register to events */ +void enable_pm1(u16 events) { - u32 pm1_en = inl(get_pmbase() + PM1_EN); - pm1_en |= mask; - outl(pm1_en, get_pmbase() + PM1_EN); + outw(events, get_pmbase() + PM1_EN); }

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New patch to review for coreboot: a75e92d lynxpoint: split clearing and enabling of smm
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2977 -gerrit commit a75e92dd9647f177b134e1818006cbec28395fd8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 27 20:57:28 2013 -0500 lynxpoint: split clearing and enabling of smm Previously southbridge_smm_init() was provided that did both the clearing of the SMM state and enabling SMIs. This is troublesome in how haswell machines bring up the APs. The BSP enters SMM once to determine if parallel SMM relocation is possible. If it is possible the BSP releases the APs to do SMM relocation. Normally, after the APs complete the SMM relocation, the BSP would then re-enter the relocation handler to relocate its own SMM space. However, because SMIs were previously enabled it is possible for an SMI event to occur before the APs are complete or have entered the relocation handler. This is bad because the BSP will turn off parallel SMM save state. Additionally, this is a problem because the relocation handler is not written to handle regular SMIs which can cause an SMI storm which effectively looks like a hung machine. Correct these issues by turning on SMIs after all the SMM relocation has occurred. Change-Id: Id4f07553b110b9664d51d2e670a14e6617591500 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/smmrelocate.c | 7 ++++++- src/southbridge/intel/lynxpoint/pch.h | 6 +++++- src/southbridge/intel/lynxpoint/smi.c | 6 +++++- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 65ac363..a8ab841 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -396,7 +396,8 @@ int smm_initialize(void) if (cpu_smm_setup()) return -1; - southbridge_smm_init(); + /* Clear the SMM state in the southbridge. */ + southbridge_smm_clear_state(); /* Run the relocation handler. */ smm_initiate_relocation(); @@ -412,6 +413,10 @@ int smm_initialize(void) release_aps_for_smm_relocation(0); } + /* Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. */ + southbridge_smm_enable_smi(); + /* Lock down the SMRAM space. */ smm_lock(); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 76672bc..a48e0a4 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -170,9 +170,13 @@ void pch_log_state(void); void acpi_create_intel_hpet(acpi_hpet_t * hpet); /* These helpers are for performing SMM relocation. */ -void southbridge_smm_init(void); void southbridge_trigger_smi(void); void southbridge_clear_smi_status(void); +/* The initialization of the southbridge is split into 2 compoments. One is + * for clearing the state in the SMM registers. The other is for enabling + * SMIs. They are split so that other work between the 2 actions. */ +void southbridge_smm_clear_state(void); +void southbridge_smm_enable_smi(void); #else void enable_smbus(void); void enable_usb_bar(void); diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 176d400..75c3e66 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -30,7 +30,7 @@ #include <string.h> #include "pch.h" -void southbridge_smm_init(void) +void southbridge_smm_clear_state(void) { u32 smi_en; @@ -54,7 +54,11 @@ void southbridge_smm_init(void) clear_pm1_status(); clear_tco_status(); clear_gpe_status(); +} +void southbridge_smm_enable_smi(void) +{ + printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events */ enable_pm1(PWRBTN_EN | GBL_EN); disable_gpe(PME_B0_EN);

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New patch to review for coreboot: 560c003 chromeos: honor MOCK_TPM=1
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2976 -gerrit commit 560c003d3b0acd4196c4d3cfb68eb5a914f01144 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 27 00:16:11 2013 -0500 chromeos: honor MOCK_TPM=1 The TPM code wasn't previously honoring MOCK_TPM=1. Because of this, boards with TPMs that didn't handle S3 resume properly would cause a hard reset. Allow one to build with MOCK_TPM=1 on the command line so that S3 can still work. Change-Id: I9adf06647de285c0b0a3203d8897be90d7783a1e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/Makefile.inc | 6 ++++++ src/vendorcode/google/chromeos/vboot.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 230523c..4fa22ea 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -31,6 +31,12 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c romstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c endif +ifeq ($(MOCK_TPM),1) +CFLAGS += -DMOCK_TPM=1 +else +CFLAGS += -DMOCK_TPM=0 +endif + ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) romstage-y += vboot_loader.c rmodules-y += vboot_wrapper.c diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c index 0f30547..03d759c 100644 --- a/src/vendorcode/google/chromeos/vboot.c +++ b/src/vendorcode/google/chromeos/vboot.c @@ -231,8 +231,10 @@ static void init_vboot(int bootmode) return; } +#if !MOCK_TPM printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result); hard_reset(); +#endif } #endif

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coreboot-gerrit March 2013