coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

1 participants
443 discussions

Patch set updated for coreboot: 3a1ca4c inteltool: Support PM registers on Cougar/Panther Point
by Nico Huber 30 Mar '13

30 Mar '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2985 -gerrit commit 3a1ca4c075015acd1a6fe2c8950b22396374d02f Author: Nico Huber <nico.h(a)gmx.de> Date: Fri Mar 29 19:00:37 2013 +0100 inteltool: Support PM registers on Cougar/Panther Point This adds the power management register definitions for Intel's Cougar Point and Panther Point platform controller hubs (PCH). The definitions are actually a subset of the older ICH10R registers: I've added just those that are mentioned in the public specifications in [1] and [2]. I've tested dumping with an H77 PCH. NM70 is missing in [1]. Therefore, I didn't add it here. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/inteltool/powermgt.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 71dfc49..f0f7664 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -21,6 +21,57 @@ #include <stdio.h> #include "inteltool.h" +static const io_register_t pch_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK + { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 + { 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK + { 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "RESERVED" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK + { 0x28, 8, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8 + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x38, 2, "ALT_GP_SMI_EN" }, + { 0x3a, 2, "ALT_GP_SMI_STS" }, + { 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control + { 0x3d, 1, "RESERVED" }, + { 0x3e, 2, "RESERVED" }, + { 0x40, 2, "RESERVED" }, + { 0x42, 1, "GPE_CNTL" }, + { 0x43, 1, "RESERVED" }, + { 0x44, 2, "DEVACT_STS" }, // Device Activity Status + { 0x46, 2, "RESERVED" }, + { 0x48, 4, "RESERVED" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 1, "PM2_CNT" }, + { 0x51, 1, "RESERVED" }, + { 0x52, 2, "RESERVED" }, + { 0x54, 4, "RESERVED" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + /* The TCO registers start here. */ + { 0x60, 2, "TCO_RLD" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 2, "TCO_MESSAGE" }, + { 0x6e, 1, "TCO_WDCNT" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 1, "SW_IRQ_GEN" }, + { 0x71, 1, "RESERVED" }, + { 0x72, 2, "TCO_TMR" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + static const io_register_t ich10_pm_registers[] = { { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 @@ -605,6 +656,39 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) printf("\n============= PMBASE ============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_Z68: + case PCI_DEVICE_ID_INTEL_P67: + case PCI_DEVICE_ID_INTEL_UM67: + case PCI_DEVICE_ID_INTEL_HM65: + case PCI_DEVICE_ID_INTEL_H67: + case PCI_DEVICE_ID_INTEL_HM67: + case PCI_DEVICE_ID_INTEL_Q65: + case PCI_DEVICE_ID_INTEL_QS67: + case PCI_DEVICE_ID_INTEL_Q67: + case PCI_DEVICE_ID_INTEL_QM67: + case PCI_DEVICE_ID_INTEL_B65: + case PCI_DEVICE_ID_INTEL_C202: + case PCI_DEVICE_ID_INTEL_C204: + case PCI_DEVICE_ID_INTEL_C206: + case PCI_DEVICE_ID_INTEL_H61: + case PCI_DEVICE_ID_INTEL_Z77: + case PCI_DEVICE_ID_INTEL_Z75: + case PCI_DEVICE_ID_INTEL_Q77: + case PCI_DEVICE_ID_INTEL_Q75: + case PCI_DEVICE_ID_INTEL_B75: + case PCI_DEVICE_ID_INTEL_H77: + case PCI_DEVICE_ID_INTEL_C216: + case PCI_DEVICE_ID_INTEL_QM77: + case PCI_DEVICE_ID_INTEL_QS77: + case PCI_DEVICE_ID_INTEL_HM77: + case PCI_DEVICE_ID_INTEL_UM77: + case PCI_DEVICE_ID_INTEL_HM76: + case PCI_DEVICE_ID_INTEL_HM75: + case PCI_DEVICE_ID_INTEL_HM70: + pmbase = pci_read_word(sb, 0x40) & 0xff80; + pm_registers = pch_pm_registers; + size = ARRAY_SIZE(pch_pm_registers); + break; case PCI_DEVICE_ID_INTEL_ICH10R: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = ich10_pm_registers;

1 0

Patch merged into coreboot/master: 14290b3 inteltool: Add Cougar/Panther Point IDs to rootcmplx.c
by gerrit＠coreboot.org 30 Mar '13

30 Mar '13

the following patch was just integrated into master: commit 14290b3cbb4428cc6416d087433e9be09605ab17 Author: Nico Huber <nico.h(a)gmx.de> Date: Fri Mar 29 19:08:39 2013 +0100 inteltool: Add Cougar/Panther Point IDs to rootcmplx.c This adds the PCI IDs of Intel's Cougar Point and Panther Point platform controller hubs (PCH) to the dumping of the root complex configuration under the root complex base address (RCBA). Those PCHs are handled exactly as the older ICHs which can be seen in [1] and [2]. I've tested dumping with an H77 PCH. NM70 is missing in [1]. Therefore, I didn't add it here. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 Change-Id: I2296caae57e614171300362d41715deecec77762 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/2986 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Sat Mar 30 04:14:48 2013, giving +1 See http://review.coreboot.org/2986 for details. -gerrit

1 0

Patch set updated for coreboot: 97856d8 util/cbmem: Don't output trailing garbage for cbmemc
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2991 -gerrit commit 97856d861d33fe922ce654e36930ca878b9d26b7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:15:12 2013 +0100 util/cbmem: Don't output trailing garbage for cbmemc Current code output the whole cbmemc buffer even if only part of it is really used. Fix it to output only really used part and notify if the buffer was too small for the required data. Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/cbmem/cbmem.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index bc6bd6b..09a073e 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -308,12 +308,21 @@ static void dump_timestamps(void) unmap_memory(); } +static const char *future_ngettext (const char *sing, const char *plural, + unsigned long int n) +{ + if (n == 1) + return sing; + return plural; +} + /* dump the cbmem console */ static void dump_console(void) { void *console_p; char *console_c; uint32_t size; + uint32_t cursor; if (console.tag != LB_TAG_CBMEM_CONSOLE) { fprintf(stderr, "No console found in coreboot table.\n"); @@ -328,6 +337,12 @@ static void dump_console(void) * Hence we have to add 8 to get to the actual console string. */ size = *(uint32_t *)console_p; + cursor = *(uint32_t *) (console_p + 4); + /* Cursor continues to go on even after no more data fits in + the buffer but the data is dropped in this case. + */ + if (size > cursor) + size = cursor; console_c = malloc(size + 1); if (!console_c) { fprintf(stderr, "Not enough memory for console.\n"); @@ -337,7 +352,11 @@ static void dump_console(void) memcpy(console_c, console_p + 8, size); console_c[size] = 0; - printf("%s", console_c); + printf("%s\n", console_c); + if (size < cursor) + printf (future_ngettext ("1 byte lost\n" : + "%d bytes lost\n", cursor - size), + cursor - size); free(console_c);

1 0

Patch set updated for coreboot: 03da0a9 Intel: Return on missing microcode file to fix null pointer dereference
by Paul Menzel 30 Mar '13

30 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2990 -gerrit commit 03da0a93e2c653900e19c421c7167202c1afefa6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Mar 12 15:53:44 2013 +0100 Intel: Return on missing microcode file to fix null pointer dereference Selecting `CPU_MICROCODE_IN_CBFS` in Kconfig but not having the microcode blob `cpu_microcode_blob.bin` in CBFS results in a null pointer dereference later on resulting in a crash. for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { Fix this by returning if `microcode_updates` is `NULL`, that means no file is found. This patch is successfully tested on the Lenovo X201. Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/intel/microcode/microcode.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index d908c25..a1f66d8 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -131,7 +131,10 @@ const void *intel_microcode_find(void) #endif if (!microcode_updates) - return microcode_updates; + /* No need for an explicit error message since the user + * already gets "file not found" from CBFS. + */ + return microcode_updates; /* NULL */ /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; @@ -202,6 +205,9 @@ void intel_update_microcode(const void *microcode_updates) const char *c; msr_t msr; + if (!microcode_updates) + return; + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0;

1 0

Patch set updated for coreboot: abb0053 ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite`
by Paul Menzel 30 Mar '13

30 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2957 -gerrit commit abb00534d1c801e00acbf8473b5ee5cc14e7b5e1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 15:39:54 2013 +0100 ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/mainboard.ramstage.o src/mainboard/asrock/e350m1/mainboard.c: In function 'mainboard_enable': src/mainboard/asrock/e350m1/mainboard.c:63:2: warning: implicit declaration of function 'pm_iowrite' [-Wimplicit-function-declaration] […] This warning was introduced by moving the initialization of the ASF registers using `pm_iowrite` to `mainboard.c` in commit db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Thu Mar 21 22:21:28 2013 +0100 Asrock E350M1: Use SPD read code from F14 wrapper Reviewed-on: http://review.coreboot.org/2875 and is fixed by including `southbridge/amd/cimx/cimx_util.h` declaring `pm_iowrite`. Note, that the other AMD SB800 based boards seem to use the header file `southbridge/amd/sb800/sb800.h`, so no warning is shown for those. But since the CIMx SB800 code is used, the routines from the CIMx directory are more appropriate to declare these functions. So delete the commented out include line for this header too. Change-Id: I179aad5157c5a91294339a3e7b6c4c1715c6f099 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index be5c36c..a98a179 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -24,7 +24,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -//#include <southbridge/amd/sb800/sb800.h> +#include <southbridge/amd/cimx/cimx_util.h> //#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void);

1 0

Patch merged into coreboot/master: f0813bb AMD Hudson boards: Use `hudson.h` for `pm_ioread` and delete `pmio.h`
by gerrit＠coreboot.org 30 Mar '13

30 Mar '13

the following patch was just integrated into master: commit f0813bb7edabd4e6df810782c843b73d3d8f55fd Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 15:59:13 2013 +0100 AMD Hudson boards: Use `hudson.h` for `pm_ioread` and delete `pmio.h` Unfortunately, an unneeded mainboard specific `pmio.h` was created when merging the AMD Parmer and Thatcher ports. Rudolf used the header from a more generic location southbridge/amd/agesa/hudson/hudson.h doing the the ASUS F2A85-M port, but did not delete the `pmio.h` now unused `pmio.h` header file. So adapt AMD Parmer and Thatcher to use the Hudson one as done for the ASUS F2A85-M and delete the now unused mainboard specific header file `pmio.h` to avoid duplication. Change-Id: I961cd145ebc3b83e31c638ac453ac95ee19c18db Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2958 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Build-Tested: build bot (Jenkins) at Fri Mar 29 19:39:45 2013, giving +1 Reviewed-By: Martin Roth <martin.roth(a)se-eng.com> at Sat Mar 30 02:15:44 2013, giving +2 See http://review.coreboot.org/2958 for details. -gerrit

1 0

Patch merged into coreboot/master: 20ed4b7 ASRock E350M1: irq_tables.c: Include `cpu/amd/amdfam14.h` for `get_bus_conf`
by gerrit＠coreboot.org 30 Mar '13

30 Mar '13

the following patch was just integrated into master: commit 20ed4b7bf3fd8d270f28d7ea35ba03b3861f58a0 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 14:36:33 2013 +0100 ASRock E350M1: irq_tables.c: Include `cpu/amd/amdfam14.h` for `get_bus_conf` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/irq_tables.ramstage.o src/mainboard/asrock/e350m1/irq_tables.c: In function 'write_pirq_routing_table': src/mainboard/asrock/e350m1/irq_tables.c:64:2: warning: implicit declaration of function 'get_bus_conf' [-Wimplicit-function-declaration] […] Including the header file `cpu/amd/amdfam14.h` declaring the function addresses this warning. The same change was done in the following commit for the AMD Persimmon board. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 Change-Id: I40b5735feb7116961ca0c4d6940ec55cdf42d3c6 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2956 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Build-Tested: build bot (Jenkins) at Fri Mar 29 21:51:21 2013, giving +1 Reviewed-By: Martin Roth <martin.roth(a)se-eng.com> at Sat Mar 30 02:16:55 2013, giving +2 See http://review.coreboot.org/2956 for details. -gerrit

1 0

Patch merged into coreboot/master: 2120460 ASRock E350M1: get_bus_conf.c: Include `agesawrapper.h` for `agesawrapper_amdinitlate`
by gerrit＠coreboot.org 30 Mar '13

30 Mar '13

the following patch was just integrated into master: commit 21204600378d71655f90c781d400c0249d1cd284 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 13:23:31 2013 +0100 ASRock E350M1: get_bus_conf.c: Include `agesawrapper.h` for `agesawrapper_amdinitlate` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/get_bus_conf.ramstage.o src/mainboard/asrock/e350m1/get_bus_conf.c: In function 'get_bus_conf': src/mainboard/asrock/e350m1/get_bus_conf.c:82:3: warning: implicit declaration of function 'agesawrapper_amdinitlate' [-Wimplicit-function-declaration] […] Including the header file `agesawrapper.h` declaring the function `agesawrapper_amdinitlate` fixes this warning. All AMD Family 14 based boards already include that header file. For example for the board AMD Persimmon the following patch fixed this warning. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 Change-Id: I695420b7071e07cb7d4667b2479b9a26ea13723d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2955 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Build-Tested: build bot (Jenkins) at Fri Mar 29 14:02:01 2013, giving +1 Reviewed-By: Martin Roth <martin.roth(a)se-eng.com> at Fri Mar 29 21:40:37 2013, giving +2 See http://review.coreboot.org/2955 for details. -gerrit

1 0

Patch merged into coreboot/master: e4807f3 ASRock E350M1: PlatformGnbPcie.c: Do not return anything for void return type
by gerrit＠coreboot.org 30 Mar '13

30 Mar '13

the following patch was just integrated into master: commit e4807f30c50df8302f3ed34bad2febf073f85ab3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 12:51:31 2013 +0100 ASRock E350M1: PlatformGnbPcie.c: Do not return anything for void return type When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/PlatformGnbPcie.romstage.o CC mainboard/asrock/e350m1/agesawrapper.romstage.o CC mainboard/asrock/e350m1/buildOpts.romstage.o src/mainboard/asrock/e350m1/PlatformGnbPcie.c: In function 'OemCustomizeInitEarly': src/mainboard/asrock/e350m1/PlatformGnbPcie.c:131:5: warning: 'return' with a value, in function returning void [enabled by default] […] The function signature is (the return type might not be part of this though [1]), VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) so do not return anything. All other AMD Family 14 boards already have the correct code. For example following commit fixed this for AMD Persimmon. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 [1] http://cboard.cprogramming.com/cplusplus-programming/117286-what-exactly-fu… Change-Id: Ie60246bd9bb8452efd096e6838d8610f6364a6aa Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2954 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Build-Tested: build bot (Jenkins) at Fri Mar 29 14:16:24 2013, giving +1 Reviewed-By: Martin Roth <martin.roth(a)se-eng.com> at Sat Mar 30 02:10:24 2013, giving +2 See http://review.coreboot.org/2954 for details. -gerrit

1 0

Patch set updated for coreboot: 38b9a01 Don't output trailing garbage for cbmemc
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2991 -gerrit commit 38b9a01cd2e4406faadd890700235ee251843d3b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:15:12 2013 +0100 Don't output trailing garbage for cbmemc Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/cbmem/cbmem.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index bc6bd6b..09a073e 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -308,12 +308,21 @@ static void dump_timestamps(void) unmap_memory(); } +static const char *future_ngettext (const char *sing, const char *plural, + unsigned long int n) +{ + if (n == 1) + return sing; + return plural; +} + /* dump the cbmem console */ static void dump_console(void) { void *console_p; char *console_c; uint32_t size; + uint32_t cursor; if (console.tag != LB_TAG_CBMEM_CONSOLE) { fprintf(stderr, "No console found in coreboot table.\n"); @@ -328,6 +337,12 @@ static void dump_console(void) * Hence we have to add 8 to get to the actual console string. */ size = *(uint32_t *)console_p; + cursor = *(uint32_t *) (console_p + 4); + /* Cursor continues to go on even after no more data fits in + the buffer but the data is dropped in this case. + */ + if (size > cursor) + size = cursor; console_c = malloc(size + 1); if (!console_c) { fprintf(stderr, "Not enough memory for console.\n"); @@ -337,7 +352,11 @@ static void dump_console(void) memcpy(console_c, console_p + 8, size); console_c[size] = 0; - printf("%s", console_c); + printf("%s\n", console_c); + if (size < cursor) + printf (future_ngettext ("1 byte lost\n" : + "%d bytes lost\n", cursor - size), + cursor - size); free(console_c);

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2013