Patch set updated for coreboot: 3a1ca4c inteltool: Support PM registers on Cougar/Panther Point

[Nico Huber]

Nico Huber ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2985

-gerrit

commit 3a1ca4c075015acd1a6fe2c8950b22396374d02f
Author: Nico Huber 
Date:   Fri Mar 29 19:00:37 2013 +0100

inteltool: Support PM registers on Cougar/Panther Point

This adds the power management register definitions for Intel's Cougar
    Point and Panther Point platform controller hubs (PCH). The definitions
    are actually a subset of the older ICH10R registers: I've added just
    those that are mentioned in the public specifications in [1] and [2].
    I've tested dumping with an H77 PCH.

NM70 is missing in [1]. Therefore, I didn't add it here.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
        Document-Number: 324645-006

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
        Datasheet
        Document-Number: 326776-003

Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95
    Signed-off-by: Nico Huber 
---
 util/inteltool/powermgt.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index 71dfc49..f0f7664 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -21,6 +21,57 @@
 #include <stdio.h>
 #include "inteltool.h"

+static const io_register_t pch_pm_registers[] = {
+	{ 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
+	{ 0x02, 2, "PM1_EN" },  // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
+	{ 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK
+	{ 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK
+	{ 0x0c, 4, "RESERVED" },
+	{ 0x10, 4, "RESERVED" },
+	{ 0x14, 4, "RESERVED" },
+	{ 0x18, 4, "RESERVED" },
+	{ 0x1c, 4, "RESERVED" },
+	{ 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK
+	{ 0x28, 8, "GPE0_EN" },  // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8
+	{ 0x30, 4, "SMI_EN" },
+	{ 0x34, 4, "SMI_STS" },
+	{ 0x38, 2, "ALT_GP_SMI_EN" },
+	{ 0x3a, 2, "ALT_GP_SMI_STS" },
+	{ 0x3c, 1, "UPRWC" },   // USB Per-Port registers write control
+	{ 0x3d, 1, "RESERVED" },
+	{ 0x3e, 2, "RESERVED" },
+	{ 0x40, 2, "RESERVED" },
+	{ 0x42, 1, "GPE_CNTL" },
+	{ 0x43, 1, "RESERVED" },
+	{ 0x44, 2, "DEVACT_STS" }, // Device Activity Status
+	{ 0x46, 2, "RESERVED" },
+	{ 0x48, 4, "RESERVED" },
+	{ 0x4c, 4, "RESERVED" },
+	{ 0x50, 1, "PM2_CNT" },
+	{ 0x51, 1, "RESERVED" },
+	{ 0x52, 2, "RESERVED" },
+	{ 0x54, 4, "RESERVED" },
+	{ 0x58, 4, "RESERVED" },
+	{ 0x5c, 4, "RESERVED" },
+	/* The TCO registers start here. */
+	{ 0x60, 2, "TCO_RLD" },
+	{ 0x62, 1, "TCO_DAT_IN" },
+	{ 0x63, 1, "TCO_DAT_OUT" },
+	{ 0x64, 2, "TCO1_STS" },
+	{ 0x66, 2, "TCO2_STS" },
+	{ 0x68, 2, "TCO1_CNT" },
+	{ 0x6a, 2, "TCO2_CNT" },
+	{ 0x6c, 2, "TCO_MESSAGE" },
+	{ 0x6e, 1, "TCO_WDCNT" },
+	{ 0x6f, 1, "RESERVED" },
+	{ 0x70, 1, "SW_IRQ_GEN" },
+	{ 0x71, 1, "RESERVED" },
+	{ 0x72, 2, "TCO_TMR" },
+	{ 0x74, 4, "RESERVED" },
+	{ 0x78, 4, "RESERVED" },
+	{ 0x7c, 4, "RESERVED" },
+};
+
 static const io_register_t ich10_pm_registers[] = {
    { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
    { 0x02, 2, "PM1_EN" },  // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
@@ -605,6 +656,39 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
    printf("\n============= PMBASE ============\n\n");

switch (sb->device_id) {
+	case PCI_DEVICE_ID_INTEL_Z68:
+	case PCI_DEVICE_ID_INTEL_P67:
+	case PCI_DEVICE_ID_INTEL_UM67:
+	case PCI_DEVICE_ID_INTEL_HM65:
+	case PCI_DEVICE_ID_INTEL_H67:
+	case PCI_DEVICE_ID_INTEL_HM67:
+	case PCI_DEVICE_ID_INTEL_Q65:
+	case PCI_DEVICE_ID_INTEL_QS67:
+	case PCI_DEVICE_ID_INTEL_Q67:
+	case PCI_DEVICE_ID_INTEL_QM67:
+	case PCI_DEVICE_ID_INTEL_B65:
+	case PCI_DEVICE_ID_INTEL_C202:
+	case PCI_DEVICE_ID_INTEL_C204:
+	case PCI_DEVICE_ID_INTEL_C206:
+	case PCI_DEVICE_ID_INTEL_H61:
+	case PCI_DEVICE_ID_INTEL_Z77:
+	case PCI_DEVICE_ID_INTEL_Z75:
+	case PCI_DEVICE_ID_INTEL_Q77:
+	case PCI_DEVICE_ID_INTEL_Q75:
+	case PCI_DEVICE_ID_INTEL_B75:
+	case PCI_DEVICE_ID_INTEL_H77:
+	case PCI_DEVICE_ID_INTEL_C216:
+	case PCI_DEVICE_ID_INTEL_QM77:
+	case PCI_DEVICE_ID_INTEL_QS77:
+	case PCI_DEVICE_ID_INTEL_HM77:
+	case PCI_DEVICE_ID_INTEL_UM77:
+	case PCI_DEVICE_ID_INTEL_HM76:
+	case PCI_DEVICE_ID_INTEL_HM75:
+	case PCI_DEVICE_ID_INTEL_HM70:
+		pmbase = pci_read_word(sb, 0x40) & 0xff80;
+		pm_registers = pch_pm_registers;
+		size = ARRAY_SIZE(pch_pm_registers);
+		break;
    case PCI_DEVICE_ID_INTEL_ICH10R:
    	pmbase = pci_read_word(sb, 0x40) & 0xff80;
    	pm_registers = ich10_pm_registers;