coreboot-gerrit March 2013

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New patch to review for coreboot: 0a80427 armv7: import updated cache/MMU stuff from coreboot
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2975 -gerrit commit 0a80427956fd42ed11de6eb7147cac477959ad78 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Mar 25 15:02:29 2013 -0700 armv7: import updated cache/MMU stuff from coreboot This imports the newest cache and MMU code from coreboot. This time it's so new that it hasn't even been checked in to coreboot. However, this version at least allows DMA to work properly for the MSHC driver. So even if we rebase a few more times, this version is at least a step in the right direction. Note: This omits the stuff that sets up dcache policy since libpayload should not need to worry about that and it depends on cbmem stuff. Change-Id: Idd42b083e8019634aaaa44d5bf5b51db6c3912f5 Signed-off-by: David Hendricks <dhendrix(a)google.com> --- payloads/libpayload/arch/armv7/cache.c | 141 ++++++++++++++++++++++--- payloads/libpayload/include/armv7/arch/cache.h | 102 +++++++++++++----- 2 files changed, 203 insertions(+), 40 deletions(-) diff --git a/payloads/libpayload/arch/armv7/cache.c b/payloads/libpayload/arch/armv7/cache.c index 60d5f74..9fac442 100644 --- a/payloads/libpayload/arch/armv7/cache.c +++ b/payloads/libpayload/arch/armv7/cache.c @@ -26,7 +26,9 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * cache.c: Low-level cache operations for ARMv7 + * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R + * + * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition */ #include <inttypes.h> @@ -52,8 +54,8 @@ void tlb_invalidate_all(void) { /* * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction - * instruction vs. data TLBs is deprecated in ARMv7. But that doesn't - * really seem true for Cortex-A15? + * instruction vs. data TLBs is deprecated in ARMv7, however this does + * not seem to be the case as of Cortex-A15. */ tlbiall(); dtlbiall(); @@ -64,7 +66,8 @@ void tlb_invalidate_all(void) void icache_invalidate_all(void) { - /* icache can be entirely invalidated with one operation. + /* + * icache can be entirely invalidated with one operation. * Note: If branch predictors are architecturally-visible, ICIALLU * also performs a BPIALL operation (B2-1283 in arch manual) */ @@ -74,10 +77,17 @@ void icache_invalidate_all(void) enum dcache_op { OP_DCCISW, - OP_DCISW + OP_DCISW, + OP_DCCIMVAC, + OP_DCCMVAC, }; -/* do a dcache operation on entire cache by set/way */ +/* + * Do a dcache operation on entire cache by set/way. This is done for + * portability because mapping of memory address to cache location is + * implementation defined (See note on "Requirements for operations by + * set/way" in arch ref. manual). + */ static void dcache_op_set_way(enum dcache_op op) { uint32_t ccsidr; @@ -101,6 +111,8 @@ static void dcache_op_set_way(enum dcache_op op) /* FIXME: do we need to use CTR.DminLine here? */ linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4; + dsb(); + /* * Set/way operations require an interesting bit packing. See section * B4-35 in the ARMv7 Architecture Reference Manual: @@ -134,8 +146,7 @@ static void dcache_op_set_way(enum dcache_op op) } } } - - dsb(); + isb(); } void dcache_clean_invalidate_all(void) @@ -161,18 +172,116 @@ static unsigned int line_bytes(void) return size; } +/* + * Do a dcache operation by modified virtual address. This is useful for + * maintaining coherency in drivers which do DMA transfers and only need to + * perform cache maintenance on a particular memory range rather than the + * entire cache. + */ +static void dcache_op_mva(unsigned long addr, + unsigned long len, enum dcache_op op) +{ + unsigned long line, linesize; + + linesize = line_bytes(); + line = addr & ~(linesize - 1); + + dsb(); + while (line < addr + len) { + switch(op) { + case OP_DCCIMVAC: + dccimvac(line); + break; + default: + break; + } + line += linesize; + } + isb(); +} + +void dcache_clean_by_mva(unsigned long addr, unsigned long len) +{ + dcache_op_mva(addr, len, OP_DCCMVAC); +} + void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) { - unsigned long line, i; + dcache_op_mva(addr, len, OP_DCCIMVAC); +} + +void dcache_mmu_disable(void) +{ + uint32_t sctlr, csselr; + + /* ensure L1 data/unified cache is selected */ + csselr = read_csselr(); + csselr &= ~0xf; + write_csselr(csselr); + + dcache_clean_invalidate_all(); + + sctlr = read_sctlr(); + sctlr &= ~(SCTLR_C | SCTLR_M); + write_sctlr(sctlr); +} + + +void dcache_mmu_enable(void) +{ + uint32_t sctlr; - line = line_bytes(); - for (i = addr & ~(line - 1); i < addr + len - 1; i += line) - dccimvac(addr); + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr |= SCTLR_C | SCTLR_M; + write_sctlr(sctlr); } -/* FIXME: wrapper around imported mmu_setup() for now */ -extern void mmu_setup(unsigned long start, unsigned long size); -void mmu_setup_by_mva(unsigned long start, unsigned long size) +void armv7_invalidate_caches(void) { - mmu_setup(start, size); + uint32_t clidr; + int level; + + /* Invalidate branch predictor */ + bpiall(); + + /* Iterate thru each cache identified in CLIDR and invalidate */ + clidr = read_clidr(); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + uint32_t csselr; + + switch(ctype) { + case 0x0: + /* no cache */ + break; + case 0x1: + /* icache only */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + break; + case 0x2: + case 0x4: + /* dcache only or unified cache */ + dcache_invalidate_all(); + break; + case 0x3: + /* separate icache and dcache */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + + csselr = level < 1; + write_csselr(csselr); + dcache_invalidate_all(); + break; + default: + /* reserved */ + break; + } + } + + /* Invalidate TLB */ + tlb_invalidate_all(); } diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/armv7/arch/cache.h index 5125b8c..f074a3b 100644 --- a/payloads/libpayload/include/armv7/arch/cache.h +++ b/payloads/libpayload/include/armv7/arch/cache.h @@ -25,6 +25,8 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. + * + * cache.h: Cache maintenance API for ARMv7 */ #ifndef ARMV7_CACHE_H @@ -91,7 +93,7 @@ static inline void isb(void) /* invalidate entire data TLB */ static inline void dtlbiall(void) { - asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory"); } /* invalidate entire instruction TLB */ @@ -103,7 +105,33 @@ static inline void itlbiall(void) /* invalidate entire unified TLB */ static inline void tlbiall(void) { - asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory"); +} + +/* write data access control register (DACR) */ +static inline void write_dacr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val)); +} + +/* write translation table base register 0 (TTBR0) */ +static inline void write_ttbr0(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory"); +} + +/* read translation table base control register (TTBCR) */ +static inline uint32_t read_ttbcr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val)); + return val; +} + +/* write translation table base control register (TTBCR) */ +static inline void write_ttbcr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory"); } /* @@ -119,31 +147,31 @@ static inline void bpiall(void) /* data cache clean and invalidate by MVA to PoC */ static inline void dccimvac(unsigned long mva) { - asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva)); + asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva) : "memory"); } /* data cache invalidate by set/way */ static inline void dccisw(uint32_t val) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val)); -} - -/* data cache invalidate by set/way */ -static inline void dcisw(uint32_t val) -{ - asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val) : "memory"); } /* data cache clean by MVA to PoC */ static inline void dccmvac(unsigned long mva) { - asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva)); + asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory"); } /* data cache invalidate by MVA to PoC */ static inline void dcimvac(unsigned long mva) { - asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva)); + asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva) : "memory"); +} + +/* data cache invalidate by set/way */ +static inline void dcisw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val) : "memory"); } /* instruction cache invalidate all by PoU */ @@ -195,12 +223,12 @@ static inline void write_csselr(uint32_t val) static inline unsigned int read_sctlr(void) { unsigned int val; - asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) : : "cc"); + asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val)); return val; } /* write system control register (SCTLR) */ -static inline void write_sctlr(unsigned int val) +static inline void write_sctlr(uint32_t val) { asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc"); isb(); @@ -210,22 +238,48 @@ static inline void write_sctlr(unsigned int val) * Cache maintenance API */ -/* invalidate all TLBs */ -void tlb_invalidate_all(void); - -/* clean and invalidate entire dcache on current level (given by CCSELR) */ +/* dcache clean and invalidate all (on current level given by CCSELR) */ void dcache_clean_invalidate_all(void); -/* invalidate entire dcache on current level (given by CCSELR) */ -void dcache_invalidate_all(void); +/* dcache clean by modified virtual address to PoC */ +void dcache_clean_by_mva(unsigned long addr, unsigned long len); -/* invalidate and clean dcache by machine virtual address to PoC */ +/* dcache clean and invalidate by modified virtual address to PoC */ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); -/* invalidate entire icache on current level (given by CSSELR) */ +/* dcache invalidate all (on current level given by CCSELR) */ +void dcache_invalidate_all(void); + +/* dcache and MMU disable */ +void dcache_mmu_disable(void); + +/* dcache and MMU enable */ +void dcache_mmu_enable(void); + +/* icache invalidate all (on current level given by CSSELR) */ void icache_invalidate_all(void); -/* MMU setup by machine virtual address */ -void mmu_setup_by_mva(unsigned long start, unsigned long size); +/* tlb invalidate all */ +void tlb_invalidate_all(void); + +/* + * Generalized setup/init functions + */ + +/* invalidate all caches on ARMv7 */ +void armv7_invalidate_caches(void); + +/* mmu initialization (set page table address, set permissions, etc) */ +void mmu_init(void); + +enum dcache_policy { + DCACHE_OFF, + DCACHE_WRITEBACK, + DCACHE_WRITETHROUGH, +}; + +/* mmu range configuration (set dcache policy) */ +void mmu_config_range(unsigned long start_mb, unsigned long size_mb, + enum dcache_policy policy); #endif /* ARMV7_CACHE_H */

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New patch to review for coreboot: fdc44f5 armv7: import new cache maintenance API from coreboot
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2974 -gerrit commit fdc44f536b9c49bd0d937202023d9a6920390d5e Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 14 19:06:11 2013 -0700 armv7: import new cache maintenance API from coreboot This imports the new cache maintenance API from coreboot at commit bba8090. This is a BSD-licensed implementation which exposes cache maintenance opertaions necessary for payloads for things such as DMA transfers. Change-Id: I554676db89517bebc6edae4f7ab7e5882e6f986d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- payloads/libpayload/arch/armv7/Makefile.inc | 2 +- payloads/libpayload/arch/armv7/cache.c | 178 +++++++++++++++++++ payloads/libpayload/include/armv7/arch/cache.h | 231 +++++++++++++++++++++++++ 3 files changed, 410 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/armv7/Makefile.inc b/payloads/libpayload/arch/armv7/Makefile.inc index da0030e..9c7fe83 100644 --- a/payloads/libpayload/arch/armv7/Makefile.inc +++ b/payloads/libpayload/arch/armv7/Makefile.inc @@ -33,4 +33,4 @@ libc-y += timer.c coreboot.c util.S libc-y += virtual.c libc-y += memcpy.S memset.S libc-y += exception_asm.S exception.c - +libc-y += cache.c diff --git a/payloads/libpayload/arch/armv7/cache.c b/payloads/libpayload/arch/armv7/cache.c new file mode 100644 index 0000000..60d5f74 --- /dev/null +++ b/payloads/libpayload/arch/armv7/cache.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.c: Low-level cache operations for ARMv7 + */ + +#include <inttypes.h> + +#include <arch/cache.h> + +#define bitmask(high, low) ((1UL << (high)) + \ + ((1UL << (high)) - 1) - ((1UL << (low)) - 1)) + +/* Basic log2() implementation. Note: log2(0) is 0 for our purposes. */ +/* FIXME: src/include/lib.h is difficult to work with due to romcc */ +static unsigned long log2(unsigned long u) +{ + int i = 0; + + while (u >>= 1) + i++; + + return i; +} + +void tlb_invalidate_all(void) +{ + /* + * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction + * instruction vs. data TLBs is deprecated in ARMv7. But that doesn't + * really seem true for Cortex-A15? + */ + tlbiall(); + dtlbiall(); + itlbiall(); + isb(); + dsb(); +} + +void icache_invalidate_all(void) +{ + /* icache can be entirely invalidated with one operation. + * Note: If branch predictors are architecturally-visible, ICIALLU + * also performs a BPIALL operation (B2-1283 in arch manual) + */ + iciallu(); + isb(); +} + +enum dcache_op { + OP_DCCISW, + OP_DCISW +}; + +/* do a dcache operation on entire cache by set/way */ +static void dcache_op_set_way(enum dcache_op op) +{ + uint32_t ccsidr; + unsigned int associativity, num_sets, linesize_bytes; + unsigned int set, way; + unsigned int level; + + level = (read_csselr() >> 1) & 0x7; + + /* + * dcache must be invalidated by set/way for portability since virtual + * memory mapping is system-defined. The number of sets and + * associativity is given by CCSIDR. We'll use DCISW to invalidate the + * dcache. + */ + ccsidr = read_ccsidr(); + + /* FIXME: rounding up required here? */ + num_sets = ((ccsidr & bitmask(27, 13)) >> 13) + 1; + associativity = ((ccsidr & bitmask(12, 3)) >> 3) + 1; + /* FIXME: do we need to use CTR.DminLine here? */ + linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4; + + /* + * Set/way operations require an interesting bit packing. See section + * B4-35 in the ARMv7 Architecture Reference Manual: + * + * A: Log2(associativity) + * B: L+S + * L: Log2(linesize) + * S: Log2(num_sets) + * + * The bits are packed as follows: + * 31 31-A B B-1 L L-1 4 3 1 0 + * |---|-------------|--------|-------|-----|-| + * |Way| zeros | Set | zeros |level|0| + * |---|-------------|--------|-------|-----|-| + */ + for (way = 0; way < associativity; way++) { + for (set = 0; set < num_sets; set++) { + uint32_t val = 0; + val |= way << (32 - log2(associativity)); + val |= set << log2(linesize_bytes); + val |= level << 1; + switch(op) { + case OP_DCCISW: + dccisw(val); + break; + case OP_DCISW: + dcisw(val); + break; + default: + break; + } + } + } + + dsb(); +} + +void dcache_clean_invalidate_all(void) +{ + dcache_op_set_way(OP_DCCISW); +} + +void dcache_invalidate_all(void) +{ + dcache_op_set_way(OP_DCISW); +} + +static unsigned int line_bytes(void) +{ + uint32_t ccsidr; + unsigned int size; + + ccsidr = read_ccsidr(); + /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ + size = 1 << ((ccsidr & 0x7) + 2); /* words per line */ + size *= sizeof(unsigned int); /* bytes per line */ + + return size; +} + +void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) +{ + unsigned long line, i; + + line = line_bytes(); + for (i = addr & ~(line - 1); i < addr + len - 1; i += line) + dccimvac(addr); +} + +/* FIXME: wrapper around imported mmu_setup() for now */ +extern void mmu_setup(unsigned long start, unsigned long size); +void mmu_setup_by_mva(unsigned long start, unsigned long size) +{ + mmu_setup(start, size); +} diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/armv7/arch/cache.h new file mode 100644 index 0000000..5125b8c --- /dev/null +++ b/payloads/libpayload/include/armv7/arch/cache.h @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef ARMV7_CACHE_H +#define ARMV7_CACHE_H + +/* SCTLR bits */ +#define SCTLR_M (1 << 0) /* MMU enable */ +#define SCTLR_A (1 << 1) /* Alignment check enable */ +#define SCTLR_C (1 << 2) /* Data/unified cache enable */ +/* Bits 4:3 are reserved */ +#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */ +/* Bit 6 is reserved */ +#define SCTLR_B (1 << 7) /* Endianness */ +/* Bits 9:8 */ +#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */ +#define SCTLR_Z (1 << 11) /* Branch prediction enable */ +#define SCTLR_I (1 << 12) /* Instruction cache enable */ +#define SCTLR_V (1 << 13) /* Low/high exception vectors */ +#define SCTLR_RR (1 << 14) /* Round Robin select */ +/* Bits 16:15 are reserved */ +#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */ +/* Bit 18 is reserved */ +/* Bits 20:19 reserved virtualization not supported */ +#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ +#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission + implies PL1 XN */ +#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */ +#define SCTLR_U (1 << 22) /* Unaligned access behavior */ +#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */ +#define SCTLR_EE (1 << 25) /* Exception endianness */ +/* Bit 26 is reserved */ +#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */ +#define SCTLR_TRE (1 << 28) /* TEX remap enable */ +#define SCTLR_AFE (1 << 29) /* Access flag enable */ +#define SCTLR_TE (1 << 30) /* Thumb exception enable */ +/* Bit 31 is reserved */ + +/* + * Sync primitives + */ + +/* data memory barrier */ +static inline void dmb(void) +{ + asm volatile ("dmb" : : : "memory"); +} + +/* data sync barrier */ +static inline void dsb(void) +{ + asm volatile ("dsb" : : : "memory"); +} + +/* instruction sync barrier */ +static inline void isb(void) +{ + asm volatile ("isb" : : : "memory"); +} + +/* + * Low-level TLB maintenance operations + */ + +/* invalidate entire data TLB */ +static inline void dtlbiall(void) +{ + asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); +} + +/* invalidate entire instruction TLB */ +static inline void itlbiall(void) +{ + asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); +} + +/* invalidate entire unified TLB */ +static inline void tlbiall(void) +{ + asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); +} + +/* + * Low-level cache maintenance operations + */ + +/* branch predictor invalidate all */ +static inline void bpiall(void) +{ + asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); +} + +/* data cache clean and invalidate by MVA to PoC */ +static inline void dccimvac(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva)); +} + +/* data cache invalidate by set/way */ +static inline void dccisw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val)); +} + +/* data cache invalidate by set/way */ +static inline void dcisw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val)); +} + +/* data cache clean by MVA to PoC */ +static inline void dccmvac(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva)); +} + +/* data cache invalidate by MVA to PoC */ +static inline void dcimvac(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva)); +} + +/* instruction cache invalidate all by PoU */ +static inline void iciallu(void) +{ + asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); +} + +/* + * Cache co-processor (CP15) access functions + */ + +/* read cache level ID register (CLIDR) */ +static inline uint32_t read_clidr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); + return val; +} + +/* read cache size ID register register (CCSIDR) */ +static inline uint32_t read_ccsidr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); + return val; +} + +/* read cache size selection register (CSSELR) */ +static inline uint32_t read_csselr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val)); + return val; +} + +/* write to cache size selection register (CSSELR) */ +static inline void write_csselr(uint32_t val) +{ + /* + * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd) + * Bit 0 - 0 = data or unified cache, 1 = instruction cache + */ + asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val)); + isb(); /* ISB to sync the change to CCSIDR */ +} + +/* read system control register (SCTLR) */ +static inline unsigned int read_sctlr(void) +{ + unsigned int val; + asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) : : "cc"); + return val; +} + +/* write system control register (SCTLR) */ +static inline void write_sctlr(unsigned int val) +{ + asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc"); + isb(); +} + +/* + * Cache maintenance API + */ + +/* invalidate all TLBs */ +void tlb_invalidate_all(void); + +/* clean and invalidate entire dcache on current level (given by CCSELR) */ +void dcache_clean_invalidate_all(void); + +/* invalidate entire dcache on current level (given by CCSELR) */ +void dcache_invalidate_all(void); + +/* invalidate and clean dcache by machine virtual address to PoC */ +void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); + +/* invalidate entire icache on current level (given by CSSELR) */ +void icache_invalidate_all(void); + +/* MMU setup by machine virtual address */ +void mmu_setup_by_mva(unsigned long start, unsigned long size); + +#endif /* ARMV7_CACHE_H */

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New patch to review for coreboot: 981ac13 lynxpoint: Fix LP clock gating setup for LPC
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2973 -gerrit commit 981ac13690c90a209b91b8c014e091e5209c9eb7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 22 11:24:45 2013 -0700 lynxpoint: Fix LP clock gating setup for LPC This bit offset is incorrect and should only be set based on another bit in a different register. Change-Id: I6037534236e3a4a5d15e15011ed9b5040b435eaf Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/lpc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 079c7ed..f6c64c5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -461,7 +461,10 @@ static void enable_lp_clock_gating(device_t dev) RCBA32_OR(0x900, 0x0000031f); reg32 = RCBA32(CG); - reg32 |= (1 << 31); // LPC Dynamic + if (RCBA32(0x3454) & (1 << 4)) + reg32 &= ~(1 << 29); // LPC Dynamic + else + reg32 |= (1 << 29); // LPC Dynamic reg32 |= (1 << 30); // LP LPC reg32 |= (1 << 28); // GPIO Dynamic reg32 |= (1 << 27); // HPET Dynamic

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New patch to review for coreboot: 59dcb34 wtm2: Enable SerialIO devices in ACPI mode
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2972 -gerrit commit 59dcb340aa25d621e74dc4d2230c1edf07f73d45 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 22 11:22:24 2013 -0700 wtm2: Enable SerialIO devices in ACPI mode This enables all of the SerialIO devices and sets the flag to put them in ACPI mode. Change-Id: I7436c47d26028e95bbefafc320854c7cc34a4d44 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/wtm2/devicetree.cb | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 80c8627..5e1ca3a 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -51,20 +51,24 @@ chip northbridge/intel/haswell register "sata_ahci" = "0x1" register "sata_port_map" = "0x2" + register "sio_acpi_mode" = "1" + register "sio_i2c0_voltage" = "1" # 1.8V + register "sio_i2c1_voltage" = "1" # 1.8V + device pci 13.0 on end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 on end # GSPI0 + device pci 15.4 on end # GSPI1 + device pci 15.5 on end # UART0 + device pci 15.6 on end # UART1 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO + device pci 17.0 on end # SDIO device pci 19.0 on end # GbE device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe Port #1

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New patch to review for coreboot: 7fddce3 lynxpoint: Basic configuration of SerialIO devices
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2971 -gerrit commit 7fddce33641774903053fe5db7617a3300b46eb4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 22 11:21:14 2013 -0700 lynxpoint: Basic configuration of SerialIO devices This adds configuration of SerialIO devices in the Lynxpoint-LP chipset. This includes DMA, I2C, SPI, UART, and SDIO controllers. There is assorted magic setup necessary for the devices and while it is similar for each device there are subtle differences in some register settings. These devices must be put into "ACPI Mode" in order to take advantage of S0ix. When in ACPI mode the allocated PCI BARs must be passed to ACPI so it can be relayed to the OS. When the devices are in ACPI mode BAR0+BAR1 is saved into ACPI NVS and then updated and returned when the OS calls _CRS. Note that is is not entirely complete yet. We need to update the IASL compiler in our build environment to support ACPI 5.0 in order to be able to pass the FixedDMA entries to the kernel. There are also no ACPI methods defined yet to do D0->D3->D0 transitions for actually entering/exiting S0ix states. This is hard to test right now because our kernel does not support any of these devices in ACPI mode. I was able to build and test the upstream bleeding-edge branch of the linux-pm git tree. With that tree I was able to enumerate and load the driver for the DesignWare I2C driver and attempt to probe the I2C bus -- although there are no devices attatched. I am also able to see the resources from ACPI in /proc/iomem get reserved properly in the kernel. Change-Id: Ie311addd6a25f3b7edf3388fe68c1cd691a0a500 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/Makefile.inc | 1 + src/southbridge/intel/lynxpoint/acpi/pch.asl | 5 + src/southbridge/intel/lynxpoint/acpi/serialio.asl | 470 ++++++++++++++++++++++ src/southbridge/intel/lynxpoint/chip.h | 7 + src/southbridge/intel/lynxpoint/pch.h | 31 ++ src/southbridge/intel/lynxpoint/serialio.c | 267 ++++++++++++ 6 files changed, 781 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 04fa2f8..7d1f894 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += sata.c ramstage-y += usb_ehci.c ramstage-y += me_9.x.c ramstage-y += smbus.c +ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c ramstage-y += rcba.c ramstage-y += me_status.c diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index ce8f0e0..f5cf6ae 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -267,6 +267,11 @@ Scope(\) // SMBus 0:1f.3 #include "smbus.asl" +// Serial IO +#if CONFIG_INTEL_LYNXPOINT_LP +#include "serialio.asl" +#endif + Method (_OSC, 4) { /* Check for proper GUID */ diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl new file mode 100644 index 0000000..6ea23c6 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -0,0 +1,470 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Intel LynxPoint Serial IO Devices in ACPI Mode + +// Serial IO Device BAR0 and BAR1 is 4KB +#define SIO_BAR_LEN 0x1000 + +// Serial IO Resource Consumption for BAR1 +Device (SIOR) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 4) + + Name (RBUF, ResourceTemplate() + { + // Serial IO BAR1 (PCI config space) resources + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D0) // SDMA + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D1) // I2C0 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D2) // I2C1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D3) // SPI0 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D4) // SPI1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D5) // UART0 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D6) // UART1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D7) // SDIO + }) + + // Update BAR1 address and length if set in NVS + Method (_CRS, 0, NotSerialized) + { + // SDMA + If (LNotEqual (\S0B1, Zero)) { + CreateDwordField (^RBUF, ^B1D0._BAS, B0AD) + CreateDwordField (^RBUF, ^B1D0._LEN, B0LN) + Store (\S0B1, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + // I2C0 + If (LNotEqual (\S1B1, Zero)) { + CreateDwordField (^RBUF, ^B1D1._BAS, B1AD) + CreateDwordField (^RBUF, ^B1D1._LEN, B1LN) + Store (\S1B1, B1AD) + Store (SIO_BAR_LEN, B1LN) + } + + // I2C1 + If (LNotEqual (\S2B1, Zero)) { + CreateDwordField (^RBUF, ^B1D2._BAS, B2AD) + CreateDwordField (^RBUF, ^B1D2._LEN, B2LN) + Store (\S2B1, B2AD) + Store (SIO_BAR_LEN, B2LN) + } + + // SPI0 + If (LNotEqual (\S3B1, Zero)) { + CreateDwordField (^RBUF, ^B1D3._BAS, B3AD) + CreateDwordField (^RBUF, ^B1D3._LEN, B3LN) + Store (\S3B1, B3AD) + Store (SIO_BAR_LEN, B3LN) + } + + // SPI1 + If (LNotEqual (\S4B1, Zero)) { + CreateDwordField (^RBUF, ^B1D4._BAS, B4AD) + CreateDwordField (^RBUF, ^B1D4._LEN, B4LN) + Store (\S4B1, B4AD) + Store (SIO_BAR_LEN, B4LN) + } + + // UART0 + If (LNotEqual (\S5B1, Zero)) { + CreateDwordField (^RBUF, ^B1D5._BAS, B5AD) + CreateDwordField (^RBUF, ^B1D5._LEN, B5LN) + Store (\S5B1, B5AD) + Store (SIO_BAR_LEN, B5LN) + } + + // UART1 + If (LNotEqual (\S6B1, Zero)) { + CreateDwordField (^RBUF, ^B1D6._BAS, B6AD) + CreateDwordField (^RBUF, ^B1D6._LEN, B6LN) + Store (\S6B1, B6AD) + Store (SIO_BAR_LEN, B6LN) + } + + // SDIO + If (LNotEqual (\S7B1, Zero)) { + CreateDwordField (^RBUF, ^B1D7._BAS, B7AD) + CreateDwordField (^RBUF, ^B1D7._LEN, B7LN) + Store (\S7B1, B7AD) + Store (SIO_BAR_LEN, B7LN) + } + + Return (RBUF) + } +} + +Device (SDMA) +{ + // Serial IO DMA Controller + Name (_HID, "INTL9C60") + Name (_UID, 1) + Name (_ADR, 0x00150000) + + // BAR0 is assigned during PCI enumeration and saved into NVS + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + }) + + Method (_CRS, 0, NotSerialized) + { + // Update BAR0 address and length if set in NVS + If (LNotEqual (\S0B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\S0B0, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S0B0, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } +} + +Device (I2C0) +{ + // Serial IO I2C0 Controller + Name (_HID, "INT33C2") + Name (_CID, "INT33C2") + Name (_UID, 1) + Name (_ADR, 0x00150001) + + // BAR0 is assigned during PCI enumeration and saved into NVS + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + }) + + // DMA channels are only used if Serial IO DMA controller is enabled + Name (DBUF, ResourceTemplate () + { + // TODO: Need to update IASL to support FixedDMA + //FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx + //FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx + }) + + Method (_CRS, 0, NotSerialized) + { + // Update BAR0 address and length if set in NVS + If (LNotEqual (\S1B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\S1B0, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + // Check if Serial IO DMA Controller is enabled + If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + Return (ConcatenateResTemplate (RBUF, DBUF)) + } Else { + Return (RBUF) + } + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S1B0, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } +} + +Device (I2C1) +{ + // Serial IO I2C1 Controller + Name (_HID, "INT33C3") + Name (_CID, "INT33C3") + Name (_UID, 1) + Name (_ADR, 0x00150002) + + // BAR0 is assigned during PCI enumeration and saved into NVS + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + }) + + // DMA channels are only used if Serial IO DMA controller is enabled + Name (DBUF, ResourceTemplate () + { + // TODO: Need to update IASL to support FixedDMA + //FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx + //FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx + }) + + Method (_CRS, 0, NotSerialized) + { + // Update BAR0 address and length if set in NVS + If (LNotEqual (\S2B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\S2B0, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + // Check if Serial IO DMA Controller is enabled + If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + Return (ConcatenateResTemplate (RBUF, DBUF)) + } Else { + Return (RBUF) + } + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S2B0, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } +} + +Device (SPI0) +{ + // Serial IO SPI0 Controller + Name (_HID, "INT33C0") + Name (_CID, "INT33C0") + Name (_UID, 1) + Name (_ADR, 0x00150003) + + // BAR0 is assigned during PCI enumeration and saved into NVS + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + }) + + Method (_CRS, 0, NotSerialized) + { + // Update BAR0 address and length if set in NVS + If (LNotEqual (\S3B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\S3B0, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S3B0, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } +} + +Device (SPI1) +{ + // Serial IO SPI1 Controller + Name (_HID, "INT33C1") + Name (_CID, "INT33C1") + Name (_UID, 1) + Name (_ADR, 0x00150004) + + // BAR0 is assigned during PCI enumeration and saved into NVS + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + }) + + // DMA channels are only used if Serial IO DMA controller is enabled + Name (DBUF, ResourceTemplate () + { + // TODO: Need to update IASL to support FixedDMA + //FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx + //FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx + }) + + Method (_CRS, 0, NotSerialized) + { + // Update BAR0 address and length if set in NVS + If (LNotEqual (\S4B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\S4B0, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + // Check if Serial IO DMA Controller is enabled + If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + Return (ConcatenateResTemplate (RBUF, DBUF)) + } Else { + Return (RBUF) + } + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S4B0, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } +} + +Device (UAR0) +{ + // Serial IO UART0 Controller + Name (_HID, "INT33C4") + Name (_CID, "INT33C4") + Name (_UID, 1) + Name (_ADR, 0x00150005) + + // BAR0 is assigned during PCI enumeration and saved into NVS + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} + }) + + // DMA channels are only used if Serial IO DMA controller is enabled + Name (DBUF, ResourceTemplate () + { + // TODO: Need to update IASL to support FixedDMA + //FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx + //FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx + }) + + Method (_CRS, 0, NotSerialized) + { + // Update BAR0 address and length if set in NVS + If (LNotEqual (\S5B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\S5B0, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + // Check if Serial IO DMA Controller is enabled + If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + Return (ConcatenateResTemplate (RBUF, DBUF)) + } Else { + Return (RBUF) + } + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S5B0, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } +} + +Device (UAR1) +{ + // Serial IO UART1 Controller + Name (_HID, "INT33C5") + Name (_CID, "INT33C5") + Name (_UID, 1) + Name (_ADR, 0x00150006) + + // BAR0 is assigned during PCI enumeration and saved into NVS + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} + }) + + Method (_CRS, 0, NotSerialized) + { + // Update BAR0 address and length if set in NVS + If (LNotEqual (\S6B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\S6B0, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S6B0, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } +} + +Device (SDIO) +{ + // Serial IO SDIO Controller + Name (_HID, "INT33C6") + Name (_CID, "PNP0D40") + Name (_UID, 1) + Name (_ADR, 0x00170000) + + // BAR0 is assigned during PCI enumeration and saved into NVS + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5} + }) + + Method (_CRS, 0, NotSerialized) + { + // Update BAR0 address and length if set in NVS + If (LNotEqual (\S7B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\S7B0, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S7B0, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } +} diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 95bd087..70f3e63 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -85,6 +85,13 @@ struct southbridge_intel_lynxpoint_config { /* Enable linear PCIe Root Port function numbers starting at zero */ uint8_t pcie_port_coalesce; + + /* Serial IO configuration */ + /* Put devices into ACPI mode instead of a PCI device */ + uint8_t sio_acpi_mode; + /* I2C voltage select: 0=3.3V 1=1.8V */ + uint8_t sio_i2c0_voltage; + uint8_t sio_i2c1_voltage; }; extern struct chip_operations southbridge_intel_lynxpoint_ops; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index ee2efd5..76672bc 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -341,11 +341,13 @@ unsigned get_gpios(const int *gpio_num_array); #define SIO_IOBP_PORTCTRL6 0xcb000260 /* SPI1 D21:F4 */ #define SIO_IOBP_PORTCTRL7 0xcb000268 /* UART0 D21:F5 */ #define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */ +#define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8)) /* PORTCTRL 2-8 have the same layout */ #define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21) #define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20) #define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18) #define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2) +#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1) #define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */ #define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */ #define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */ @@ -356,6 +358,34 @@ unsigned get_gpios(const int *gpio_num_array); #define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */ #define SIO_IOBP_FUNCDIS_DIS (1 << 8) +/* Serial IO Devices */ +#define SIO_ID_SDMA 0 /* D21:F0 */ +#define SIO_ID_I2C0 1 /* D21:F1 */ +#define SIO_ID_I2C1 2 /* D21:F2 */ +#define SIO_ID_SPI0 3 /* D21:F3 */ +#define SIO_ID_SPI1 4 /* D21:F4 */ +#define SIO_ID_UART0 5 /* D21:F5 */ +#define SIO_ID_UART1 6 /* D21:F6 */ +#define SIO_ID_SDIO 7 /* D23:F0 */ + +#define SIO_REG_PPR_RST 0x804 +#define SIO_REG_PPR_RST_ASSERT 0x3 +#define SIO_REG_PPR_GEN 0x808 +#define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2) +#define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3) +#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3) +#define SIO_REG_AUTO_LTR 0x814 + +#define SIO_REG_SDIO_PPR_GEN 0x1008 +#define SIO_REG_SDIO_PPR_SW_LTR 0x1010 +#define SIO_REG_SDIO_PPR_CMD12 0x3c +#define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30) + +#define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */ +#define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */ +#define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */ +#define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */ + /* PCI Configuration Space (D31:F3): SMBus */ #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) #define SMB_BASE 0x20 @@ -534,6 +564,7 @@ unsigned get_gpios(const int *gpio_num_array); #define D20IR 0x3160 /* 16bit */ #define D21IR 0x3164 /* 16bit */ #define D19IR 0x3168 /* 16bit */ +#define ACPIIRQEN 0x31e0 /* 32bit */ #define OIC 0x31fe /* 16bit */ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c new file mode 100644 index 0000000..11d6a36 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -0,0 +1,267 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include <stdlib.h> +#include "pch.h" +#include "nvs.h" + +/* Put Serial IO D21:F0-F6 device into desired mode. */ +static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode) +{ + u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT; + + /* Snoop select 1. */ + portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1); + + /* Set interrupt pin. */ + portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin); + + if (acpi_mode) { + /* Enable ACPI interrupt mode. */ + portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN; + + /* Disable PCI config space. */ + portctrl |= SIO_IOBP_PORTCTRL_PCI_CONF_DIS; + } + + pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl); +} + +/* Put Serial IO D23:F0 device into desired mode. */ +static void serialio_d23_mode(int acpi_mode) +{ + u32 portctrl = 0; + + /* Snoop select 1. */ + pch_iobp_update(SIO_IOBP_PORTCTRL1, 0, + SIO_IOBP_PORTCTRL1_SNOOP_SELECT(1)); + + if (acpi_mode) { + /* Enable ACPI interrupt mode. */ + portctrl |= SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN; + + /* Disable PCI config space. */ + portctrl |= SIO_IOBP_PORTCTRL0_PCI_CONF_DIS; + } + + pch_iobp_update(SIO_IOBP_PORTCTRL0, 0, portctrl); +} + +/* Enable LTR Auto Mode for D21:F1-F6. */ +static void serialio_d21_ltr(struct resource *bar0) +{ + u32 reg; + + /* 1. Program BAR0 + 808h[2] = 0b */ + reg = read32(bar0->base + SIO_REG_PPR_GEN); + reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK; + write32(bar0->base + SIO_REG_PPR_GEN, reg); + + /* 2. Program BAR0 + 804h[1:0] = 00b */ + reg = read32(bar0->base + SIO_REG_PPR_RST); + reg &= ~SIO_REG_PPR_RST_ASSERT; + write32(bar0->base + SIO_REG_PPR_RST, reg); + + /* 3. Program BAR0 + 804h[1:0] = 11b */ + reg = read32(bar0->base + SIO_REG_PPR_RST); + reg |= SIO_REG_PPR_RST_ASSERT; + write32(bar0->base + SIO_REG_PPR_RST, reg); + + /* 4. Program BAR0 + 814h[31:0] = 00000000h */ + write32(bar0->base + SIO_REG_AUTO_LTR, 0); +} + +/* Enable LTR Auto Mode for D23:F0. */ +static void serialio_d23_ltr(struct resource *bar0) +{ + u32 reg; + + /* Program BAR0 + 1008h[2] = 1b */ + reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN); + reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK; + write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg); + + /* Program BAR0 + 1010h = 0x00000000 */ + write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0); + + /* Program BAR0 + 3Ch[30] = 1b */ + reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12); + reg |= SIO_REG_SDIO_PPR_CMD12_B30; + write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg); +} + +/* Select I2C voltage of 1.8V or 3.3V. */ +static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage) +{ + u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN); + reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK; + reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage); + write32(bar0->base + SIO_REG_PPR_GEN, reg32); +} + +/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */ +static void serialio_init_once(int acpi_mode) +{ + if (acpi_mode) { + /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */ + RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5)); + } + + /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */ + pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f); + + /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ + pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); +} + +static void serialio_init(struct device *dev) +{ + struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + struct resource *bar0, *bar1; + int sio_index = -1; + + printk(BIOS_DEBUG, "Initializing Serial IO device\n"); + + /* Find BAR0 and BAR1 */ + bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!bar0) + return; + bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); + if (!bar1) + return; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(21, 0): /* SDMA */ + sio_index = SIO_ID_SDMA; + serialio_init_once(config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTB, + config->sio_acpi_mode); + break; + case PCI_DEVFN(21, 1): /* I2C0 */ + sio_index = SIO_ID_I2C0; + serialio_d21_ltr(bar0); + serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); + serialio_d21_mode(sio_index, SIO_PIN_INTC, + config->sio_acpi_mode); + break; + case PCI_DEVFN(21, 2): /* I2C1 */ + sio_index = SIO_ID_I2C1; + serialio_d21_ltr(bar0); + serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); + serialio_d21_mode(sio_index, SIO_PIN_INTC, + config->sio_acpi_mode); + break; + case PCI_DEVFN(21, 3): /* SPI0 */ + sio_index = SIO_ID_SPI0; + serialio_d21_ltr(bar0); + serialio_d21_mode(sio_index, SIO_PIN_INTC, + config->sio_acpi_mode); + break; + case PCI_DEVFN(21, 4): /* SPI1 */ + sio_index = SIO_ID_SPI1; + serialio_d21_ltr(bar0); + serialio_d21_mode(sio_index, SIO_PIN_INTC, + config->sio_acpi_mode); + break; + case PCI_DEVFN(21, 5): /* UART0 */ + sio_index = SIO_ID_UART0; + serialio_d21_ltr(bar0); + serialio_d21_mode(sio_index, SIO_PIN_INTD, + config->sio_acpi_mode); + break; + case PCI_DEVFN(21, 6): /* UART1 */ + sio_index = SIO_ID_UART1; + serialio_d21_ltr(bar0); + serialio_d21_mode(sio_index, SIO_PIN_INTD, + config->sio_acpi_mode); + break; + case PCI_DEVFN(23, 0): /* SDIO */ + sio_index = SIO_ID_SDIO; + serialio_d23_ltr(bar0); + serialio_d23_mode(config->sio_acpi_mode); + break; + default: + return; + } + + if (config->sio_acpi_mode) { + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0 and BAR1 to ACPI NVS */ + gnvs->s0b[sio_index] = (u32)bar0->base; + gnvs->s1b[sio_index] = (u32)bar1->base; + } +} + +static void serialio_set_subsystem(device_t dev, unsigned vendor, + unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = serialio_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = serialio_init, + .ops_pci = &pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + 0x9c60, /* 0:15.0 - SDMA */ + 0x9c61, /* 0:15.1 - I2C0 */ + 0x9c62, /* 0:15.2 - I2C1 */ + 0x9c65, /* 0:15.3 - SPI0 */ + 0x9c66, /* 0:15.4 - SPI1 */ + 0x9c63, /* 0:15.5 - UART0 */ + 0x9c64, /* 0:15.6 - UART1 */ + 0x9c35, /* 0:17.0 - SDIO */ + 0 +}; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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New patch to review for coreboot: f0e4c98 lynxpoint: Move ACPI NVS into separate CBMEM table
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2970 -gerrit commit f0e4c9818aec82b6d46201764543cffb14b268b5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 22 11:08:39 2013 -0700 lynxpoint: Move ACPI NVS into separate CBMEM table The ACPI NVS region was setup in place and there was a CBMEM table that pointed to it. In order to be able to use NVS earlier the CBMEM region is allocated for NVS itself during the LPC device init and the ACPI tables point to it in CBMEM. The current cbmem region is renamed to ACPI_GNVS_PTR to indicate that it is really a pointer to the GNVS and does not actually contain the GNVS. Change-Id: I31ace432411c7f825d86ca75c63dd79cd658e891 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/arch/x86/boot/acpi.c | 4 ++-- src/include/cbmem.h | 1 + src/lib/cbmem_info.c | 1 + src/mainboard/intel/baskingridge/acpi_tables.c | 20 +++++++++++++------- src/mainboard/intel/wtm1/acpi_tables.c | 20 +++++++++++++------- src/mainboard/intel/wtm2/acpi_tables.c | 20 +++++++++++++------- src/southbridge/intel/lynxpoint/lpc.c | 10 ++++++++++ 7 files changed, 53 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index b04cbe5..e73da95 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -630,7 +630,7 @@ void suspend_resume(void) wake_vec = acpi_find_wakeup_vector(); if (wake_vec) { #if CONFIG_HAVE_SMI_HANDLER - u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS); + u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS_PTR); /* Restore GNVS pointer in SMM if found */ if (gnvs_address && *gnvs_address) { @@ -794,7 +794,7 @@ void acpi_jump_to_wakeup(void *vector) void acpi_save_gnvs(u32 gnvs_address) { - u32 *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + u32 *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS_PTR, sizeof(*gnvs)); if (gnvs) *gnvs = gnvs_address; } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5b19207..219dbfc 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -51,6 +51,7 @@ #define CBMEM_ID_GDT 0x4c474454 #define CBMEM_ID_ACPI 0x41435049 #define CBMEM_ID_ACPI_GNVS 0x474e5653 +#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650 #define CBMEM_ID_CBTABLE 0x43425442 #define CBMEM_ID_PIRQ 0x49525154 #define CBMEM_ID_MPTABLE 0x534d5054 diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index 5b02f2d..ad8c890 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -33,6 +33,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_RESUME, "ACPI RESUME" }, { CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, + { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, { CBMEM_ID_SMBIOS, "SMBIOS " }, { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, { CBMEM_ID_MRCDATA, "MRC DATA " }, diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index d94251e..c4adcd7 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -70,7 +70,6 @@ static void acpi_update_thermal_table(global_nvs_t *gnvs) static void acpi_create_gnvs(global_nvs_t *gnvs) { - memset((void *)gnvs, 0, sizeof(*gnvs)); gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); @@ -165,6 +164,7 @@ unsigned long write_acpi_tables(unsigned long start) #endif acpi_header_t *ssdt; acpi_header_t *dsdt; + global_nvs_t *gnvs; current = start; @@ -240,22 +240,28 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; acpi_add_table(rsdp, mcfg); - /* Pack GNVS into the ACPI table area */ + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); - *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes - acpi_save_gnvs(current); + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); break; } } /* And fill it */ - acpi_create_gnvs((global_nvs_t *)current); + acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures((void *)current, NULL, NULL); + smm_setup_structures(gnvs, NULL, NULL); current += sizeof(global_nvs_t); ALIGN_CURRENT; diff --git a/src/mainboard/intel/wtm1/acpi_tables.c b/src/mainboard/intel/wtm1/acpi_tables.c index 6f5a1dd..16a1c6a 100644 --- a/src/mainboard/intel/wtm1/acpi_tables.c +++ b/src/mainboard/intel/wtm1/acpi_tables.c @@ -70,7 +70,6 @@ static void acpi_update_thermal_table(global_nvs_t *gnvs) static void acpi_create_gnvs(global_nvs_t *gnvs) { - memset((void *)gnvs, 0, sizeof(*gnvs)); gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); @@ -162,6 +161,7 @@ unsigned long write_acpi_tables(unsigned long start) #endif acpi_header_t *ssdt; acpi_header_t *dsdt; + global_nvs_t *gnvs; current = start; @@ -237,22 +237,28 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; acpi_add_table(rsdp, mcfg); - /* Pack GNVS into the ACPI table area */ + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); - *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes - acpi_save_gnvs(current); + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); break; } } /* And fill it */ - acpi_create_gnvs((global_nvs_t *)current); + acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures((void *)current, NULL, NULL); + smm_setup_structures(gnvs, NULL, NULL); current += sizeof(global_nvs_t); ALIGN_CURRENT; diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 6f5a1dd..16a1c6a 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -70,7 +70,6 @@ static void acpi_update_thermal_table(global_nvs_t *gnvs) static void acpi_create_gnvs(global_nvs_t *gnvs) { - memset((void *)gnvs, 0, sizeof(*gnvs)); gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); @@ -162,6 +161,7 @@ unsigned long write_acpi_tables(unsigned long start) #endif acpi_header_t *ssdt; acpi_header_t *dsdt; + global_nvs_t *gnvs; current = start; @@ -237,22 +237,28 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; acpi_add_table(rsdp, mcfg); - /* Pack GNVS into the ACPI table area */ + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); - *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes - acpi_save_gnvs(current); + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); break; } } /* And fill it */ - acpi_create_gnvs((global_nvs_t *)current); + acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures((void *)current, NULL, NULL); + smm_setup_structures(gnvs, NULL, NULL); current += sizeof(global_nvs_t); ALIGN_CURRENT; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6b01489..079c7ed 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -32,6 +32,9 @@ #include <cpu/cpu.h> #include <cpu/x86/smm.h> #include <elog.h> +#include <cbmem.h> +#include <string.h> +#include "nvs.h" #include "pch.h" #define NMI_OFF 0 @@ -696,6 +699,8 @@ static void pch_lpc_add_io_resources(device_t dev) static void pch_lpc_read_resources(device_t dev) { + global_nvs_t *gnvs; + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -704,6 +709,11 @@ static void pch_lpc_read_resources(device_t dev) /* Add IO resources. */ pch_lpc_add_io_resources(dev); + + /* Allocate ACPI NVS in CBMEM */ + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + if (gnvs) + memset(gnvs, 0, sizeof(global_nvs_t)); } static void pch_lpc_enable_resources(device_t dev)

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New patch to review for coreboot: fc8732d lynxpoint: Rework ACPI NVS to add new SerialIO variables
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2969 -gerrit commit fc8732dd0ac1b5d3637662f56bd46d2687f13f2a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 22 11:05:38 2013 -0700 lynxpoint: Rework ACPI NVS to add new SerialIO variables This reclaims space in ACPI NVS by removing unused fields and adds new fields for SerialIO BARs which will be used to communicate the allocated resources to ACPI. Change-Id: I002bf396cf7b495bc5b7e54b741527e507aff716 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 53 ++++++++++------------ src/southbridge/intel/lynxpoint/nvs.h | 37 +++------------ 2 files changed, 31 insertions(+), 59 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 2fe092d..8f6c825 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -106,36 +106,31 @@ Field (GNVS, ByteAcc, NoLock, Preserve) DID3, 32, // 0x4f - Device ID 3 DID4, 32, // 0x53 - Device ID 4 DID5, 32, // 0x57 - Device ID 5 - /* Backlight Control */ - Offset (0x64), - BLCS, 8, // 0x64 - Backlight control possible? - BRTL, 8, // 0x65 - Brightness Level - ODDS, 8, // 0x66 - /* Ambient Light Sensors */ - Offset (0x6e), - ALSE, 8, // 0x6e - ALS enable - ALAF, 8, // 0x6f - Ambient light adjustment factor - LLOW, 8, // 0x70 - LUX Low - LHIH, 8, // 0x71 - LUX High - /* EMA */ - Offset (0x78), - EMAE, 8, // 0x78 - EMA enable - EMAP, 16, // 0x79 - EMA pointer - EMAL, 16, // 0x7b - EMA length - /* MEF */ - Offset (0x82), - MEFE, 8, // 0x82 - MEF enable + /* TPM support */ - Offset (0x8c), - TPMP, 8, // 0x8c - TPM - TPME, 8, // 0x8d - TPM enable - /* SATA */ - Offset (0x96), - GTF0, 56, // 0x96 - GTF task file buffer for port 0 - GTF1, 56, // 0x9d - GTF task file buffer for port 1 - GTF2, 56, // 0xa4 - GTF task file buffer for port 2 - IDEM, 8, // 0xab - IDE mode (compatible / enhanced) - IDET, 8, // 0xac - IDE + Offset (0x5b), + TPMP, 8, // 0x5b - TPM Present + TPME, 8, // 0x5c - TPM Enable + + /* LynxPoint Serial IO device BARs */ + Offset (0x60), + S0B0, 32, // 0x60 - D21:F0 Serial IO SDMA BAR0 + S1B0, 32, // 0x64 - D21:F1 Serial IO I2C0 BAR0 + S2B0, 32, // 0x68 - D21:F2 Serial IO I2C1 BAR0 + S3B0, 32, // 0x6c - D21:F3 Serial IO SPI0 BAR0 + S4B0, 32, // 0x70 - D21:F4 Serial IO SPI1 BAR0 + S5B0, 32, // 0x74 - D21:F5 Serial IO UAR0 BAR0 + S6B0, 32, // 0x78 - D21:F6 Serial IO UAR1 BAR0 + S7B0, 32, // 0x7c - D23:F0 Serial IO SDIO BAR0 + S0B1, 32, // 0x80 - D21:F0 Serial IO SDMA BAR1 + S1B1, 32, // 0x84 - D21:F1 Serial IO I2C0 BAR1 + S2B1, 32, // 0x88 - D21:F2 Serial IO I2C1 BAR1 + S3B1, 32, // 0x8c - D21:F3 Serial IO SPI0 BAR1 + S4B1, 32, // 0x90 - D21:F4 Serial IO SPI1 BAR1 + S5B1, 32, // 0x94 - D21:F5 Serial IO UAR0 BAR1 + S6B1, 32, // 0x98 - D21:F6 Serial IO UAR1 BAR1 + S7B1, 32, // 0x9c - D23:F0 Serial IO SDIO BAR1 + /* IGD OpRegion */ Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index b8506d4..3df1da1 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -83,37 +83,14 @@ typedef struct { u16 sste; /* 0x44 - set display state */ u8 ndid; /* 0x46 - number of device ids */ u32 did[5]; /* 0x47 - 5b device id 1..5 */ - u8 rsvd5[0x9]; - /* Backlight Control */ - u8 blcs; /* 0x64 - Backlight Control possible */ - u8 brtl; - u8 odds; - u8 rsvd6[0x7]; - /* Ambient Light Sensors*/ - u8 alse; /* 0x6e - ALS enable */ - u8 alaf; - u8 llow; - u8 lhih; - u8 rsvd7[0x6]; - /* Extended Mobile Access */ - u8 emae; /* 0x78 - EMA enable */ - u16 emap; /* 0x79 - EMA pointer */ - u16 emal; /* 0x7a - EMA Length */ - u8 rsvd8[0x5]; - /* MEF */ - u8 mefe; /* 0x82 - MEF enable */ - u8 rsvd9[0x9]; /* TPM support */ - u8 tpmp; /* 0x8c - TPM */ - u8 tpme; - u8 rsvd10[8]; - /* SATA */ - u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */ - u8 gtf1[7]; - u8 gtf2[7]; - u8 idem; - u8 idet; - u8 rsvd11[7]; + u8 tpmp; /* 0x5b - TPM Present */ + u8 tpme; /* 0x5c - TPM Enable */ + u8 rsvd5[3]; + /* LynxPoint Serial IO device BARs */ + u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ + u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ + u8 rsvd6[20]; /* IGD OpRegion (not implemented yet) */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ u8 ibtt; /* 0xb8 - IGD boot type */

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New patch to review for coreboot: 99bf4d8 wtm1/wtm2/baskingridge: Enable TPM ACPI device
by Stefan Reinauer 29 Mar '13

29 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2968 -gerrit commit 99bf4d89f851e2306600f45f9125b31e9bf9068f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 22 11:01:37 2013 -0700 wtm1/wtm2/baskingridge: Enable TPM ACPI device This enables the TPM device in ACPI tables so the OS is able to probe for the TPM without needing it be force loaded. Change-Id: I21e660ac1c12e3e1341cf266cf8f0bf03763df5a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/baskingridge/acpi_tables.c | 3 +++ src/mainboard/intel/baskingridge/dsdt.asl | 4 +++- src/mainboard/intel/wtm1/acpi_tables.c | 3 +++ src/mainboard/intel/wtm1/dsdt.asl | 2 ++ src/mainboard/intel/wtm2/acpi_tables.c | 3 +++ src/mainboard/intel/wtm2/dsdt.asl | 2 ++ 6 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index 5131ec1..d94251e 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -89,6 +89,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* CBMEM TOC */ gnvs->cmem = 0; + /* TPM Present */ + gnvs->tpmp = 1; + /* IGD Displays */ gnvs->ndid = 3; gnvs->did[0] = 0x80000100; diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 79bb8f3..a56562e 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#define ENABLE_TPM + DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/wtm1/acpi_tables.c b/src/mainboard/intel/wtm1/acpi_tables.c index 4232afc..6f5a1dd 100644 --- a/src/mainboard/intel/wtm1/acpi_tables.c +++ b/src/mainboard/intel/wtm1/acpi_tables.c @@ -86,6 +86,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* CBMEM TOC */ gnvs->cmem = 0; + /* TPM Present */ + gnvs->tpmp = 1; + /* IGD Displays */ gnvs->ndid = 3; gnvs->did[0] = 0x80000100; diff --git a/src/mainboard/intel/wtm1/dsdt.asl b/src/mainboard/intel/wtm1/dsdt.asl index 965f501..81e39c3 100644 --- a/src/mainboard/intel/wtm1/dsdt.asl +++ b/src/mainboard/intel/wtm1/dsdt.asl @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#define ENABLE_TPM + DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 4232afc..6f5a1dd 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -86,6 +86,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* CBMEM TOC */ gnvs->cmem = 0; + /* TPM Present */ + gnvs->tpmp = 1; + /* IGD Displays */ gnvs->ndid = 3; gnvs->did[0] = 0x80000100; diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index ed953c4..112a47a 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#define ENABLE_TPM + DefinitionBlock( "dsdt.aml", "DSDT",

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New patch to review for coreboot: 2c38317 armv7: remove loop from dcache_mmu_disable()
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2967 -gerrit commit 2c38317a9105ccc6b4183e2a839fefe1b7fb5ad2 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Mar 29 13:40:09 2013 -0700 armv7: remove loop from dcache_mmu_disable() dcache_mmu_disable() no longer needs to have its own iterative loop to select each cache level of cache since dcache_clean_invalidate_all() does that now. Change-Id: I5ca273f98943981b943c1c1622f4574d7133fb50 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/cache.c | 32 ++------------------------------ 1 file changed, 2 insertions(+), 30 deletions(-) diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index c7283f1..04eaa88 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -237,37 +237,9 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) void dcache_mmu_disable(void) { - uint32_t sctlr, clidr; - int level; - - clidr = read_clidr(); - for (level = 0; level < 7; level++) { - unsigned int ctype = (clidr >> (level * 3)) & 0x7; - uint32_t csselr; - - switch(ctype) { - case 0x0: - /* no cache */ - break; - case 0x2: - case 0x4: - /* dcache only or unified cache */ - csselr = level << 1; - write_csselr(csselr); - dcache_clean_invalidate_all(); - break; - case 0x3: - /* separate icache and dcache */ - csselr = level << 1; - write_csselr(csselr); - dcache_clean_invalidate_all(); - break; - default: - /* reserved */ - break; - } - } + uint32_t sctlr; + dcache_clean_invalidate_all(); sctlr = read_sctlr(); sctlr &= ~(SCTLR_C | SCTLR_M); write_sctlr(sctlr);

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Patch merged into coreboot/master: bae3f06 AMD CIMx SB800: Update Kconfig help texts to new SATA mode default
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit bae3f062457cf52da8e06e6abebfb99084411646 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Mar 28 13:03:38 2013 +0100 AMD CIMx SB800: Update Kconfig help texts to new SATA mode default In the following commit commit ee5c111755ac4acc6dfb6e10a4e271211e149a39 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Mar 12 12:41:40 2013 +0100 AMD CIMx SB800: Enable AHCI mode for SATA controller by default Reviewed-on: http://review.coreboot.org/2661 I forgot to update the help texts to the new SATA mode default. Do so now. Additionally note that help texts for `choice` do not seem to be shown. Change-Id: I17f401633a2136efca2b21a621482e0724ff9f04 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2936 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Mar 28 13:33:52 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Mar 29 21:33:37 2013, giving +2 See http://review.coreboot.org/2936 for details. -gerrit

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coreboot-gerrit March 2013