coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: bc07f5d x86: add rom cache variable MTRR index to tables
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit bc07f5d93552640793254ce003937ec646120a21 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 13:09:39 2013 -0500 x86: add rom cache variable MTRR index to tables Downstream payloads may need to take advantage of caching the ROM for performance reasons. Add the ability to communicate the variable range MTRR index to use to perform the caching enablement. An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the coreboot tables. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching. Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 14:48:13 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 20:09:36 2013, giving +2 See http://review.coreboot.org/2919 for details. -gerrit

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New patch to review for coreboot: a87ca9d ASRock E350M1: buildOpts.c: Add missing memory related defines
by Paul Menzel 29 Mar '13

29 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2962 -gerrit commit a87ca9d403de9322ee73aedc2ce431c7613dbd36 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 19:55:56 2013 +0100 ASRock E350M1: buildOpts.c: Add missing memory related defines When building the ASRock E350M1, the following warnings are shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/buildOpts.romstage.o In file included from src/mainboard/asrock/e350m1/buildOpts.c:294:0: src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2071:6: warning: "DDR1333_FREQUENCY" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2071:40: warning: "DDR1866_FREQUENCY" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2089:5: warning: "TIMING_MODE_AUTO" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2089:31: warning: "TIMING_MODE_SPECIFIC" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2113:5: warning: "QUADRANK_UNBUFFERED" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2113:33: warning: "QUADRANK_UNBUFFERED" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2127:5: warning: "POWER_DOWN_BY_CHIP_SELECT" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2127:28: warning: "POWER_DOWN_BY_CHIP_SELECT" is not defined [-Wundef] […] Adding the corresponding defines as done for AMD Persimmon in commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 addresses the warnings. Change-Id: Id311b2dacdba5f2e6b4d834e43db0310213a35f9 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/buildOpts.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 8b33e70..19ba4f3 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -279,6 +279,30 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE */ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + // The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation.

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Patch merged into coreboot/master: f567f16 sandybridge: add option to mark graphics memory write-combining.
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit f567f16af4c3cbfcadc3bc5c44b569a592829262 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:25:37 2013 -0500 sandybridge: add option to mark graphics memory write-combining. The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Add an option to enable write-combining for the graphics memory. Change-Id: I7d37fd78906262aabef92c2b4f4cab0e3f7e4f6d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 07:22:59 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 20:00:39 2013, giving +2 See http://review.coreboot.org/2894 for details. -gerrit

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Patch merged into coreboot/master: fcfe67c haswell: add option to mark graphics memory write-combining.
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit fcfe67c3b2b3391a8131eb26cc546a9afaa28822 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:23:05 2013 -0500 haswell: add option to mark graphics memory write-combining. The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Add an option to enable write-combining for the graphics memory. Change-Id: I797fcd9f0dfb074f9e45476773acbfe614eb4b0a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 08:21:28 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 20:00:25 2013, giving +2 See http://review.coreboot.org/2893 for details. -gerrit

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Patch merged into coreboot/master: 77a5b40 x86: mtrr: add CONFIG_CACHE_ROM support
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 77a5b4046ab7e7bee887990b342a7356554fd391 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 12:47:47 2013 -0500 x86: mtrr: add CONFIG_CACHE_ROM support The CONFIG_CACHE_ROM support in the MTRR code allocates an MTRR specifically for setting up write-protect cachine of the ROM. It is assumed that CONFIG_ROM_SIZE is the size of the ROM and the whole area should be cached just under 4GiB. If enabled, the MTRR code will allocate but not enable rom caching. It is up to the callers of the MTRR code to explicitly enable (and disable afterwards) through the use of 2 new functions: - x86_mtrr_enable_rom_caching() - x86_mtrr_disable_rom_caching() Additionally, the CACHE_ROM option is exposed to the config menu so that it is not just selected by the chipset or board. The reasoning is that through a multitude of options CACHE_ROM may not be appropriate for enabling. Change-Id: I4483df850f442bdcef969ffeaf7608ed70b88085 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 05:21:00 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 19:59:53 2013, giving +2 See http://review.coreboot.org/2918 for details. -gerrit

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Patch merged into coreboot/master: 9b027fe mtrr: honor IORESOURCE_WRCOMB
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 9b027fe5b028011593c98d2af8727199b74d3e4c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 14:10:34 2013 -0500 mtrr: honor IORESOURCE_WRCOMB All resources that set the IORESOURCE_WRCOMB attribute which are also marked as IORESOURCE_PREFETCH will have a MTRR set up that is of the write-combining cacheable type. The only resources on x86 that can be set to write-combining are prefetchable ones. Change-Id: Iba7452cff3677e07d7e263b79982a49c93be9c54 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2892 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 29 08:06:26 2013, giving +1 See http://review.coreboot.org/2892 for details. -gerrit

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Patch merged into coreboot/master: a05a852 lib: add memrange infrastructure
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit a05a8522ce1dd90c6d667b70bafb24757a27c656 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 20:44:46 2013 -0500 lib: add memrange infrastructure The memrange infrastructure allows for keeping track of the machine's physical address space. Each memory_range entry in a memory_ranges structure can be tagged with an arbitrary value. It supports merging and deleting ranges as well as filling in holes in the address space with a particular tag. The memrange infrastructure will serve as a shared implementation for address tracking by the MTRR and coreboot mem table code. Change-Id: Id5bea9d2a419114fca55c59af0fdca063551110e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2888 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 06:52:25 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 19:55:47 2013, giving +2 See http://review.coreboot.org/2888 for details. -gerrit

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Patch merged into coreboot/master: 3ece5ac stdlib: add ALIGN_UP and ALIGN_DOWN macros
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 3ece5ac40c66c78b4abce74eeec6521ad661c53c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 28 16:17:11 2013 -0500 stdlib: add ALIGN_UP and ALIGN_DOWN macros There wasn't an equivalent to align down so add ALIGN_DOWN. For symmetry provide an ALIGN_UP macro as well. Change-Id: I7033109311eeb15c8c69c649878785378790feb9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2951 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 08:37:45 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 19:54:47 2013, giving +2 See http://review.coreboot.org/2951 for details. -gerrit

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Patch merged into coreboot/master: 4fa5fa5 resources: introduce IORESOURCE_WRCOMB
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 4fa5fa5088503ff5c168b4fb8d548dd90034d29e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:16:58 2013 -0500 resources: introduce IORESOURCE_WRCOMB Certain MMIO resources can be set to a write-combining cacheable mode to increase performance. Typical resources that use this would be graphics memory. Change-Id: Icd96c720f86f7e2f19a6461bb23cb323124eb68e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2891 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 29 06:21:09 2013, giving +1 See http://review.coreboot.org/2891 for details. -gerrit

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Patch merged into coreboot/master: a755614 resources: remove IORESOURCE_[UMA_FB|IGNORE_MTRR]
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit a75561415e75d3a4dc813fc061140570e39b7078 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:09:46 2013 -0500 resources: remove IORESOURCE_[UMA_FB|IGNORE_MTRR] The IORESOURCE_UMA_FB and IORESOURCE_IGNORE_MTRR attributes on a resource provided hints to the MTRR algorithm. The IORESOURCE_UMA_FB directed the MTRR algorithm to setup a uncacheable space for the resource. The IORESOURCE_IGNORE_MTRR directed the MTRR algorithm to ignore this resource as it was used reserving RAM space. Now that the optimizing MTRR algorithm is in place there isn't a need for these flags. All IORESOURCE_IGNORE_MTRR users are handled by the MTRR code merging resources of the same cacheable type. The users of the IORESOURCE_UMA_FB will find that the default MTRR type calculation means there isn't a need for this flag any more. Change-Id: I4f62192edd9a700cb80fa7569caf49538f9b83b7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 05:51:11 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 19:54:00 2013, giving +2 See http://review.coreboot.org/2890 for details. -gerrit

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coreboot-gerrit March 2013