coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: c5293d3 ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite`
by Paul Menzel 29 Mar '13

29 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2957 -gerrit commit c5293d3b579f2b264513f622b375e1ac5a7b5d1d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 15:39:54 2013 +0100 ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/mainboard.ramstage.o src/mainboard/asrock/e350m1/mainboard.c: In function 'mainboard_enable': src/mainboard/asrock/e350m1/mainboard.c:63:2: warning: implicit declaration of function 'pm_iowrite' [-Wimplicit-function-declaration] […] The warning was introduced by moving the initialization of the ASF registers using `pm_iowrite` to `mainboard.c` in commit db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Thu Mar 21 22:21:28 2013 +0100 Asrock E350M1: Use SPD read code from F14 wrapper Reviewed-on: http://review.coreboot.org/2875 and is fixed by including `southbridge/amd/cimx/cimx_util.h` declaring `pm_iowrite`. Note, that the other AMD SB800 based boards seem to use the header file `southbridge/amd/sb800/sb800.h` so no warning is shown for those. Since the CIMx code is used, the routines from the CIMx are more appropriote to declare these functions. Change-Id: I179aad5157c5a91294339a3e7b6c4c1715c6f099 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/mainboard.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index be5c36c..cdac2be 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -25,6 +25,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> //#include <southbridge/amd/sb800/sb800.h> +#include <southbridge/amd/cimx/cimx_util.h> //#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void);

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New patch to review for coreboot: b5d63f2 ASRock E350M1: irq_tables.c: Include `cpu/amd/amdfam14.h` for `get_bus_conf`
by Paul Menzel 29 Mar '13

29 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2956 -gerrit commit b5d63f203afc15afdde6fc21c52979050fc7d653 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 14:36:33 2013 +0100 ASRock E350M1: irq_tables.c: Include `cpu/amd/amdfam14.h` for `get_bus_conf` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/irq_tables.ramstage.o src/mainboard/asrock/e350m1/irq_tables.c: In function 'write_pirq_routing_table': src/mainboard/asrock/e350m1/irq_tables.c:64:2: warning: implicit declaration of function 'get_bus_conf' [-Wimplicit-function-declaration] […] Including the header file `cpu/amd/amdfam14.h` declaring the function addresses this warning. This change is indentical to the following changeg done for the AMD Persimmon board. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 Change-Id: I40b5735feb7116961ca0c4d6940ec55cdf42d3c6 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/irq_tables.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index 6bb9911..5323d44 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -23,8 +23,7 @@ #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> -//#include <cpu/amd/amdfam10_sysconf.h> - +#include <cpu/amd/amdfam14.h> static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,

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Patch set updated for coreboot: a67b1c4 x86: mtrr: add hole punching support
by Aaron Durbin 29 Mar '13

29 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2925 -gerrit commit a67b1c49a7eaf7a524e3ff2a160e45a4881897b2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 28 20:48:51 2013 -0500 x86: mtrr: add hole punching support Some ranges would use less variable MTRRs if an UC area can be carved off the top of larger WB range. Implement this approach by doing 3 passes over each region in the addres space: 1. UC default type. Cover non-UC and non-WB regions with respectie type. Punch UC hole at upper end of larger WB regions with WB type. 2. UC default type. Cover non-UC regions with respective type. 3. WB default type. Cover non-WB regions with respective type. The hole at upper end of a region uses the same min alignment of 64MiB. Below are results using a combination of options. The board this was tested on has 10 variable MTRRs at its disposal. It has 4GiB of RAM. IO hole config #1: hole starts at 0xad800000 No CACHE_ROM or WRCOMB resources (takes 4 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x0000000100000000 size 0x52800000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 4/9. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 No CACHE_ROM. 1 WRCOMB resource (takes 6 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 6/10. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 CACHE_ROM and no WRCOMB resources (taks 10 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000ff800000 size 0x52000000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 11/10. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6 MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6 MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 5 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 6 base 0x0000000100000000 mask 0x0000007fc0000000 type 6 MTRR: 7 base 0x0000000140000000 mask 0x0000007ff0000000 type 6 Taking a reserved OS MTRR. MTRR: 8 base 0x000000014f600000 mask 0x0000007fffe00000 type 0 Taking a reserved OS MTRR. MTRR: 9 base 0x000000014f800000 mask 0x0000007fff800000 type 0 A combination of CACHE_ROM and WRCOMB just won't work. IO hole config #2: hole starts at 0x80000000: No CACHE_ROM or WRCOMB resources (takes 1 MTRR): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 1/5. MTRR: WB selected as default type. MTRR: 0 base 0x0000000080000000 mask 0x0000007f80000000 type 0 No CACHE_ROM. 1 WRCOMB resource (takes 4 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 4/6. MTRR: WB selected as default type. MTRR: 0 base 0x0000000080000000 mask 0x0000007fc0000000 type 0 MTRR: 1 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 2 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 3 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 CACHE_ROM and no WRCOMB resources (takes 6 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000ff800000 size 0x7f800000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 9/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 2 base 0x0000000100000000 mask 0x0000007f80000000 type 6 MTRR: 3 base 0x000000017ce00000 mask 0x0000007fffe00000 type 0 MTRR: 4 base 0x000000017d000000 mask 0x0000007fff000000 type 0 MTRR: 5 base 0x000000017e000000 mask 0x0000007ffe000000 type 0 CACHE_ROM and 1 WRCOMB resource (takes 7 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 10/7. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 2 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 3 base 0x0000000100000000 mask 0x0000007f80000000 type 6 MTRR: 4 base 0x000000017ce00000 mask 0x0000007fffe00000 type 0 MTRR: 5 base 0x000000017d000000 mask 0x0000007fff000000 type 0 MTRR: 6 base 0x000000017e000000 mask 0x0000007ffe000000 type 0 Change-Id: Iceb9b64991accf558caae2e7b0205951e9bcde44 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 236 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 188 insertions(+), 48 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 9c8f8c7..005ea81 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -122,6 +122,21 @@ static inline unsigned int fls(unsigned int x) #define RANGE_1MB PHYS_TO_RANGE_ADDR(1 << 20) #define RANGE_4GB (1 << (ADDR_SHIFT_TO_RANGE_SHIFT(32))) +/* + * The default MTRR type selection uses 3 approaches for selecting the + * optimal number of variable MTRRs. For each range do 3 calculations: + * 1. UC as default type with no holes at top of range. + * 2. UC as default using holes at top of range. + * 3. WB as default. + * If using holes is optimal for a range when UC is the default type the + * tag is updated to direct the commit routine to use a hole at the top + * of a range. + */ +#define MTRR_ALGO_SHIFT (8) +#define MTRR_TAG_MASK ((1 << MTRR_ALGO_SHIFT) - 1) +/* If the default type is UC use the hole carving algorithm for a range. */ +#define MTRR_RANGE_UC_USE_HOLE (1 << MTRR_ALGO_SHIFT) + static inline uint32_t range_entry_base_mtrr_addr(struct range_entry *r) { return PHYS_TO_RANGE_ADDR(range_entry_base(r)); @@ -132,6 +147,11 @@ static inline uint32_t range_entry_end_mtrr_addr(struct range_entry *r) return PHYS_TO_RANGE_ADDR(range_entry_end(r)); } +static inline int range_entry_mtrr_type(struct range_entry *r) +{ + return range_entry_tag(r) & MTRR_TAG_MASK; +} + static struct memranges *get_physical_address_space(void) { static struct memranges *addr_space; @@ -491,9 +511,72 @@ static void calc_var_mtrr_range(struct var_mtrr_state *var_state, } } -static void setup_var_mtrrs_by_state(struct var_mtrr_state *var_state) +static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, + struct range_entry *r) { - struct range_entry *r; + uint32_t a1, a2, b1, b2; + int mtrr_type; + struct range_entry *next; + + /* + * Determine MTRRs based on the following algoirthm for the given entry: + * +------------------+ b2 = ALIGN_UP(end) + * | 0 or more bytes | <-- hole is carved out between b1 and b2 + * +------------------+ a2 = b1 = end + * | | + * +------------------+ a1 = begin + * + * Thus, there are 3 sub-ranges to configure variable MTRRs for. + */ + mtrr_type = range_entry_mtrr_type(r); + + a1 = range_entry_base_mtrr_addr(r); + a2 = range_entry_end_mtrr_addr(r); + + /* The end address is under 1MiB. The fixed MTRRs take + * precedence over the variable ones. Therefore this range + * can be ignored. */ + if (a2 < RANGE_1MB) + return; + + /* Again, the fixed MTRRs take precedence so the beginning + * of the range can be set to 0 if it starts below 1MiB. */ + if (a1 < RANGE_1MB) + a1 = 0; + + /* If the range starts above 4GiB the processing is done. */ + if (!var_state->above4gb && a1 >= RANGE_4GB) + return; + + /* Clip the upper address to 4GiB if addresses above 4GiB + * are not being processed. */ + if (!var_state->above4gb && a2 > RANGE_4GB) + a2 = RANGE_4GB; + + b1 = a2; + b2 = ALIGN_UP(a2, MTRR_MIN_ALIGN); + + /* Check against the next range. If the current range_entry is the + * last entry then carving a hole is no problem. If the current entry + * isn't the last entry then check that the last entry covers the + * entire hole range with the default mtrr type. */ + next = memranges_next_entry(var_state->addr_space, r); + if (next != NULL && + (range_entry_mtrr_type(next) != var_state->def_mtrr_type || + range_entry_end_mtrr_addr(next) < b2)) { + calc_var_mtrr_range(var_state, a1, a2 - a1, mtrr_type); + return; + } + + calc_var_mtrr_range(var_state, a1, b2 - a1, mtrr_type); + calc_var_mtrr_range(var_state, b1, b2 - b1, var_state->def_mtrr_type); +} + +static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, + struct range_entry *r) +{ + uint32_t a1, a2, b1, b2, c1, c2; + int mtrr_type; /* * For each range that meets the non-default type process it in the @@ -508,51 +591,44 @@ static void setup_var_mtrrs_by_state(struct var_mtrr_state *var_state) * * Thus, there are 3 sub-ranges to configure variable MTRRs for. */ - memranges_each_entry(r, var_state->addr_space) { - uint32_t a1, a2, b1, b2, c1, c2; - int mtrr_type = range_entry_tag(r); + mtrr_type = range_entry_mtrr_type(r); - /* Skip default type. */ - if (var_state->def_mtrr_type == mtrr_type) - continue; - - a1 = range_entry_base_mtrr_addr(r); - c2 = range_entry_end_mtrr_addr(r); + a1 = range_entry_base_mtrr_addr(r); + c2 = range_entry_end_mtrr_addr(r); - /* The end address is under 1MiB. The fixed MTRRs take - * precedence over the variable ones. Therefore this range - * can be ignored. */ - if (c2 < RANGE_1MB) - continue; + /* The end address is under 1MiB. The fixed MTRRs take + * precedence over the variable ones. Therefore this range + * can be ignored. */ + if (c2 < RANGE_1MB) + return; - /* Again, the fixed MTRRs take precedence so the beginning - * of the range can be set to 0 if it starts below 1MiB. */ - if (a1 < RANGE_1MB) - a1 = 0; + /* Again, the fixed MTRRs take precedence so the beginning + * of the range can be set to 0 if it starts below 1MiB. */ + if (a1 < RANGE_1MB) + a1 = 0; - /* If the range starts above 4GiB the processing is done. */ - if (!var_state->above4gb && a1 >= RANGE_4GB) - break; + /* If the range starts above 4GiB the processing is done. */ + if (!var_state->above4gb && a1 >= RANGE_4GB) + return; - /* Clip the upper address to 4GiB if addresses above 4GiB - * are not being processed. */ - if (!var_state->above4gb && c2 > RANGE_4GB) - c2 = RANGE_4GB; + /* Clip the upper address to 4GiB if addresses above 4GiB + * are not being processed. */ + if (!var_state->above4gb && c2 > RANGE_4GB) + c2 = RANGE_4GB; - /* Don't align up or down on the range if it is smaller - * than the minimum granularity. */ - if ((c2 - a1) < MTRR_MIN_ALIGN) { - calc_var_mtrr_range(var_state, a1, c2 - a1, mtrr_type); - continue; - } + /* Don't align up or down on the range if it is smaller + * than the minimum granularity. */ + if ((c2 - a1) < MTRR_MIN_ALIGN) { + calc_var_mtrr_range(var_state, a1, c2 - a1, mtrr_type); + return; + } - b1 = a2 = ALIGN_UP(a1, MTRR_MIN_ALIGN); - b2 = c1 = ALIGN_DOWN(c2, MTRR_MIN_ALIGN); + b1 = a2 = ALIGN_UP(a1, MTRR_MIN_ALIGN); + b2 = c1 = ALIGN_DOWN(c2, MTRR_MIN_ALIGN); - calc_var_mtrr_range(var_state, a1, a2 - a1, mtrr_type); - calc_var_mtrr_range(var_state, b1, b2 - b1, mtrr_type); - calc_var_mtrr_range(var_state, c1, c2 - c1, mtrr_type); - } + calc_var_mtrr_range(var_state, a1, a2 - a1, mtrr_type); + calc_var_mtrr_range(var_state, b1, b2 - b1, mtrr_type); + calc_var_mtrr_range(var_state, c1, c2 - c1, mtrr_type); } static int calc_var_mtrrs(struct memranges *addr_space, @@ -560,6 +636,7 @@ static int calc_var_mtrrs(struct memranges *addr_space, { int wb_deftype_count; int uc_deftype_count; + struct range_entry *r; struct var_mtrr_state var_state; /* The default MTRR cacheability type is determined by calculating @@ -570,15 +647,67 @@ static int calc_var_mtrrs(struct memranges *addr_space, var_state.address_bits = address_bits; var_state.commit_mtrrs = 0; - var_state.mtrr_index = 0; - var_state.def_mtrr_type = MTRR_TYPE_WRBACK; - setup_var_mtrrs_by_state(&var_state); - wb_deftype_count = var_state.mtrr_index; + wb_deftype_count = 0; + uc_deftype_count = 0; - var_state.mtrr_index = 0; - var_state.def_mtrr_type = MTRR_TYPE_UNCACHEABLE; - setup_var_mtrrs_by_state(&var_state); - uc_deftype_count = var_state.mtrr_index; + /* + * For each range do 3 calculations: + * 1. UC as default type with no holes at top of range. + * 2. UC as default using holes at top of range. + * 3. WB as default. + * The lowest count is then used as default after totalling all + * MTRRs. Note that the optimal algoirthm for UC default is marked in + * the tag of each range regardless of final decision. UC takes + * precedence in the MTRR archiecture. Therefore, only holes can be + * used when the type of the region is MTRR_TYPE_WRBACK with + * MTRR_TYPE_UNCACHEABLE as the default type. + */ + memranges_each_entry(r, var_state.addr_space) { + int mtrr_type; + + mtrr_type = range_entry_mtrr_type(r); + + if (mtrr_type != MTRR_TYPE_UNCACHEABLE) { + int uc_hole_count; + int uc_no_hole_count; + + var_state.def_mtrr_type = MTRR_TYPE_UNCACHEABLE; + var_state.mtrr_index = 0; + + /* No hole calculation. */ + calc_var_mtrrs_without_hole(&var_state, r); + uc_no_hole_count = var_state.mtrr_index; + + /* Hole calculation only if type is WB. The 64 number + * is a count that is unachievable, thus making it + * a default large number in the case of not doing + * the hole calculation. */ + uc_hole_count = 64; + if (mtrr_type == MTRR_TYPE_WRBACK) { + var_state.mtrr_index = 0; + calc_var_mtrrs_with_hole(&var_state, r); + uc_hole_count = var_state.mtrr_index; + } + + /* Mark the entry with the optimal algorithm. */ + if (uc_no_hole_count < uc_hole_count) { + uc_deftype_count += uc_no_hole_count; + } else { + unsigned long new_tag; + + new_tag = mtrr_type | MTRR_RANGE_UC_USE_HOLE; + range_entry_update_tag(r, new_tag); + uc_deftype_count += uc_hole_count; + } + } + + if (mtrr_type != MTRR_TYPE_WRBACK) { + var_state.mtrr_index = 0; + var_state.def_mtrr_type = MTRR_TYPE_WRBACK; + calc_var_mtrrs_without_hole(&var_state, r); + wb_deftype_count += var_state.mtrr_index; + } + } printk(BIOS_DEBUG, "MTRR: default type WB/UC MTRR counts: %d/%d.\n", wb_deftype_count, uc_deftype_count); @@ -594,6 +723,7 @@ static int calc_var_mtrrs(struct memranges *addr_space, static void commit_var_mtrrs(struct memranges *addr_space, int def_type, int above4gb, int address_bits) { + struct range_entry *r; struct var_mtrr_state var_state; int i; @@ -604,7 +734,17 @@ static void commit_var_mtrrs(struct memranges *addr_space, int def_type, var_state.commit_mtrrs = 1; var_state.mtrr_index = 0; var_state.def_mtrr_type = def_type; - setup_var_mtrrs_by_state(&var_state); + + memranges_each_entry(r, var_state.addr_space) { + if (range_entry_mtrr_type(r) == def_type) + continue; + + if (def_type == MTRR_TYPE_UNCACHEABLE && + (range_entry_tag(r) & MTRR_RANGE_UC_USE_HOLE)) + calc_var_mtrrs_with_hole(&var_state, r); + else + calc_var_mtrrs_without_hole(&var_state, r); + } /* Clear all remaining variable MTTRs. */ for (i = var_state.mtrr_index; i < total_mtrrs; i++)

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Patch set updated for coreboot: 2b0853a memrange: add 2 new range_entry routines
by Aaron Durbin 29 Mar '13

29 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2924 -gerrit commit 2b0853afddd2a2f5166012c05cff05fbacb0cbb4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 21:22:42 2013 -0500 memrange: add 2 new range_entry routines Two convenience functions are added to operate on a range_entry: - range_entry_update_tag() - update the entry's tag - memranges_next_entry() - get the next entry after the one provide These functions will be used by a follow on patch to the MTRR code to allow hole punching in WB region when the default MTRR type is UC. Change-Id: I3c2be19c8ea1bbbdf7736c867e4a2aa82df2d611 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/memrange.h | 9 +++++++++ src/lib/memrange.c | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/src/include/memrange.h b/src/include/memrange.h index 23dae6a..0e69b2f 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -61,6 +61,12 @@ static inline unsigned long range_entry_tag(const struct range_entry *r) return r->tag; } +static inline void range_entry_update_tag(struct range_entry *r, + unsigned long new_tag) +{ + r->tag = new_tag; +} + /* Iterate over each entry in a memranges structure. Ranges cannot * be deleted while processing each entry as the list cannot be safely * traversed after such an operation. @@ -104,4 +110,7 @@ void memranges_create_hole(struct memranges *ranges, void memranges_insert(struct memranges *ranges, resource_t base, resource_t size, unsigned long tag); +/* Returns next entry after the provided entry. NULL if r is last. */ +struct range_entry *memranges_next_entry(struct memranges *ranges, + const struct range_entry *r); #endif /* MEMRANGE_H_ */ diff --git a/src/lib/memrange.c b/src/lib/memrange.c index c376d52..1a16ef7 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -321,3 +321,9 @@ void memranges_fill_holes_up_to(struct memranges *ranges, /* Merge all entries that were newly added. */ merge_neighbor_entries(ranges); } + +struct range_entry *memranges_next_entry(struct memranges *ranges, + const struct range_entry *r) +{ + return r->next; +}

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Patch set updated for coreboot: e71ab66 chromeos: remove CACHE_ROM automatic selection
by Aaron Durbin 29 Mar '13

29 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2921 -gerrit commit e71ab66afa7aa4bdee4999b104d5adb98ae04342 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 14:52:04 2013 -0500 chromeos: remove CACHE_ROM automatic selection It's not appropriate for the chromeos Kconfig to automatically select CACHE_ROM. The reason is that enabling CACHE_ROM is dependent on the board and chipset atrributes. Change-Id: I47429f1cceefd40226c4b943215d627a3c869c7b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index e99e2c8..d5ca212 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -20,7 +20,6 @@ config CHROMEOS bool default n select TPM - select CACHE_ROM help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported

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Patch set updated for coreboot: e781944 libpayload: add x86 ROM variable MTRR support
by Aaron Durbin 29 Mar '13

29 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2920 -gerrit commit e7819449d30b4bd790a80c4963f26f2ece8daf81 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 13:34:37 2013 -0500 libpayload: add x86 ROM variable MTRR support On x86, coreboot may allocate a variable range MTRR for enabling caching of the system ROM. Add the ability to parse this structure and add the result to the sysinfo structure. An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the sysinfo structure. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching. Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/x86/coreboot.c | 17 ++++++++++++++++- payloads/libpayload/include/coreboot_tables.h | 12 ++++++++++++ payloads/libpayload/include/sysinfo.h | 5 +++++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index f4f9b86..6c6122d 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -158,6 +158,12 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) } #endif +static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) +{ + struct cb_x86_rom_mtrr *rom_mtrr = ptr; + info->x86_rom_var_mtrr_index = rom_mtrr->index; +} + static void cb_parse_string(unsigned char *ptr, char **info) { *info = (char *)((struct cb_string *)ptr)->string; @@ -281,6 +287,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_MRC_CACHE: cb_parse_mrc_cache(ptr, info); break; + case CB_TAG_X86_ROM_MTRR: + cb_parse_x86_rom_var_mtrr(ptr, info); + break; } ptr += rec->size; @@ -294,7 +303,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); + int ret; + + /* Ensure the variable range MTRR index covering the ROM is set to + * an invalid value. */ + info->x86_rom_var_mtrr_index = -1; + + ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); if (ret != 1) ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 38bda55..02c9449 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -217,6 +217,18 @@ struct cb_vboot_handoff { uint32_t vboot_handoff_size; }; +#define CB_TAG_X86_ROM_MTRR 0x0021 +struct cb_x86_rom_mtrr { + uint32_t tag; + uint32_t size; + /* The variable range MTRR index covering the ROM. If one wants to + * enable caching the ROM, the variable MTRR needs to be set to + * write-protect. To disable the caching after enabling set the + * type to uncacheable. */ + uint32_t index; +}; + + #define CB_TAG_CMOS_OPTION_TABLE 0x00c8 struct cb_cmos_option_table { u32 tag; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index e05ef9f..fd60dc3 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -99,6 +99,11 @@ struct sysinfo_t { void *vdat_addr; u32 vdat_size; #endif + +#ifdef CONFIG_ARCH_X86 + int x86_rom_var_mtrr_index; +#endif + void *tstamp_table; void *cbmem_cons; void *mrc_cache;

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Patch set updated for coreboot: 77fa0ca x86: add rom cache variable MTRR index to tables
by Aaron Durbin 29 Mar '13

29 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2919 -gerrit commit 77fa0ca9bad1029545290b9ce45c39b0159de086 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 13:09:39 2013 -0500 x86: add rom cache variable MTRR index to tables Downstream payloads may need to take advantage of caching the ROM for performance reasons. Add the ability to communicate the variable range MTRR index to use to perform the caching enablement. An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the coreboot tables. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching. Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 5 +++++ src/include/boot/coreboot_tables.h | 8 ++++++++ src/include/cpu/x86/mtrr.h | 3 +++ src/lib/coreboot_table.c | 23 +++++++++++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dad1029..9c8f8c7 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -349,6 +349,11 @@ void x86_setup_fixed_mtrrs(void) #if CONFIG_CACHE_ROM static long rom_cache_mtrr = -1; +long x86_mtrr_rom_cache_var_index(void) +{ + return rom_cache_mtrr; +} + void x86_mtrr_enable_rom_caching(void) { msr_t msr_val; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index f624ac1..a7e4ab0 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -250,6 +250,14 @@ struct lb_vboot_handoff { uint32_t vboot_handoff_size; }; +#define LB_TAG_X86_ROM_MTRR 0x0021 +struct lb_x86_rom_mtrr { + uint32_t tag; + uint32_t size; + /* The variable range MTRR index covering the ROM. */ + uint32_t index; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index bff736d..15a5cad 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -78,9 +78,12 @@ int x86_mtrr_check(void); #if CONFIG_CACHE_ROM void x86_mtrr_enable_rom_caching(void); void x86_mtrr_disable_rom_caching(void); +/* Return the variable range MTRR index of the ROM cache. */ +long x86_mtrr_rom_cache_var_index(void); #else static inline void x86_mtrr_enable_rom_caching(void) {} static inline void x86_mtrr_disable_rom_caching(void) {} +static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } #endif /* CONFIG_CACHE_ROM */ #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index b9a82a8..765c510 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -40,6 +40,9 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif +#if CONFIG_ARCH_X86 +#include <cpu/x86/mtrr.h> +#endif static struct lb_header *lb_table_init(unsigned long addr) { @@ -237,6 +240,24 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ +static void lb_x86_rom_cache(struct lb_header *header) +{ +#if CONFIG_ARCH_X86 + long mtrr_index; + struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; + + mtrr_index = x86_mtrr_rom_cache_var_index(); + + if (mtrr_index < 0) + return; + + lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); + lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; + lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); + lb_x86_rom_mtrr->index = mtrr_index; +#endif +} + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -539,6 +560,8 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); + /* Communicate x86 variable MTRR ROM cache information. */ + lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */

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Patch set updated for coreboot: 2480cb6 ASRock E350M1: PlatformGnbPcie.c: Do not return anything for void return type
by Paul Menzel 29 Mar '13

29 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2954 -gerrit commit 2480cb62571d7a4b47598a5d20ff79ea48832ded Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 12:51:31 2013 +0100 ASRock E350M1: PlatformGnbPcie.c: Do not return anything for void return type When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/PlatformGnbPcie.romstage.o CC mainboard/asrock/e350m1/agesawrapper.romstage.o CC mainboard/asrock/e350m1/buildOpts.romstage.o src/mainboard/asrock/e350m1/PlatformGnbPcie.c: In function 'OemCustomizeInitEarly': src/mainboard/asrock/e350m1/PlatformGnbPcie.c:131:5: warning: 'return' with a value, in function returning void [enabled by default] […] The function signature is (the return type might not be part of this though [1]), VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) so do not return anything. All other AMD Family 14 boards already have the correct code. For example following commit fixed this for AMD Persimmon. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 [1] http://cboard.cprogramming.com/cplusplus-programming/117286-what-exactly-fu… Change-Id: Ie60246bd9bb8452efd096e6838d8610f6364a6aa Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index a580567..cef3e37 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -128,7 +128,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { if ( Status!= AGESA_SUCCESS) { // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR ASSERT(FALSE); - return Status; + return; } BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;

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New patch to review for coreboot: a11a804 ASRock E350M1: get_bus_conf.c: Include `agesawrapper.h` for `agesawrapper_amdinitlate`
by Paul Menzel 29 Mar '13

29 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2955 -gerrit commit a11a80444dc6b4da6e230fe05b8b43c9d319f427 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 13:23:31 2013 +0100 ASRock E350M1: get_bus_conf.c: Include `agesawrapper.h` for `agesawrapper_amdinitlate` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/get_bus_conf.ramstage.o src/mainboard/asrock/e350m1/get_bus_conf.c: In function 'get_bus_conf': src/mainboard/asrock/e350m1/get_bus_conf.c:82:3: warning: implicit declaration of function 'agesawrapper_amdinitlate' [-Wimplicit-function-declaration] […] Including the header file `agesawrapper.h` declaring the function `agesawrapper_amdinitlate` fixes this warning. All AMD Family 14 based boards already include that header file. For example for the board AMD Persimmon the following patch fixed this warning. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 Change-Id: I695420b7071e07cb7d4667b2479b9a26ea13723d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/get_bus_conf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index c2034f8..1419d79 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -24,6 +24,7 @@ #include <stdint.h> #include <stdlib.h> #include <cpu/amd/amdfam14.h> +#include "agesawrapper.h" #if CONFIG_AMD_SB_CIMX #include "sb_cimx.h" #endif

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New patch to review for coreboot: 639bb99 ASRock E350M1: PlatformGnbPcie.c: Do not return anything for void return type
by Paul Menzel 29 Mar '13

29 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2954 -gerrit commit 639bb991bbac2a470f33ddb2b6fd8b8b8a40dda3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 12:51:31 2013 +0100 ASRock E350M1: PlatformGnbPcie.c: Do not return anything for void return type Building the ASRock E350M1, the following warning is shown. $ make […] CC mainboard/asrock/e350m1/PlatformGnbPcie.romstage.o CC mainboard/asrock/e350m1/agesawrapper.romstage.o CC mainboard/asrock/e350m1/buildOpts.romstage.o src/mainboard/asrock/e350m1/PlatformGnbPcie.c: In function 'OemCustomizeInitEarly': src/mainboard/asrock/e350m1/PlatformGnbPcie.c:131:5: warning: 'return' with a value, in function returning void [enabled by default] […] The function signature is (the return type might not be part of this though [1]), VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) so do not return anything. All other AMD Family 14 boards already have the correct code. For example following commit fixed this for AMD Persimmon. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 [1] http://cboard.cprogramming.com/cplusplus-programming/117286-what-exactly-fu… Change-Id: Ie60246bd9bb8452efd096e6838d8610f6364a6aa Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index a580567..cef3e37 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -128,7 +128,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { if ( Status!= AGESA_SUCCESS) { // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR ASSERT(FALSE); - return Status; + return; } BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;

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coreboot-gerrit March 2013