coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: bb4e79a x86: add new mtrr implementation
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit bb4e79a332f0a4f79d402c91b61010157d8a7886 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 14:09:47 2013 -0500 x86: add new mtrr implementation The old MTRR code had issues using too many variable MTRRs depending on the physical address space layout dictated by the device resources. This new implementation calculates the default MTRR type by comparing the number of variable MTRRs used for each type. This avoids the need for IORESOURE_UMA_FB because in many of those situations setting the default type to WB frees up the variable MTTRs to set that space to UC. Additionally, it removes the need for IORESOURCE_IGNORE_MTRR becuase the new mtrr uses the memrange library which does merging of resources. Lastly, the sandybridge gma has its speedup optimization removed for the graphics memory by writing a pre-determined MTRR index. That will be fixed in an upcoming patch once write-combining support is added to the resources. Slight differences from previous MTRR code: - The number of reserved OS MTRRs is not a hard limit. It's now advisory as PAT can be used by the OS to setup the regions to the caching policy desired. - The memory types are calculated once by the first CPU to run the code. After that all other CPUs use that value. - CONFIG_CACHE_ROM support was dropped. It will be added back in its own change. A pathological case that was previously fixed by changing vendor code to adjust the IO hole location looked like the following: MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 As noted by the output below it's impossible to accomodate those ranges even with 10 variable MTRRS. However, because the code can select WB as the default MTRR type it can be done in 6 MTRRs: MTRR: default type WB/UC MTRR counts: 6/14. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 Change-Id: Idfcc78d9afef9d44c769a676716aae3ff2bd79de Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2889 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 07:06:46 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 29 19:53:43 2013, giving +2 See http://review.coreboot.org/2889 for details. -gerrit

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Patch set updated for coreboot: 0fc6891 AMD Hudson boards: Use `hudson.h` for `pm_ioread` and delete `pmio.h`
by Paul Menzel 29 Mar '13

29 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2958 -gerrit commit 0fc68918d36856aa890dac05798694ea466c3158 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 15:59:13 2013 +0100 AMD Hudson boards: Use `hudson.h` for `pm_ioread` and delete `pmio.h` Unfortunately, an unneeded mainboard specific `pmio.h` was created when merging the AMD Parmer and Thatcher ports. Rudolf used the header from a more generic location southbridge/amd/agesa/hudson/hudson.h doing the the ASUS F2A85-M port, but did not delete the `pmio.h` now unused `pmio.h` header file. So adapt AMD Parmer and Thatcher to use the Hudson one as done for the ASUS F2A85-M and delete the now unused mainboard specific header file `pmio.h` to avoid duplication. Change-Id: I961cd145ebc3b83e31c638ac453ac95ee19c18db Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/parmer/mptable.c | 2 +- src/mainboard/amd/parmer/pmio.h | 33 --------------------------------- src/mainboard/amd/thatcher/mptable.c | 2 +- src/mainboard/amd/thatcher/pmio.h | 33 --------------------------------- src/mainboard/asus/f2a85-m/mptable.c | 2 +- src/mainboard/asus/f2a85-m/pmio.h | 33 --------------------------------- 6 files changed, 3 insertions(+), 102 deletions(-) diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 268f6d8..67f73c4 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -24,9 +24,9 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/amdfam15.h> -#include "pmio.h" #include <arch/cpu.h> #include <cpu/x86/lapic.h> +#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS diff --git a/src/mainboard/amd/parmer/pmio.h b/src/mainboard/amd/parmer/pmio.h deleted file mode 100644 index 35751f5..0000000 --- a/src/mainboard/amd/parmer/pmio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PMIO_H_ -#define _PMIO_H_ - -#define PM_INDEX 0xCD6 -#define PM_DATA 0xCD7 -#define PM2_INDEX 0xCD0 -#define PM2_DATA 0xCD1 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index ffa7992..8253b2c 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -24,9 +24,9 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/amdfam15.h> -#include "pmio.h" #include <arch/cpu.h> #include <cpu/x86/lapic.h> +#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS diff --git a/src/mainboard/amd/thatcher/pmio.h b/src/mainboard/amd/thatcher/pmio.h deleted file mode 100644 index 35751f5..0000000 --- a/src/mainboard/amd/thatcher/pmio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PMIO_H_ -#define _PMIO_H_ - -#define PM_INDEX 0xCD6 -#define PM_DATA 0xCD7 -#define PM2_INDEX 0xCD0 -#define PM2_DATA 0xCD1 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 5b6136c..6ed9fca 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -26,7 +26,7 @@ #include <cpu/amd/amdfam15.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "southbridge/amd/agesa/hudson/hudson.h" +#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 diff --git a/src/mainboard/asus/f2a85-m/pmio.h b/src/mainboard/asus/f2a85-m/pmio.h deleted file mode 100644 index 35751f5..0000000 --- a/src/mainboard/asus/f2a85-m/pmio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PMIO_H_ -#define _PMIO_H_ - -#define PM_INDEX 0xCD6 -#define PM_DATA 0xCD7 -#define PM2_INDEX 0xCD0 -#define PM2_DATA 0xCD1 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif

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New patch to review for coreboot: 90d16f7 inteltool: Support GPIO registers on Cougar/Panther Point
by Nico Huber 29 Mar '13

29 Mar '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2961 -gerrit commit 90d16f76e17259f09c49f92cdc1848162ae4ac68 Author: Nico Huber <nico.h(a)gmx.de> Date: Fri Mar 29 18:08:13 2013 +0100 inteltool: Support GPIO registers on Cougar/Panther Point This adds the GPIO register definitions for Intel's Cougar Point and Panther Point platform controller hubs (PCH). All information is taken from the public specifications in [1] and [2]. I've tested it with an H77 PCH. NM70 is missing in [1]. Therefore, I didn't add it here. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 Change-Id: I31711e24f852e68b3c113e3bd9243dc7e89ac197 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/inteltool/gpio.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 1d48a68..8b85593 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -221,6 +221,42 @@ static const io_register_t i631x_gpio_registers[] = { { 0x38, 4, "GP_LVL2" }, }; +static const io_register_t pch_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "GP_SER_BLINK" }, + { 0x20, 4, "GP_SB_CMDSTS" }, + { 0x24, 4, "GP_SB_DATA" }, + { 0x28, 2, "GPI_NMI_EN" }, + { 0x2a, 2, "GPI_NMI_STS" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x3c, 4, "RESERVED" }, + { 0x40, 4, "GPIO_USE_SEL3" }, + { 0x44, 4, "GPIO_SEL3" }, + { 0x48, 4, "GPIO_LVL3" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 4, "RESERVED" }, + { 0x54, 4, "RESERVED" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + { 0x60, 4, "GP_RST_SEL1" }, + { 0x64, 4, "GP_RST_SEL2" }, + { 0x68, 4, "GP_RST_SEL3" }, + { 0x6c, 4, "RESERVED" }, + { 0x70, 4, "RESERVED" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + int print_gpios(struct pci_dev *sb) { int i, size; @@ -230,6 +266,39 @@ int print_gpios(struct pci_dev *sb) printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_Z68: + case PCI_DEVICE_ID_INTEL_P67: + case PCI_DEVICE_ID_INTEL_UM67: + case PCI_DEVICE_ID_INTEL_HM65: + case PCI_DEVICE_ID_INTEL_H67: + case PCI_DEVICE_ID_INTEL_HM67: + case PCI_DEVICE_ID_INTEL_Q65: + case PCI_DEVICE_ID_INTEL_QS67: + case PCI_DEVICE_ID_INTEL_Q67: + case PCI_DEVICE_ID_INTEL_QM67: + case PCI_DEVICE_ID_INTEL_B65: + case PCI_DEVICE_ID_INTEL_C202: + case PCI_DEVICE_ID_INTEL_C204: + case PCI_DEVICE_ID_INTEL_C206: + case PCI_DEVICE_ID_INTEL_H61: + case PCI_DEVICE_ID_INTEL_Z77: + case PCI_DEVICE_ID_INTEL_Z75: + case PCI_DEVICE_ID_INTEL_Q77: + case PCI_DEVICE_ID_INTEL_Q75: + case PCI_DEVICE_ID_INTEL_B75: + case PCI_DEVICE_ID_INTEL_H77: + case PCI_DEVICE_ID_INTEL_C216: + case PCI_DEVICE_ID_INTEL_QM77: + case PCI_DEVICE_ID_INTEL_QS77: + case PCI_DEVICE_ID_INTEL_HM77: + case PCI_DEVICE_ID_INTEL_UM77: + case PCI_DEVICE_ID_INTEL_HM76: + case PCI_DEVICE_ID_INTEL_HM75: + case PCI_DEVICE_ID_INTEL_HM70: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_ICH10R: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich10_gpio_registers;

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New patch to review for coreboot: c630fbc inteltool: Add definitions for Cougar/Panther Point PCI IDs
by Nico Huber 29 Mar '13

29 Mar '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2960 -gerrit commit c630fbcf328fe091b4c2e83ccd08ed9f6ea6b2d2 Author: Nico Huber <nico.h(a)gmx.de> Date: Fri Mar 29 17:57:15 2013 +0100 inteltool: Add definitions for Cougar/Panther Point PCI IDs This adds correspondings #defines for the PCI IDs of the LPC device on Intel's Cougar Point and Panther Point platform controller hubs. Those will be used more in later commits. I've checked all those IDs against the specification updates [1] and [2]. [1] Intel 6 Series Chipset and Intel C200 Series Chipset Specification Update Document-Number: 324646-019 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) Family - Datasheet Specification Update Document-Number: 326777-010 Change-Id: Ibef5a30d283c568c345eb8d8149723e7a3049272 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/inteltool/inteltool.c | 60 +++++++++++++++++++++++----------------------- util/inteltool/inteltool.h | 30 +++++++++++++++++++++++ 2 files changed, 60 insertions(+), 30 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index be2b721..d56d058 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -119,38 +119,38 @@ static const struct { { PCI_VENDOR_ID_INTEL, 0x3b14, "3420" }, { PCI_VENDOR_ID_INTEL, 0x3b16, "3450" }, { PCI_VENDOR_ID_INTEL, 0x3b1e, "B55" }, - { PCI_VENDOR_ID_INTEL, 0x1c44, "Z68" }, - { PCI_VENDOR_ID_INTEL, 0x1c46, "P67" }, - { PCI_VENDOR_ID_INTEL, 0x1c47, "UM67" }, - { PCI_VENDOR_ID_INTEL, 0x1c49, "HM65" }, - { PCI_VENDOR_ID_INTEL, 0x1c4a, "H67" }, - { PCI_VENDOR_ID_INTEL, 0x1c4b, "HM67" }, - { PCI_VENDOR_ID_INTEL, 0x1c4c, "Q65" }, - { PCI_VENDOR_ID_INTEL, 0x1c4d, "QS67" }, - { PCI_VENDOR_ID_INTEL, 0x1c4e, "Q67" }, - { PCI_VENDOR_ID_INTEL, 0x1c4f, "QM67" }, - { PCI_VENDOR_ID_INTEL, 0x1c50, "B65" }, - { PCI_VENDOR_ID_INTEL, 0x1c52, "C202" }, - { PCI_VENDOR_ID_INTEL, 0x1c54, "C204" }, - { PCI_VENDOR_ID_INTEL, 0x1c56, "C206" }, - { PCI_VENDOR_ID_INTEL, 0x1c5c, "H61" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z68, "Z68" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_P67, "P67" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UM67, "UM67" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65, "HM65" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H67, "H67" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM67, "HM67" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q65, "Q65" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QS67, "QS67" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q67, "Q67" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM67, "QM67" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B65, "B65" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C202, "C202" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C204, "C204" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C206, "C206" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H61, "H61" }, { PCI_VENDOR_ID_INTEL, 0x1d40, "X79" }, { PCI_VENDOR_ID_INTEL, 0x1d41, "X79" }, - { PCI_VENDOR_ID_INTEL, 0x1e44, "Z77" }, - { PCI_VENDOR_ID_INTEL, 0x1e46, "Z75" }, - { PCI_VENDOR_ID_INTEL, 0x1e47, "Q77" }, - { PCI_VENDOR_ID_INTEL, 0x1e48, "Q75" }, - { PCI_VENDOR_ID_INTEL, 0x1e49, "B75" }, - { PCI_VENDOR_ID_INTEL, 0x1e4a, "H77" }, - { PCI_VENDOR_ID_INTEL, 0x1e53, "C216" }, - { PCI_VENDOR_ID_INTEL, 0x1e55, "QM77" }, - { PCI_VENDOR_ID_INTEL, 0x1e56, "QS77" }, - { PCI_VENDOR_ID_INTEL, 0x1e57, "HM77" }, - { PCI_VENDOR_ID_INTEL, 0x1e58, "UM77" }, - { PCI_VENDOR_ID_INTEL, 0x1e59, "HM76" }, - { PCI_VENDOR_ID_INTEL, 0x1e5d, "HM75" }, - { PCI_VENDOR_ID_INTEL, 0x1e5e, "HM70" }, - { PCI_VENDOR_ID_INTEL, 0x1e5f, "NM70" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z77, "Z77" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z75, "Z75" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q77, "Q77" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q75, "Q75" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B75, "B75" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H77, "H77" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C216, "C216" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM77, "QM77" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QS77, "QS77" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM77, "HM77" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UM77, "UM77" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM76, "HM76" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM75, "HM75" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM70, "HM70" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM70, "NM70" }, { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, }; diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 00adc68..ac23fe1 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -61,6 +61,36 @@ #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 +#define PCI_DEVICE_ID_INTEL_Z68 0x1c44 +#define PCI_DEVICE_ID_INTEL_P67 0x1c46 +#define PCI_DEVICE_ID_INTEL_UM67 0x1c47 +#define PCI_DEVICE_ID_INTEL_HM65 0x1c49 +#define PCI_DEVICE_ID_INTEL_H67 0x1c4a +#define PCI_DEVICE_ID_INTEL_HM67 0x1c4b +#define PCI_DEVICE_ID_INTEL_Q65 0x1c4c +#define PCI_DEVICE_ID_INTEL_QS67 0x1c4d +#define PCI_DEVICE_ID_INTEL_Q67 0x1c4e +#define PCI_DEVICE_ID_INTEL_QM67 0x1c4f +#define PCI_DEVICE_ID_INTEL_B65 0x1c50 +#define PCI_DEVICE_ID_INTEL_C202 0x1c52 +#define PCI_DEVICE_ID_INTEL_C204 0x1c54 +#define PCI_DEVICE_ID_INTEL_C206 0x1c56 +#define PCI_DEVICE_ID_INTEL_H61 0x1c5c +#define PCI_DEVICE_ID_INTEL_Z77 0x1e44 +#define PCI_DEVICE_ID_INTEL_Z75 0x1e46 +#define PCI_DEVICE_ID_INTEL_Q77 0x1e47 +#define PCI_DEVICE_ID_INTEL_Q75 0x1e48 +#define PCI_DEVICE_ID_INTEL_B75 0x1e49 +#define PCI_DEVICE_ID_INTEL_H77 0x1e4a +#define PCI_DEVICE_ID_INTEL_C216 0x1e53 +#define PCI_DEVICE_ID_INTEL_QM77 0x1e55 +#define PCI_DEVICE_ID_INTEL_QS77 0x1e56 +#define PCI_DEVICE_ID_INTEL_HM77 0x1e57 +#define PCI_DEVICE_ID_INTEL_UM77 0x1e58 +#define PCI_DEVICE_ID_INTEL_HM76 0x1e59 +#define PCI_DEVICE_ID_INTEL_HM75 0x1e5d +#define PCI_DEVICE_ID_INTEL_HM70 0x1e5e +#define PCI_DEVICE_ID_INTEL_NM70 0x1e5f #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122

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Patch merged into coreboot/master: 28adb6e coreboot table: use memrange library
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 28adb6ead6d82073f32e4e786728e27326ccbc6c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Mar 23 00:06:36 2013 -0500 coreboot table: use memrange library Use the memrange library for keeping track of the address space region types. The memrange library is built to do just that for both the MTRR code and the coreboot memtable code. Change-Id: Iee2a7c37a3f4cf388db87ce40b580f274384ff3c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2917 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 29 05:05:10 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Mar 29 18:38:41 2013, giving +2 See http://review.coreboot.org/2917 for details. -gerrit

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Patch merged into coreboot/master: 7762091 armv7: set cache level explicitly for dcache/unified cache case
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 7762091fcb91710615f20229d43fc7fc7246ccdb Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 18:37:29 2013 -0700 armv7: set cache level explicitly for dcache/unified cache case This adds a missing CSSELR write in the case of a dcache or unified cache being invalidated by armv7_invalidate_caches(), ensuring that all levels of dcache/unified cache are invalidated as expected when the function is called. Change-Id: Ie90184bf8a8181afa3afe0786897455b30b7f022 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2947 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Mar 29 04:00:04 2013, giving +1 See http://review.coreboot.org/2947 for details. -gerrit

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Patch merged into coreboot/master: d4d6a40 armv7: invalidate TLB after changing translation table entries
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit d4d6a407f74e241c0d00c2eeac2fb85e7f08f989 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 18:28:30 2013 -0700 armv7: invalidate TLB after changing translation table entries This adds a call to tlb_invalidate_all() after configuring a range of memory. Change-Id: I558402e7e54b6bf9e0b013f153d9b84c0873a6cf Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2946 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Mar 29 03:46:32 2013, giving +1 See http://review.coreboot.org/2946 for details. -gerrit

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New patch to review for coreboot: caeeb23 x86: mtrr: optimize hole carving above 4GiB
by Aaron Durbin 29 Mar '13

29 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2959 -gerrit commit caeeb23f58515996d67a3ca4060fe4ad97591286 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 29 11:48:27 2013 -0500 x86: mtrr: optimize hole carving above 4GiB There is an optimization that can take place when hole carving in ranges above 4GiB. If the range is the last range then there is no need to carve UC holes out from the larger WB range. This optimization also has the same assumption of choosing WB as the default MTRR type: the OS needs to properly handle accessing realloacted MMIO resources with PAT so that the MTRR type can be overidden. Below are results using a combination of options. The board this was tested on has 10 variable MTRRs at its disposal. It has 4GiB of RAM. IO hole config #1: hole starts at 0xad800000 No CACHE_ROM and no WRCOMB resources (takes 4 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x0000000100000000 size 0x52800000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 4/6. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 No CACHE_ROM and 1 WRCOMB resource (takes 6 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 6/7. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 CACHE_ROM and no WRCOMB resources (takes 7 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000ff800000 size 0x52000000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 11/7. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6 MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6 MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 5 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 6 base 0x0000000100000000 mask 0x0000007f00000000 type 6 CACHE_ROM and 1 WRCOMB resource (takes 8 MTRRs): Previously this combination was impossible without the optimization. MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 12/8. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6 MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6 MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 5 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 6 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 7 base 0x0000000100000000 mask 0x0000007f00000000 type 6 IO hole config #1: hole starts at 0x80000000 No CACHE_ROM and no WRCOMB resources (takes 1 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 1/2. MTRR: WB selected as default type. MTRR: 0 base 0x0000000080000000 mask 0x0000007f80000000 type 0 No CACHE_ROM and 1 WRCOMB resource (takes 3 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 4/3. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6 CACHE_ROM and no WRCOMB resources (takes 3 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000ff800000 size 0x7f800000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 9/3. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6 CACHE_ROM and 1 WRCOMB resource (takes 4 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 10/4. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 2 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 3 base 0x0000000100000000 mask 0x0000007f00000000 type 6 Change-Id: Ia3195af686c3f0603b21f713cfb2d9075eb02806 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 005ea81..253a7c3 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -553,14 +553,31 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, if (!var_state->above4gb && a2 > RANGE_4GB) a2 = RANGE_4GB; + next = memranges_next_entry(var_state->addr_space, r); + b1 = a2; + + /* First check if a1 is >= 4GiB and the current etnry is the last + * entry. If so perform an optimization of covering a larger range + * defined by the base address' alignment. */ + if (a1 >= RANGE_4GB && next == NULL) { + uint32_t addr_lsb; + + addr_lsb = fls(a1); + b2 = (1 << addr_lsb) + a1; + if (b2 >= a2) { + calc_var_mtrr_range(var_state, a1, b2 - a1, mtrr_type); + return; + } + } + + /* Handle the min alignment roundup case. */ b2 = ALIGN_UP(a2, MTRR_MIN_ALIGN); /* Check against the next range. If the current range_entry is the * last entry then carving a hole is no problem. If the current entry * isn't the last entry then check that the last entry covers the * entire hole range with the default mtrr type. */ - next = memranges_next_entry(var_state->addr_space, r); if (next != NULL && (range_entry_mtrr_type(next) != var_state->def_mtrr_type || range_entry_end_mtrr_addr(next) < b2)) {

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Patch merged into coreboot/master: 7b19f66 armv7: iterate thru all levels when doing dcache ops
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit 7b19f669025a9f1dfc32035d7c93231e7a59c456 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 18:26:03 2013 -0700 armv7: iterate thru all levels when doing dcache ops This makes dcache maintenance functions operate on all levels of cache instead of just the current one. Change-Id: I2708fc7ba6da6740dbdfd733d937e7c943012d62 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2945 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Mar 29 03:33:42 2013, giving +1 See http://review.coreboot.org/2945 for details. -gerrit

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New patch to review for coreboot: 385ec20 AMD SB9xx boards: Include `hudson.h` for `pm_ioread` and delete `pmio.h`
by Paul Menzel 29 Mar '13

29 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2958 -gerrit commit 385ec2064b6a8df30604238206161f19621d5cc2 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 15:59:13 2013 +0100 AMD SB9xx boards: Include `hudson.h` for `pm_ioread` and delete `pmio.h` Unfortunately, an unneeded mainboard specific `pmio.h` was created when merging the board support. Rudolf used the header from a more generic location doing the the ASUS F2A85-M port, but did not delete the `pmio.h` header file. So adapt AMD Parmer and Thatcher to use the Hudson one and delete the mainboard specific header file to avoid duplication. Change-Id: I961cd145ebc3b83e31c638ac453ac95ee19c18db Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/parmer/mptable.c | 2 +- src/mainboard/amd/parmer/pmio.h | 33 --------------------------------- src/mainboard/amd/thatcher/mptable.c | 2 +- src/mainboard/amd/thatcher/pmio.h | 33 --------------------------------- src/mainboard/asus/f2a85-m/mptable.c | 2 +- src/mainboard/asus/f2a85-m/pmio.h | 33 --------------------------------- 6 files changed, 3 insertions(+), 102 deletions(-) diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 268f6d8..67f73c4 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -24,9 +24,9 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/amdfam15.h> -#include "pmio.h" #include <arch/cpu.h> #include <cpu/x86/lapic.h> +#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS diff --git a/src/mainboard/amd/parmer/pmio.h b/src/mainboard/amd/parmer/pmio.h deleted file mode 100644 index 35751f5..0000000 --- a/src/mainboard/amd/parmer/pmio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PMIO_H_ -#define _PMIO_H_ - -#define PM_INDEX 0xCD6 -#define PM_DATA 0xCD7 -#define PM2_INDEX 0xCD0 -#define PM2_DATA 0xCD1 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index ffa7992..8253b2c 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -24,9 +24,9 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/amdfam15.h> -#include "pmio.h" #include <arch/cpu.h> #include <cpu/x86/lapic.h> +#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS diff --git a/src/mainboard/amd/thatcher/pmio.h b/src/mainboard/amd/thatcher/pmio.h deleted file mode 100644 index 35751f5..0000000 --- a/src/mainboard/amd/thatcher/pmio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PMIO_H_ -#define _PMIO_H_ - -#define PM_INDEX 0xCD6 -#define PM_DATA 0xCD7 -#define PM2_INDEX 0xCD0 -#define PM2_DATA 0xCD1 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 5b6136c..6ed9fca 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -26,7 +26,7 @@ #include <cpu/amd/amdfam15.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "southbridge/amd/agesa/hudson/hudson.h" +#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 diff --git a/src/mainboard/asus/f2a85-m/pmio.h b/src/mainboard/asus/f2a85-m/pmio.h deleted file mode 100644 index 35751f5..0000000 --- a/src/mainboard/asus/f2a85-m/pmio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PMIO_H_ -#define _PMIO_H_ - -#define PM_INDEX 0xCD6 -#define PM_DATA 0xCD7 -#define PM2_INDEX 0xCD0 -#define PM2_DATA 0xCD1 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif

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coreboot-gerrit March 2013