coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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443 discussions

New patch to review for coreboot: c745467 snow: explicitly configure L2 cache
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2950 -gerrit commit c745467db847968fd1d8ca356acc1feff5a9d724 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 19:05:29 2013 -0700 snow: explicitly configure L2 cache This adds a call to explicitly configure L2 cache (though defaults should be set correctly). Change-Id: I120e29c986918c2904a0332e46fcf9f1c5380d85 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/ramstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 1751a1b..1459279 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -21,6 +21,7 @@ #include <cbmem.h> #include <arch/exception.h> #include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> #include <arch/cache.h> @@ -45,6 +46,7 @@ void main(void) /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ + exynos5_config_l2_cache(); mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);

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New patch to review for coreboot: fcddc24 exynos5250: Add functions for configuring L2 cache
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2949 -gerrit commit fcddc243428064380ca53ef816f20f3c8e9c45ba Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 19:04:58 2013 -0700 exynos5250: Add functions for configuring L2 cache This adds functions to configure L2 cache. Change-Id: I9562f3301aa1e2911dae3856ab57bb6beec2e224 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/cpu.c | 16 ++++++++++++++++ src/cpu/samsung/exynos5250/cpu.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index b6eae46..7b58ae1 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,5 +1,7 @@ #include <console/console.h> #include <device/device.h> +#include <arch/cache.h> +#include <cpu/samsung/exynos5250/cpu.h> #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) @@ -33,3 +35,17 @@ struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") .enable_dev = enable_dev, }; + +void exynos5_config_l2_cache(void) +{ + uint32_t val = read_l2ctlr(); + + /* + * Bit 9 - L2 tag RAM setup (1 cycle) + * Bits 8:6 - L2 tag RAM latency (3 cycles) + * Bit 5 - L2 data RAM setup (1 cycle) + * Bits 2:0 - L2 data RAM latency (3 cycles) + */ + val |= (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); + write_l2ctlr(val); +} diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index 772e591..83b3292 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -118,4 +118,6 @@ /* helper function to map mmio address to peripheral id */ enum periph_id exynos5_get_periph_id(unsigned base_addr); +void exynos5_config_l2_cache(void); + #endif /* _EXYNOS5250_CPU_H */

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New patch to review for coreboot: a02461d armv7: add functions for reading/writing L2CTLR
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2948 -gerrit commit a02461dd7b63936c007cf23f21fa0c0079efd784 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 19:04:14 2013 -0700 armv7: add functions for reading/writing L2CTLR This adds simple accessor functions for reading/writing L2CTLR. Change-Id: I2768d00d5bb2c43e84741ccead81e529dac9254d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/arch/cache.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index f074a3b..3e0ff2e 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -219,6 +219,25 @@ static inline void write_csselr(uint32_t val) isb(); /* ISB to sync the change to CCSIDR */ } +/* read L2 control register (L2CTLR) */ +static inline unsigned int read_l2ctlr(void) +{ + unsigned int val = 0; + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + return val; +} + +/* write L2 control register (L2CTLR) */ +static inline void write_l2ctlr(uint32_t val) +{ + /* + * Note: L2CTLR can only be written when the L2 memory system + * is idle, ie before the MMU is enabled. + */ + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" ); + isb(); +} + /* read system control register (SCTLR) */ static inline unsigned int read_sctlr(void) {

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New patch to review for coreboot: c11b51b armv7: set cache level explicitly for dcache/unified cache case
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2947 -gerrit commit c11b51b5ef9983d9dac3fe51ed3680f8ee3b0f23 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 18:37:29 2013 -0700 armv7: set cache level explicitly for dcache/unified cache case This adds a missing CSSELR write in the case of a dcache or unified cache being invalidated by armv7_invalidate_caches(), ensuring that all levels of dcache/unified cache are invalidated as expected when the function is called. Change-Id: Ie90184bf8a8181afa3afe0786897455b30b7f022 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/cache.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index da03a81..d65e021 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -310,6 +310,8 @@ void armv7_invalidate_caches(void) case 0x2: case 0x4: /* dcache only or unified cache */ + csselr = level << 1; + write_csselr(csselr); dcache_invalidate_all(); break; case 0x3:

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New patch to review for coreboot: b641366 armv7: invalidate TLB after changing translation table entries
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2946 -gerrit commit b641366b56ef72edcdcf327f7264730d88ff25e1 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 18:28:30 2013 -0700 armv7: invalidate TLB after changing translation table entries This adds a call to tlb_invalidate_all() after configuring a range of memory. Change-Id: I558402e7e54b6bf9e0b013f153d9b84c0873a6cf Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/mmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c index d55d4bd..224b566 100644 --- a/src/arch/armv7/lib/mmu.c +++ b/src/arch/armv7/lib/mmu.c @@ -88,6 +88,9 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, for (i = start_mb; i < start_mb + size_mb; i++) ttb_entry[i] = (i << 20) | attr; + + /* TODO: add helper to invalidate TLB by MVA */ + tlb_invalidate_all(); } void mmu_init(void)

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New patch to review for coreboot: ff40233 armv7: iterate thru all levels when doing dcache ops
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2945 -gerrit commit ff402334d6d77559dbb450125f12d7cc77b9a683 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 18:26:03 2013 -0700 armv7: iterate thru all levels when doing dcache ops This makes dcache maintenance functions operate on all levels of cache instead of just the current one. Change-Id: I2708fc7ba6da6740dbdfd733d937e7c943012d62 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/cache.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 8709daf..da03a81 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -148,14 +148,39 @@ static void dcache_op_set_way(enum dcache_op op) dsb(); } +static void dcache_foreach(enum dcache_op op) +{ + uint32_t clidr; + int level; + + clidr = read_clidr(); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + uint32_t csselr; + + switch(ctype) { + case 0x2: + case 0x3: + case 0x4: + csselr = level << 1; + write_csselr(csselr); + dcache_op_set_way(op); + break; + default: + /* no cache, icache only, or reserved */ + break; + } + } +} + void dcache_clean_invalidate_all(void) { - dcache_op_set_way(OP_DCCISW); + dcache_foreach(OP_DCCISW); } void dcache_invalidate_all(void) { - dcache_op_set_way(OP_DCISW); + dcache_foreach(OP_DCISW); } static unsigned int line_bytes(void)

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New patch to review for coreboot: dbbb106 armv7: use stdint.h in cache and MMU files
by David Hendricks 29 Mar '13

29 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2944 -gerrit commit dbbb10664f0657c045c971ced22b322328e3eee8 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 28 18:07:30 2013 -0700 armv7: use stdint.h in cache and MMU files This makes it easier to copy + paste code into libpayload since libpayload since both coreboot and libpayload have stdint.h and it defines the types needed. Change-Id: Ifa55f04a9bdddd17bc1a2679321a6744c75f25a8 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/cache.c | 2 +- src/arch/armv7/lib/mmu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 7bb337d..8709daf 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -31,7 +31,7 @@ * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition */ -#include <types.h> +#include <stdint.h> #include <arch/cache.h> diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c index 34a484f..d55d4bd 100644 --- a/src/arch/armv7/lib/mmu.c +++ b/src/arch/armv7/lib/mmu.c @@ -28,7 +28,7 @@ */ #include <stdlib.h> -#include <types.h> +#include <stdint.h> #include <cbmem.h> #include <console/console.h>

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Patch merged into coreboot/master: eca4843 armv7: added paranoia for cache library
by gerrit＠coreboot.org 29 Mar '13

29 Mar '13

the following patch was just integrated into master: commit eca48438fcac64d3b68f6028bcbe98b24547f033 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 26 21:26:51 2013 -0700 armv7: added paranoia for cache library This adds some paranoia to cache manipulation routines: - "memory" is added to the clobber list for functions which clean and/or invalidate dcache or TLB entries. - Remove unneeded clobber list for read_sctlr() Change-Id: Iaa82ef78bfdad4119f097c3b6db8219f29f832bc Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2928 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Mar 27 09:23:54 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Mar 29 00:26:25 2013, giving +2 See http://review.coreboot.org/2928 for details. -gerrit

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New patch to review for coreboot: 94e0b92 ASRock E350M1: Include ASL file of Winbond W83627HF in the DSDT
by Paul Menzel 28 Mar '13

28 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2943 -gerrit commit 94e0b9264200b90a920b8157a85adc064b124d7f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Mar 28 14:05:45 2013 +0100 ASRock E350M1: Include ASL file of Winbond W83627HF in the DSDT Unfortunately there are still some problems, but note that the ASRock E350M1 actually has a Nuvoton NCT6775F, which is supposed to be compatible though [1]. At least Scott chose it in its `devicetree.cb`. Hooking up this ACPI snippet, under Linux, serial does not work anymore. It works fine for coreboot, SeaBIOS and GRUB. $ dmesg | egrep -i -e kbd -e acpi [ 0.145384] calling acpi_pci_init+0x0/0x4d @ 1 [ 0.145388] ACPI: bus type pci registered [ 0.145392] initcall acpi_pci_init+0x0/0x4d returned 0 after 0 usecs [ 0.148960] calling acpi_init+0x0/0x27b @ 1 [ 0.148960] ACPI: Added _OSI(Module Device) [ 0.148960] ACPI: Added _OSI(Processor Device) [ 0.148960] ACPI: Added _OSI(3.0 _SCP Extensions) [ 0.148960] ACPI: Added _OSI(Processor Aggregator Device) [ 0.149539] ACPI: EC: Look up EC in DSDT [ 0.152869] ACPI: Executed 2 blocks of module-level executable AML code [ 0.158645] ACPI: Interpreter enabled [ 0.158655] ACPI: (supports S0 S1 S2 S3 S4 S5) [ 0.158705] ACPI: BIOS offers _BFS [ 0.158708] ACPI: If "acpi.bfs=1" improves resume, please notify linux-acpi(a)vger.kernel.org [ 0.158713] ACPI: Using IOAPIC for interrupt routing [ 0.183262] initcall acpi_init+0x0/0x27b returned 0 after 31251 usecs [ 0.183448] ACPI: No dock devices found. [ 0.183459] calling acpi_pci_root_init+0x0/0x26 @ 1 [ 0.183472] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.183609] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.186229] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 0.186570] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.AGPB._PRT] [ 0.186658] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT] [ 0.186864] pci0000:00: Requesting ACPI _OSC control (0x1d) [ 0.186918] pci0000:00: ACPI _OSC control (0x1d) granted [ 0.196771] initcall acpi_pci_root_init+0x0/0x26 returned 0 after 15625 usecs [ 0.196778] calling acpi_pci_link_init+0x0/0x36 @ 1 [ 0.196927] ACPI: PCI Interrupt Link [INTA] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.197157] ACPI: PCI Interrupt Link [INTB] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.197313] ACPI: PCI Interrupt Link [INTC] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.197468] ACPI: PCI Interrupt Link [INTD] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.197623] ACPI: PCI Interrupt Link [INTE] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.197777] ACPI: PCI Interrupt Link [INTF] (IRQs 9) *0 [ 0.197927] ACPI: PCI Interrupt Link [INTG] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.198080] ACPI: PCI Interrupt Link [INTH] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.198133] initcall acpi_pci_link_init+0x0/0x36 returned 0 after 0 usecs [ 0.198564] PCI: Using ACPI for IRQ routing [ 0.203236] calling acpi_event_init+0x0/0x42 @ 1 [ 0.203260] initcall acpi_event_init+0x0/0x42 returned 0 after 17 usecs [ 0.203305] calling pnpacpi_init+0x0/0x77 @ 1 [ 0.203309] pnp: PnP ACPI init [ 0.203340] ACPI: bus type pnp registered [ 0.203762] pnp 00:00: Plug and Play ACPI device, IDs PNP0a05 (active) [ 0.204137] pnp 00:01: Plug and Play ACPI device, IDs PNP0700 (disabled) [ 0.204451] pnp 00:02: Plug and Play ACPI device, IDs PNP0400 (disabled) [ 0.204734] pnp 00:03: Plug and Play ACPI device, IDs PNP0501 (disabled) [ 0.205029] pnp 00:04: Plug and Play ACPI device, IDs PNP0501 (disabled) [ 0.205471] pnp 00:05: Plug and Play ACPI device, IDs PNP0303 (disabled) [ 0.205747] pnp 00:06: Plug and Play ACPI device, IDs PNP0f13 (disabled) [ 0.205986] pnp 00:07: Plug and Play ACPI device, IDs PNPb02f (disabled) [ 0.206241] pnp 00:08: Plug and Play ACPI device, IDs PNPb006 (disabled) [ 0.206510] system 00:09: Plug and Play ACPI device, IDs PNP0c02 (disabled) [ 0.206715] pnp 00:0a: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active) [ 0.207119] pnp 00:0b: Plug and Play ACPI device, IDs PNP0b00 (active) [ 0.207203] pnp 00:0c: Plug and Play ACPI device, IDs PNP0800 (active) [ 0.207314] pnp 00:0d: Plug and Play ACPI device, IDs PNP0200 (active) [ 0.207476] pnp 00:0e: Plug and Play ACPI device, IDs PNP0c04 (active) [ 0.207502] pnp: PnP ACPI: found 15 devices [ 0.207506] ACPI: ACPI bus type pnp unregistered [ 0.207582] initcall pnpacpi_init+0x0/0x77 returned 0 after 4169 usecs [ 0.207594] PnPBIOS: Disabled by ACPI PNP [ 0.225665] calling init_acpi_pm_clocksource+0x0/0x164 @ 1 [ 0.260733] initcall init_acpi_pm_clocksource+0x0/0x164 returned 0 after 34239 usecs [ 0.855693] calling acpiphp_init+0x0/0x4e @ 1 [ 0.855697] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 [ 0.856259] initcall acpiphp_init+0x0/0x4e returned -19 after 546 usecs [ 0.856609] calling acpi_reserve_resources+0x0/0xc4 @ 1 [ 0.856621] initcall acpi_reserve_resources+0x0/0xc4 returned 0 after 5 usecs [ 0.856638] calling acpi_hed_init+0x0/0x1f @ 1 [ 0.856675] initcall acpi_hed_init+0x0/0x1f returned 0 after 29 usecs [ 0.970098] i8042 kbd 00:05: [irq 1] [ 0.970106] i8042 kbd 00:05: unable to assign resources [ 0.970349] i8042 kbd: probe of 00:05 failed with error -16 [ 0.971153] i8042: PNP: PS/2 controller doesn't have KBD irq; using default 1 [ 1.224701] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.225631] calling atkbd_init+0x0/0x1b @ 1 [ 1.225751] initcall atkbd_init+0x0/0x1b returned 0 after 109 usecs [ 1.225757] calling xenkbd_init+0x0/0x46 @ 1 [ 1.225765] initcall xenkbd_init+0x0/0x46 returned -19 after 1 usecs [ 25.448901] calling acpi_container_init+0x0/0x1000 [container] @ 499 [ 25.452331] initcall acpi_container_init+0x0/0x1000 [container] returned 0 after 3337 usecs [ 25.453368] calling acpi_button_init+0x0/0x1000 [button] @ 498 [ 25.453569] ACPI: Power Button [PWRB] [ 25.453701] ACPI: Power Button [PWRF] [ 25.453802] initcall acpi_button_init+0x0/0x1000 [button] returned 0 after 411 usecs [ 25.510107] calling acpi_processor_init+0x0/0x1000 [processor] @ 504 [ 25.510247] ACPI: acpi_idle registered with cpuidle [ 25.511931] initcall acpi_processor_init+0x0/0x1000 [processor] returned 0 after 1762 usecs [ 26.386279] parport_pc 00:02: reported by Plug and Play ACPI [1] https://www.kernel.org/doc/Documentation/hwmon/w83627ehf Change-Id: I82c98f16e6879d47594fcf90140a827b98a39a7f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/dsdt.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 25030aa..7520be8 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -792,6 +792,8 @@ DefinitionBlock ( } /* End Method(_SB.INTH._SRS) */ } /* End Device(INTH) */ + #include <superio/winbond/w83627hf/acpi/superio.asl> + } /* End Scope(_SB) */

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New patch to review for coreboot: 153f968 Winbond W83627HF: ACPI: Make `AddressMax` a multiple of `AddressAlignment`
by Paul Menzel 28 Mar '13

28 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2942 -gerrit commit 153f968e4c0b536f8a8a4934b3acfe74ad078d67 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Mar 28 14:59:34 2013 +0100 Winbond W83627HF: ACPI: Make `AddressMax` a multiple of `AddressAlignment` Hooking the ASL into the DSDT of the ASRock E350M1, building fails with the following error. […] Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 1281: IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) Error 4001 - ^ Must be a multiple of alignment/granularity value dsdt.ramstage.asl 1415: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 1524: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 1633: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 1705: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 1788: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 1855: CreateByteField (Arg0, IRQX._INT, IRQL) Warning 1126 - ResourceTag larger than Field ^ (Size mismatch, Tag: 16 bits, Field: 8 bits) dsdt.ramstage.asl 2304: Method(_OSC,4) Warning 1114 - ^ Not all control paths return a value (_OSC) dsdt.ramstage.asl 2304: Method(_OSC,4) Warning 1106 - ^ Reserved method must return a value (Buffer required for _OSC) ASL Input: dsdt.ramstage.asl - 2885 lines, 58411 bytes, 1507 keywords Hex Dump: dsdt.ramstage.hex - 155352 bytes Compilation complete. 1 Errors, 9 Warnings, 0 Remarks, 547 Optimizations make: *** [build/mainboard/asrock/e350m1/dsdt.ramstage.o] Fehler 255 According to the ACPI specification the maximum acceptable starting address `AddressMax` has to be a multiple of the alignment granularity for the I/O address. Citing ACPI specification 4.0a, page 612 [1]. 18.5.56 IO (IO Resource Descriptor Macro) ### Syntax IO (Decode, AddressMin, AddressMax, AddressAlignment, RangeLength, DescriptorName) => Buffer ### Argument […] AddressMax evaluates to a 16-bit integer that specifies the maximum acceptable starting address for the I/O range. It must be an even multiple of AddressAlignment. The field DescriptorName._MAX is automatically created to refer to this portion of the resource descriptor. Use address 0x0FF0, a multiple of 0x08, instead of 0x0FFC, fixes the error. [1] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf Change-Id: I272e09d091149791f2867b1d06e4fc27bc1bb2cd Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/superio/winbond/w83627hf/acpi/superio.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 69017fe..2e12ef8 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -556,7 +556,7 @@ Device(SIO) { } StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) + IO (Decode16, 0x0100, 0x0FF0, 0x08, 0x08) IRQNoFlags () {3,4,5,7,9,10,11,12} } StartDependentFn (2,1)

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coreboot-gerrit March 2013