Patch set updated for coreboot: f465637 snow: explicitly configure L2 cache

[David Hendricks]

David Hendricks ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2950

-gerrit

commit f465637bb42a04f50b0c56909faf54f6065bf39d
Author: David Hendricks 
Date:   Thu Mar 28 19:05:29 2013 -0700

snow: explicitly configure L2 cache

This adds a call to explicitly configure L2 cache (though defaults
    should be set correctly).

Change-Id: I120e29c986918c2904a0332e46fcf9f1c5380d85
    Signed-off-by: David Hendricks 
---
 src/mainboard/google/snow/ramstage.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index 1751a1b..9081629 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -21,6 +21,7 @@
 #include <cbmem.h>
 #include <arch/exception.h>
 #include <cpu/samsung/exynos5250/clk.h>
+#include <cpu/samsung/exynos5250/cpu.h>
 #include <cpu/samsung/exynos5250/power.h>

#include <arch/cache.h>
@@ -45,6 +46,7 @@ void main(void)

/* set up dcache and MMU */
    /* FIXME: this should happen via resource allocator */
+	exynos5250_config_l2_cache();
    mmu_init();
    mmu_config_range(0, DRAM_START, DCACHE_OFF);
    mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);