coreboot-gerrit March 2013

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New patch to review for coreboot: 5de4c5f libpayload: fix size_t handling
by Stefan Reinauer 25 Mar '13

25 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2904 -gerrit commit 5de4c5f9080725f2462969b68d4a3a31fad487e1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 25 15:13:20 2013 -0700 libpayload: fix size_t handling libcbfs was using printf for size_t typed variables. However, printf did not support printing those. This patch fixes the issue, removing the warning when compiling ram_media.c libcbfs/ram_media.c:52:10: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'long unsigned int' [-Wformat] libcbfs/ram_media.c:52:10: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat] Change-Id: Iaf6e723f9a5b0a61a39d3125036fee9853e37ba8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/libc/printf.c | 3 +++ payloads/libpayload/libcbfs/ram_media.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/libc/printf.c b/payloads/libpayload/libc/printf.c index ccb64fd..bc2c41c 100644 --- a/payloads/libpayload/libc/printf.c +++ b/payloads/libpayload/libc/printf.c @@ -552,6 +552,9 @@ static int printf_core(const char *fmt, struct printf_spec *ps, va_list ap) qualifier = PrintfQualifierByte; } break; + case 'z': /* size_t or ssize_t */ + qualifier = PrintfQualifierLong; + break; case 'l': /* long or long long */ qualifier = PrintfQualifierLong; if (fmt[i] == 'l') { diff --git a/payloads/libpayload/libcbfs/ram_media.c b/payloads/libpayload/libcbfs/ram_media.c index 1a0500e..859555c 100644 --- a/payloads/libpayload/libcbfs/ram_media.c +++ b/payloads/libpayload/libcbfs/ram_media.c @@ -48,7 +48,7 @@ static void *ram_map(struct cbfs_media *media, size_t offset, size_t count) { offset = m->size + offset; } if (offset + count > m->size) { - printf("ERROR: ram_map: request out of range (0x%x+0x%x)\n", + printf("ERROR: ram_map: request out of range (0x%zx+0x%zx)\n", offset, count); return NULL; }

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Patch set updated for coreboot: 5165e77 samsung/exynos5: add resource functions for the display port
by Ronald G. Minnich 25 Mar '13

25 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2615 -gerrit commit 5165e778d0406d1eec3cf0fd0515e15fd402bdc8 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 18 09:49:54 2013 -0700 samsung/exynos5: add resource functions for the display port This does NOT turn on the graphics. The device tree has been changed enough so that, at the very least, the correct functions are called at the correct time, with the correct paramaters. We decided to yank the I2C entries as they did not obvious function and might not even have been correct. Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. We realized that the display code should be part of the cpu -- that's how the hardware works! Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/displayport/Kconfig | 2 - .../exynos5-common/displayport/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/displayport/chip.h | 40 -------- .../exynos5-common/displayport/displayport.c | 107 --------------------- src/cpu/samsung/exynos5-common/exynos-fb.c | 4 +- src/cpu/samsung/exynos5250/chip.h | 40 ++++++++ src/cpu/samsung/exynos5250/cpu.c | 84 +++++++++++++++- src/mainboard/google/snow/devicetree.cb | 17 +--- src/vendorcode/google/chromeos/build-snow | 4 +- 9 files changed, 130 insertions(+), 170 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig deleted file mode 100644 index 26d1422..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config EXYNOS_DISPLAYPORT - bool diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc deleted file mode 100644 index 7c52eaf..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c - diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h deleted file mode 100644 index 53b7836..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/chip.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H -#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H - -struct cpu_samsung_exynos5_common_displayport_config { - /* special magic numbers! */ - int clkval_f; - int upper_margin; - int lower_margin; - int vsync; - int left_margin; - int right_margin; - int hsync; - - int xres; - int yres; - int bpp; - - u32 lcdbase; -}; - -#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c deleted file mode 100644 index 1c08bc7..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/displayport.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <delay.h> -#include <arch/io.h> -#include <device/device.h> - -/* we distinguish a display port device from a raw graphics device because there are - * dramatic differences in startup depending on graphics usage. To make startup fast - * and easier to understand and debug we explicitly name this common case. The alternate - * approach, involving lots of machine and callbacks, is hard to debug and verify. - */ -static void exynos_displayport_init(void) -{ - struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; - /* put these on the stack. If, at some point, we want to move this code to a - * pre-ram stage, it will be much easier. - */ - vidinfo_t vi; - struct exynos5_fimd_panel panel; - void *lcdbase; - - memset(vi, 0, sizeof(vi)); - memset(panel, 0, sizeof(panel)); - - panel.is_dp = 1; /* Display I/F is eDP */ - /* while it is true that we did a memset to zero, - * we leave some 'set to zero' entries here to make - * it clear what's going on. Graphics is confusing. - */ - panel.is_mipi = 0; - panel.fixvclk = 0; - panel.ivclk = 0; - panel.clkval_f = conf->clkval_f; - panel.upper_margin = conf->upper_margin; - panel.lower_margin = conf->lower_margin; - panel.vsync = conf->vsync; - panel.left_margin = conf->left_margin; - panel.right_margin = conf->right_margin; - panel.hsync = conf->hsync; - - vi->vl_col = conf->xres; - vi->fl_row = conf->yres; - vi->vl_bpix = conf->bpp; - vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */ - - lcdbase = conf->lcdbase; - printk(BIOS_DEBUG, "Initializing exynos VGA\n"); - ret = lcd_ctrl_init(&vi, &panel, lcdbase); -#if 0 - ret = board_dp_lcd_vdd(blob, &wait_ms); - ret = board_dp_bridge_setup(blob, &wait_ms); - while (tries < 5) { - ret = board_dp_bridge_init(blob, &wait_ms); - ret = board_dp_hotplug(blob, &wait_ms); - if (ret) { - ret = board_dp_bridge_reset(blob, &wait_ms); - continue; - } - ret = dp_controller_init(blob, &wait_ms); - ret = board_dp_backlight_vdd(blob, &wait_ms); - ret = board_dp_backlight_pwm(blob, &wait_ms); - ret = board_dp_backlight_en(blob, &wait_ms); - } -#endif -} - -static void exynos_displayport_noop(device_t dummy) -{ -} - -static struct device_operations exynos_displayport_operations = { - .read_resources = exynos_displayport_noop, - .set_resources = exynos_displayport_noop, - .enable_resources = exynos_displayport_noop, - .init = exynos_displayport_init, - .scan_bus = exynos_displayport_noop, -}; - -static void exynos_displayport_enable(struct device *dev) -{ - if (dev->link_list != NULL) - dev->ops = &exynos_displayport_operations; -} - -struct chip_operations drivers_i2c_exynos_displayport_ops = { - CHIP_NAME("exynos displayport") - .enable_dev = exynos_displayport_enable; -}; diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 30d0767..2671305 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -100,7 +100,7 @@ static void fimd_bypass(void) { struct exynos5_sysreg *sysreg = samsung_get_base_sysreg(); - /*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/ + setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } @@ -586,7 +586,9 @@ int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, //vi->yres = panel_info->vl_row; fimd_bypass(); + printk(BIOS_SPEW, "fimd_bypass\n"); fb_init(panel_info, lcdbase, panel_data); + printk(BIOS_SPEW, "fb_init(%p, %p, %p\n",panel_info, lcdbase, panel_data); /* Enable flushing after LCD writes if requested */ // forget it. lcd_set_flush_dcache(1); diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h new file mode 100644 index 0000000..798cd26 --- /dev/null +++ b/src/cpu/samsung/exynos5250/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5250_H +#define CPU_SAMSUNG_EXYNOS5250_H + +struct cpu_samsung_exynos5250_config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5250_H */ diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index bcf4d22..114d691 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,5 +1,14 @@ +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <delay.h> #include <console/console.h> +#include <arch/io.h> #include <device/device.h> +#include <cbmem.h> +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> +#include "chip.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) @@ -28,8 +37,76 @@ static struct device_operations domain_ops = { .scan_bus = domain_scan_bus, }; +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(device_t dev) +{ + int ret; + struct cpu_samsung_exynos5250_config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + u32 lcdbase; + + printk(BIOS_SPEW, "%s: dev %p, conf %p\n", __func__, dev, conf); + memset(&vi, 0, sizeof(vi)); + memset(&panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi.vl_col = conf->xres; + vi.vl_row = conf->yres; + vi.vl_bpix = conf->bpp; + printk(BIOS_SPEW, "lcd base is %p\n", (void *)(conf->lcdbase)); + /* The size is a magic number from hardware. */ + mmio_resource(dev, 0, conf->lcdbase/KiB, 64); + vi.cmap = (void *)conf->lcdbase; + lcdbase = conf->lcdbase + 64*KiB; + + mmio_resource(dev, 1, lcdbase, (conf->xres*conf->yres*4 + (KiB-1))/KiB); + printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); +#if 0 + ret = board_dp_lcd_vdd(blob, &wait_ms); + ret = board_dp_bridge_setup(blob, &wait_ms); + while (tries < 5) { + ret = board_dp_bridge_init(blob, &wait_ms); + ret = board_dp_hotplug(blob, &wait_ms); + if (ret) { + ret = board_dp_bridge_reset(blob, &wait_ms); + continue; + } + ret = dp_controller_init(blob, &wait_ms); + ret = board_dp_backlight_vdd(blob, &wait_ms); + ret = board_dp_backlight_pwm(blob, &wait_ms); + ret = board_dp_backlight_en(blob, &wait_ms); + } +#endif +} + static void cpu_init(device_t dev) { + printk(BIOS_SPEW, "%s\n", __func__); + exynos_displayport_init(dev); } static void cpu_noop(device_t dev) @@ -44,17 +121,20 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_exynos5250_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { + printk(BIOS_SPEW, "%s: DOMAIN\n", __func__); dev->ops = &domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + printk(BIOS_SPEW, "%s: CPU_CLUSTER\n", __func__); dev->ops = &cpu_ops; } + printk(BIOS_SPEW, "%s: done\n", __func__); } struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") - .enable_dev = enable_dev, + .enable_dev = enable_exynos5250_dev, }; diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 5ad786e..e8da851 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -17,18 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# FIXME: this is just a stub for now chip cpu/samsung/exynos5250 - -device cpu_cluster 0 on -end - -device domain 0 on - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # ? - device i2c 9 on end # ? - end - chip cpu/samsung/exynos5-common/displayport + device cpu_cluster 0 on end register "xres" = "1366" register "yres" = "768" register "bpp" = "16" @@ -40,7 +30,6 @@ device domain 0 on register "left_margin" = "80" register "right_margin" = "48" register "hsync" = "32" - register "lcdbase" = "0x10000000" - end -end + register "lcdbase" = "0x50000000" + end diff --git a/src/vendorcode/google/chromeos/build-snow b/src/vendorcode/google/chromeos/build-snow index a749ba5..9cdba75 100755 --- a/src/vendorcode/google/chromeos/build-snow +++ b/src/vendorcode/google/chromeos/build-snow @@ -70,8 +70,8 @@ main() { create_diff_192k "$OUTPUT" "$TMP_DIFF" echo "OK: Generated image (with BL1) in $OUTPUT" if is_servod_ready; then - echo "servod detected - flashing into device." - fast_flash_image "$OUTPUT" "$TMP_DIFF" + echo "servod detected - NOT flashing into device." + echo fast_flash_image "$OUTPUT" "$TMP_DIFF" echo "OK: Generated and flashed 128k of image into device via servo." else echo "(servod is not running, flashing into device is skipped)"

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Patch set updated for coreboot: fbfae40 samsung/exynos5: add resource functions for the display port
by Ronald G. Minnich 25 Mar '13

25 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2615 -gerrit commit fbfae403aa26cc1bc086184aa80ad5988e26a5fc Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 18 09:49:54 2013 -0700 samsung/exynos5: add resource functions for the display port This does NOT turn on the graphics. The device tree has been changed enough so that, at the very least, the correct functions are called at the correct time, with the correct paramaters. We decided to yank the I2C entries as they did not obvious function and might not even have been correct. Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. We realized that the display code should be part of the cpu -- that's how the hardware works! Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/displayport/Kconfig | 2 - .../exynos5-common/displayport/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/displayport/chip.h | 40 -------- .../exynos5-common/displayport/displayport.c | 107 --------------------- src/cpu/samsung/exynos5-common/exynos-fb.c | 4 +- src/cpu/samsung/exynos5250/chip.h | 40 ++++++++ src/cpu/samsung/exynos5250/cpu.c | 84 +++++++++++++++- src/mainboard/google/snow/devicetree.cb | 17 +--- src/vendorcode/google/chromeos/build-snow | 4 +- 9 files changed, 130 insertions(+), 170 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig deleted file mode 100644 index 26d1422..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config EXYNOS_DISPLAYPORT - bool diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc deleted file mode 100644 index 7c52eaf..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c - diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h deleted file mode 100644 index 53b7836..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/chip.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H -#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H - -struct cpu_samsung_exynos5_common_displayport_config { - /* special magic numbers! */ - int clkval_f; - int upper_margin; - int lower_margin; - int vsync; - int left_margin; - int right_margin; - int hsync; - - int xres; - int yres; - int bpp; - - u32 lcdbase; -}; - -#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c deleted file mode 100644 index 1c08bc7..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/displayport.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <delay.h> -#include <arch/io.h> -#include <device/device.h> - -/* we distinguish a display port device from a raw graphics device because there are - * dramatic differences in startup depending on graphics usage. To make startup fast - * and easier to understand and debug we explicitly name this common case. The alternate - * approach, involving lots of machine and callbacks, is hard to debug and verify. - */ -static void exynos_displayport_init(void) -{ - struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; - /* put these on the stack. If, at some point, we want to move this code to a - * pre-ram stage, it will be much easier. - */ - vidinfo_t vi; - struct exynos5_fimd_panel panel; - void *lcdbase; - - memset(vi, 0, sizeof(vi)); - memset(panel, 0, sizeof(panel)); - - panel.is_dp = 1; /* Display I/F is eDP */ - /* while it is true that we did a memset to zero, - * we leave some 'set to zero' entries here to make - * it clear what's going on. Graphics is confusing. - */ - panel.is_mipi = 0; - panel.fixvclk = 0; - panel.ivclk = 0; - panel.clkval_f = conf->clkval_f; - panel.upper_margin = conf->upper_margin; - panel.lower_margin = conf->lower_margin; - panel.vsync = conf->vsync; - panel.left_margin = conf->left_margin; - panel.right_margin = conf->right_margin; - panel.hsync = conf->hsync; - - vi->vl_col = conf->xres; - vi->fl_row = conf->yres; - vi->vl_bpix = conf->bpp; - vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */ - - lcdbase = conf->lcdbase; - printk(BIOS_DEBUG, "Initializing exynos VGA\n"); - ret = lcd_ctrl_init(&vi, &panel, lcdbase); -#if 0 - ret = board_dp_lcd_vdd(blob, &wait_ms); - ret = board_dp_bridge_setup(blob, &wait_ms); - while (tries < 5) { - ret = board_dp_bridge_init(blob, &wait_ms); - ret = board_dp_hotplug(blob, &wait_ms); - if (ret) { - ret = board_dp_bridge_reset(blob, &wait_ms); - continue; - } - ret = dp_controller_init(blob, &wait_ms); - ret = board_dp_backlight_vdd(blob, &wait_ms); - ret = board_dp_backlight_pwm(blob, &wait_ms); - ret = board_dp_backlight_en(blob, &wait_ms); - } -#endif -} - -static void exynos_displayport_noop(device_t dummy) -{ -} - -static struct device_operations exynos_displayport_operations = { - .read_resources = exynos_displayport_noop, - .set_resources = exynos_displayport_noop, - .enable_resources = exynos_displayport_noop, - .init = exynos_displayport_init, - .scan_bus = exynos_displayport_noop, -}; - -static void exynos_displayport_enable(struct device *dev) -{ - if (dev->link_list != NULL) - dev->ops = &exynos_displayport_operations; -} - -struct chip_operations drivers_i2c_exynos_displayport_ops = { - CHIP_NAME("exynos displayport") - .enable_dev = exynos_displayport_enable; -}; diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 30d0767..2671305 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -100,7 +100,7 @@ static void fimd_bypass(void) { struct exynos5_sysreg *sysreg = samsung_get_base_sysreg(); - /*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/ + setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } @@ -586,7 +586,9 @@ int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, //vi->yres = panel_info->vl_row; fimd_bypass(); + printk(BIOS_SPEW, "fimd_bypass\n"); fb_init(panel_info, lcdbase, panel_data); + printk(BIOS_SPEW, "fb_init(%p, %p, %p\n",panel_info, lcdbase, panel_data); /* Enable flushing after LCD writes if requested */ // forget it. lcd_set_flush_dcache(1); diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h new file mode 100644 index 0000000..798cd26 --- /dev/null +++ b/src/cpu/samsung/exynos5250/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5250_H +#define CPU_SAMSUNG_EXYNOS5250_H + +struct cpu_samsung_exynos5250_config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5250_H */ diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index bcf4d22..e127d36 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,5 +1,14 @@ +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <delay.h> #include <console/console.h> +#include <arch/io.h> #include <device/device.h> +#include <cbmem.h> +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> +#include "chip.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) @@ -28,8 +37,76 @@ static struct device_operations domain_ops = { .scan_bus = domain_scan_bus, }; +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(device_t dev) +{ + int ret; + struct cpu_samsung_exynos5250_config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + u32 lcdbase; + + printk(BIOS_SPEW, "%s: dev %p, conf %p\n", __func__, dev, conf); + memset(&vi, 0, sizeof(vi)); + memset(&panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi.vl_col = conf->xres; + vi.vl_row = conf->yres; + vi.vl_bpix = conf->bpp; + printk(BIOS_SPEW, "lcd base is %p\n", (void *)(conf->lcdbase)); + /* The size is a magic number from hardware. */ + mmio_resource(dev, 0, conf->lcdbase/KiB, 64); + vi.cmap = (void *)conf->lcdbase; + lcdbase = conf->lcdbase + 64*KiB; + + mmio_resource(dev, 1, lcdbase/KiB, (conf->xres*conf->yres*4 + (KiB-1))/KiB); + printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); +#if 0 + ret = board_dp_lcd_vdd(blob, &wait_ms); + ret = board_dp_bridge_setup(blob, &wait_ms); + while (tries < 5) { + ret = board_dp_bridge_init(blob, &wait_ms); + ret = board_dp_hotplug(blob, &wait_ms); + if (ret) { + ret = board_dp_bridge_reset(blob, &wait_ms); + continue; + } + ret = dp_controller_init(blob, &wait_ms); + ret = board_dp_backlight_vdd(blob, &wait_ms); + ret = board_dp_backlight_pwm(blob, &wait_ms); + ret = board_dp_backlight_en(blob, &wait_ms); + } +#endif +} + static void cpu_init(device_t dev) { + printk(BIOS_SPEW, "%s\n", __func__); + exynos_displayport_init(dev); } static void cpu_noop(device_t dev) @@ -44,17 +121,20 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_exynos5250_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { + printk(BIOS_SPEW, "%s: DOMAIN\n", __func__); dev->ops = &domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + printk(BIOS_SPEW, "%s: CPU_CLUSTER\n", __func__); dev->ops = &cpu_ops; } + printk(BIOS_SPEW, "%s: done\n", __func__); } struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") - .enable_dev = enable_dev, + .enable_dev = enable_exynos5250_dev, }; diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 5ad786e..e8da851 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -17,18 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# FIXME: this is just a stub for now chip cpu/samsung/exynos5250 - -device cpu_cluster 0 on -end - -device domain 0 on - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # ? - device i2c 9 on end # ? - end - chip cpu/samsung/exynos5-common/displayport + device cpu_cluster 0 on end register "xres" = "1366" register "yres" = "768" register "bpp" = "16" @@ -40,7 +30,6 @@ device domain 0 on register "left_margin" = "80" register "right_margin" = "48" register "hsync" = "32" - register "lcdbase" = "0x10000000" - end -end + register "lcdbase" = "0x50000000" + end diff --git a/src/vendorcode/google/chromeos/build-snow b/src/vendorcode/google/chromeos/build-snow index a749ba5..9cdba75 100755 --- a/src/vendorcode/google/chromeos/build-snow +++ b/src/vendorcode/google/chromeos/build-snow @@ -70,8 +70,8 @@ main() { create_diff_192k "$OUTPUT" "$TMP_DIFF" echo "OK: Generated image (with BL1) in $OUTPUT" if is_servod_ready; then - echo "servod detected - flashing into device." - fast_flash_image "$OUTPUT" "$TMP_DIFF" + echo "servod detected - NOT flashing into device." + echo fast_flash_image "$OUTPUT" "$TMP_DIFF" echo "OK: Generated and flashed 128k of image into device via servo." else echo "(servod is not running, flashing into device is skipped)"

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Patch merged into coreboot/master: 04d352d libpayload: Fix Config.in warning
by gerrit＠coreboot.org 25 Mar '13

25 Mar '13

the following patch was just integrated into master: commit 04d352db41522b3c7aec2ce574ff90484bc0ad8a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 25 14:13:43 2013 -0700 libpayload: Fix Config.in warning PDcurses is already default. Hence drop the additional attempt that is not supported by Kconfig. Config.in:123:warning: defaults for choice values not supported Change-Id: I12cb5ea0bef2f146cf237c7a3cc9293a600d736b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2902 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Mon Mar 25 22:30:54 2013, giving +1 See http://review.coreboot.org/2902 for details. -gerrit

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New patch to review for coreboot: d138570 libpayload: Fix type issues
by Stefan Reinauer 25 Mar '13

25 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2903 -gerrit commit d13857079b8c16ed988b8b127388513a553b6fa7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 25 15:03:41 2013 -0700 libpayload: Fix type issues There were a number of type issues in libpayload that sneaked in with the latest set of patches. - size_t and ssize_t were conflicting with gcc builtins - some stdint types were used in libpayload but not defined in our stdint.h With this patch it's possible to compile libpayload with the reference toolchain again. Change-Id: Idd5ccfdd9f3536b36bceca2d101e7405883b10bc Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/include/armv7/arch/types.h | 4 ++-- payloads/libpayload/include/stdint.h | 24 ++++++++++++++++++++++++ payloads/libpayload/include/x86/arch/types.h | 4 ++-- 3 files changed, 28 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/include/armv7/arch/types.h b/payloads/libpayload/include/armv7/arch/types.h index d6f4aa8..bb40257 100644 --- a/payloads/libpayload/include/armv7/arch/types.h +++ b/payloads/libpayload/include/armv7/arch/types.h @@ -53,8 +53,8 @@ typedef signed long long s64; typedef long time_t; typedef long suseconds_t; -typedef unsigned int size_t; -typedef int ssize_t; +typedef unsigned long size_t; +typedef long ssize_t; #ifndef NULL #define NULL ((void *)0) diff --git a/payloads/libpayload/include/stdint.h b/payloads/libpayload/include/stdint.h index dd7439d..1f0657b 100644 --- a/payloads/libpayload/include/stdint.h +++ b/payloads/libpayload/include/stdint.h @@ -29,8 +29,32 @@ #ifndef __STDINT_H #define __STDINT_H + +#if defined(__GNUC__) +#define __HAVE_LONG_LONG__ 1 +#else +#define __HAVE_LONG_LONG__ 0 +#endif + #include <arch/types.h> +/* Largest integral types */ +#if __HAVE_LONG_LONG__ +typedef long long int intmax_t; +typedef unsigned long long uintmax_t; +#else +typedef long int intmax_t; +typedef unsigned long int uintmax_t; +#endif + typedef unsigned long uintptr_t; typedef long intptr_t; + +#ifndef UINT32_MAX +#define UINT32_MAX (4294967295U) +#endif +#ifndef UINT64_MAX +# define UINT64_MAX (18446744073709551615ULL) +#endif + #endif diff --git a/payloads/libpayload/include/x86/arch/types.h b/payloads/libpayload/include/x86/arch/types.h index d6f4aa8..bb40257 100644 --- a/payloads/libpayload/include/x86/arch/types.h +++ b/payloads/libpayload/include/x86/arch/types.h @@ -53,8 +53,8 @@ typedef signed long long s64; typedef long time_t; typedef long suseconds_t; -typedef unsigned int size_t; -typedef int ssize_t; +typedef unsigned long size_t; +typedef long ssize_t; #ifndef NULL #define NULL ((void *)0)

1 0

Patch merged into coreboot/master: 3926b4c AMD Inagua: add GEC firmware, document Broadcom BCM57xx Selfboot Patch format
by gerrit＠coreboot.org 25 Mar '13

25 Mar '13

the following patch was just integrated into master: commit 3926b4c520e74da9dc22e3d136a8a178483e0d25 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Fri Mar 1 19:41:41 2013 +0100 AMD Inagua: add GEC firmware, document Broadcom BCM57xx Selfboot Patch format The Broadcom BCM5785 GbE MAC integrated in the AMD Hudson-E1 requires a secret sauce firmware blob to work. As Broadcom wasn't willing to send us any documentation (or a firmware adapted to our Micrel PHY) I had to figure out everything by myself in many weeks of hard detective work. In the end we had to settle for a different solution, the modified firmware I devised for the Micrel KSZ9021 PHY on our early FrontRunner-AF prototypes is no longer needed for the production version. However the information contained here might be very useful for others who'd like to use a competing PHY instead of Broadcom's 50610, so it should not get lost. And of course the unmodified, but now in large parts documented Selfboot Patch is needed to get Ethernet on AMD Inagua. The code introduced here should make the Hudson's internal MAC usable without having to add the proprietary firmware blob. - At least in theory. Unfortunately we've been unable to actually test this patch on Inagua, therefore the broadcom_init() call in mainboard.c was left commented out. If you have the hardware and can confirm it works please enable it. The fun thing is: as Broadcom refused to do any business with us at all, or send us any documentation, we never had to sign an NDA with them. This leaves me free to publish everything I have found out. :-) Change-Id: I94868250591862b376049c76bd21cb7e85f82569 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 19 19:02:00 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 25 22:42:01 2013, giving +2 See http://review.coreboot.org/2831 for details. -gerrit

1 0

Patch set updated for coreboot: 8182722 armv7: add new dcache and MMU setup functions
by David Hendricks 25 Mar '13

25 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2877 -gerrit commit 8182722f84d5495394b9e11c9d5f033d9add62ab Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 21 21:58:50 2013 -0700 armv7: add new dcache and MMU setup functions This adds new MMU setup code. Most notably, this version uses cbmem_add() to determine the translation table base address, which in turn is necessary to ensure payloads which wipe memory can tell which regions to wipe out. TODOs: - Finish cleaning up references to old cache/MMU stuff - Add L2 setup (from exynos_cache.c) - Set up ranges dynamically rather than in ramstage's main(). Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock_simple.c | 6 +- src/arch/armv7/include/arch/cache.h | 46 ++++- src/arch/armv7/include/system.h | 83 --------- src/arch/armv7/lib/Makefile.inc | 7 +- src/arch/armv7/lib/cache-cp15.c | 221 ----------------------- src/arch/armv7/lib/cache.c | 29 ++- src/arch/armv7/lib/cache_v7.c | 339 ----------------------------------- src/arch/armv7/lib/mmu.c | 132 ++++++++++++++ src/mainboard/google/snow/ramstage.c | 28 ++- src/mainboard/google/snow/romstage.c | 3 - 10 files changed, 226 insertions(+), 668 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index ad25b41..f6134f7 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -53,12 +53,14 @@ void main(void) armv7_invalidate_caches(); /* - * Re-enable caches and branch prediction. MMU will be set up later. + * Re-enable icache and branch prediction. MMU and dcache will be + * set up later. + * * Note: If booting from USB, we need to disable branch prediction * before copying from USB into RAM (FIXME: why?) */ sctlr = read_sctlr(); - sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I; + sctlr |= SCTLR_Z | SCTLR_I; write_sctlr(sctlr); if (boot_cpu()) { diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index c003256..92c0f2b 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -108,6 +108,32 @@ static inline void tlbiall(void) asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); } +/* write data access control register (DACR) */ +static inline void write_dacr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val)); +} + +/* write translation table base register 0 (TTBR0) */ +static inline void write_ttbr0(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory"); +} + +/* read translation table base control register (TTBCR) */ +static inline uint32_t read_ttbcr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val)); + return val; +} + +/* write translation table base control register (TTBCR) */ +static inline void write_ttbcr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory"); +} + /* * Low-level cache maintenance operations */ @@ -224,6 +250,12 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* dcache and MMU disable */ +void dcache_mmu_disable(void); + +/* dcache and MMU enable */ +void dcache_mmu_enable(void); + /* icache invalidate all (on current level given by CSSELR) */ void icache_invalidate_all(void); @@ -237,7 +269,17 @@ void tlb_invalidate_all(void); /* invalidate all caches on ARMv7 */ void armv7_invalidate_caches(void); -/* MMU setup by modified virtual address */ -void mmu_setup_by_mva(unsigned long start, unsigned long size); +/* mmu initialization (set page table address, set permissions, etc) */ +void mmu_init(void); + +enum dcache_policy { + DCACHE_OFF, + DCACHE_WRITEBACK, + DCACHE_WRITETHROUGH, +}; + +/* mmu range configuration (set dcache policy) */ +void mmu_config_range(unsigned long start_mb, unsigned long size_mb, + enum dcache_policy policy); #endif /* ARMV7_CACHE_H */ diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index eda0bc1..0643852 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -3,37 +3,6 @@ #define SYSTEM_H_ /* - * CR1 bits (CP#15 CR1) - */ -#define CR_M (1 << 0) /* MMU enable */ -#define CR_A (1 << 1) /* Alignment abort enable */ -#define CR_C (1 << 2) /* Dcache enable */ -#define CR_W (1 << 3) /* Write buffer enable */ -#define CR_P (1 << 4) /* 32-bit exception handler */ -#define CR_D (1 << 5) /* 32-bit data address range */ -#define CR_L (1 << 6) /* Implementation defined */ -#define CR_B (1 << 7) /* Big endian */ -#define CR_S (1 << 8) /* System MMU protection */ -#define CR_R (1 << 9) /* ROM MMU protection */ -#define CR_F (1 << 10) /* Implementation defined */ -#define CR_Z (1 << 11) /* Implementation defined */ -#define CR_I (1 << 12) /* Icache enable */ -#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ -#define CR_RR (1 << 14) /* Round Robin cache replacement */ -#define CR_L4 (1 << 15) /* LDR pc can set T bit */ -#define CR_DT (1 << 16) -#define CR_IT (1 << 18) -#define CR_ST (1 << 19) -#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ -#define CR_U (1 << 22) /* Unaligned access operation */ -#define CR_XP (1 << 23) /* Extended page tables */ -#define CR_VE (1 << 24) /* Vectored interrupts */ -#define CR_EE (1 << 25) /* Exception (Big) Endian */ -#define CR_TRE (1 << 28) /* TEX remap enable */ -#define CR_AFE (1 << 29) /* Access flag enable */ -#define CR_TE (1 << 30) /* Thumb exception enable */ - -/* * This is used to ensure the compiler did actually allocate the register we * asked it for some inline assembly sequences. Apparently we can't trust * the compiler from one version to another so a bit of paranoia won't hurt. @@ -48,58 +17,6 @@ #define arch_align_stack(x) (x) #ifndef __ASSEMBLER__ -#include <arch/cache.h> /* for isb() */ -static inline unsigned int get_cr(void) -{ - unsigned int val; - asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); - return val; -} - -static inline void set_cr(unsigned int val) -{ - asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" - : : "r" (val) : "cc"); - isb(); -} - -/* options available for data cache on each page */ -enum dcache_option { - DCACHE_OFF, - DCACHE_WRITETHROUGH, - DCACHE_WRITEBACK, -}; - -/* Size of an MMU section */ -enum { - MMU_SECTION_SHIFT = 20, - MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, -}; - -/** - * Change the cache settings for a region. - * - * \param start start address of memory region to change - * \param size size of memory region to change - * \param option dcache option to select - */ -void mmu_set_region_dcache(unsigned long start, int size, - enum dcache_option option); - -/** - * Register an update to the page tables, and flush the TLB - * - * \param start start address of update in page table - * \param stop stop address of update in page table - */ -void mmu_page_table_flush(unsigned long start, unsigned long stop); - -void mmu_setup(unsigned long start, unsigned long size); - -void v7_inval_tlb(void); - -void arm_init_before_mmu(void); - /* * FIXME: sdelay originally came from arch/arm/cpu/armv7/exynos5/setup.h in * u-boot but does not seem specific to exynos5... diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index c248b9e..56a1bb7 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -3,12 +3,8 @@ bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c bootblock-y += cache.c -bootblock-y += cache_v7.c -bootblock-y += cache-cp15.c romstage-y += cache.c -romstage-y += cache_v7.c -romstage-y += cache-cp15.c romstage-y += div0.c romstage-y += syslib.c romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c @@ -19,8 +15,7 @@ ramstage-y += div0.c #ramstage-y += memset.S ramstage-y += syslib.c ramstage-y += cache.c -ramstage-y += cache_v7.c -ramstage-y += cache-cp15.c +ramstage-y += mmu.c #FIXME(dhendrix): should this be a config option? romstage-y += eabi_compat.c diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c deleted file mode 100644 index 32f3c79..0000000 --- a/src/arch/armv7/lib/cache-cp15.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <stdlib.h> -#include <system.h> - -static unsigned int tlb_addr; - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++) - nop(); - asm volatile("" : : : "memory"); -} - -static void set_section_dcache(int section, enum dcache_option option) -{ - u32 value = section << MMU_SECTION_SHIFT | (3 << 10); - u32 *page_table; - unsigned int tlb_size = 4096 * 4; - - /* - * FIXME(dhendrix): This calculation is from arch/arm/lib/board.c - * in u-boot. We may need to subtract more due to logging. - * FIXME(rminnich) - * The cast avoids an incorrect overflow diagnostic. - * We really need to start adding ULL to constants that are - * intrinsically unsigned. - */ - tlb_addr = ((u32)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20UL)); - tlb_addr -= tlb_size; - /* round down to next 64KB limit */ - tlb_addr &= ~(0x10000 - 1); - page_table = (u32 *)tlb_addr; - - switch (option) { - case DCACHE_WRITETHROUGH: - value |= 0x1a; - break; - - case DCACHE_WRITEBACK: - value |= 0x1e; - break; - - case DCACHE_OFF: - value |= 0x12; - break; - } - - page_table[section] = value; -} - -#if 0 -void __mmu_page_table_flush(unsigned long start, unsigned long stop) -{ - debug("%s: Warning: not implemented\n", __func__); -} -#endif - -void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option option) -{ - u32 *page_table = &tlb_addr; - u32 upto, end; - - end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; - start = start >> MMU_SECTION_SHIFT; - debug("mmu_set_region_dcache start=%x, size=%x, option=%d\n", - start, size, option); - for (upto = start; upto < end; upto++) - set_section_dcache(upto, option); - mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); -} - -/** - * dram_bank_mmu_set - set up the data cache policy for a given dram bank - * - * @start: virtual address start of bank - * @size: size of bank (in bytes) - */ -static inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) -{ - int i; - - debug("%s: bank: %d\n", __func__, bank); - for (i = start >> 20; i < (start + size) >> 20; i++) { -#if defined(CONFIG_ARM_DCACHE_POLICY_WRITEBACK) - set_section_dcache(i, DCACHE_WRITEBACK); -#elif defined(CONFIG_ARM_DCACHE_POLICY_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#else -#error "Must define dcache policy." -#endif - } -} - -/* to activate the MMU we need to set up virtual memory: use 1M areas */ -inline void mmu_setup(unsigned long start, unsigned long size_mb) -{ - int i; - u32 reg; - -// arm_init_before_mmu(); - /* Set up an identity-mapping for all 4GB, rw for everyone */ - for (i = 0; i < 4096; i++) - set_section_dcache(i, DCACHE_OFF); - - dram_bank_mmu_setup(start, size_mb << 20); - - /* Copy the page table address to cp15 */ - asm volatile("mcr p15, 0, %0, c2, c0, 0" - : : "r" (tlb_addr) : "memory"); - /* Set the access control to all-supervisor */ - asm volatile("mcr p15, 0, %0, c3, c0, 0" - : : "r" (~0)); - /* and enable the mmu */ - reg = get_cr(); /* get control reg. */ - cp_delay(); - set_cr(reg | CR_M); -} - -static int mmu_enabled(void) -{ - return get_cr() & CR_M; -} - -/* cache_bit must be either CR_I or CR_C */ -static void cache_enable(unsigned long start, unsigned long size, uint32_t cache_bit) -{ - uint32_t reg; - - /* The data cache is not active unless the mmu is enabled too */ - if ((cache_bit == CR_C) && !mmu_enabled()) - mmu_setup(start, size); - reg = get_cr(); /* get control reg. */ - cp_delay(); - set_cr(reg | cache_bit); -} - -/* - * Big hack warning! - * - * Devs like to compile with -O0 to get a nice debugging illusion. But this - * function does not survive that since -O0 causes the compiler to read the - * PC back from the stack after the dcache flush. Might it be possible to fix - * this by flushing the write buffer? - */ -static void cache_disable(uint32_t cache_bit) __attribute__ ((optimize(2))); - -/* cache_bit must be either CR_I or CR_C */ -static void cache_disable(uint32_t cache_bit) -{ - uint32_t reg; - - if (cache_bit == CR_C) { - /* if cache isn;t enabled no need to disable */ - reg = get_cr(); - if ((reg & CR_C) != CR_C) - return; - /* if disabling data cache, disable mmu too */ - cache_bit |= CR_M; - } - reg = get_cr(); - cp_delay(); - if (cache_bit == (CR_C | CR_M)) - flush_dcache_all(); - set_cr(reg & ~cache_bit); -} - -void icache_enable(unsigned long start, unsigned long size) -{ - cache_enable(start, size, CR_I); -} - -void icache_disable(void) -{ - cache_disable(CR_I); -} - -int icache_status(void) -{ - return (get_cr() & CR_I) != 0; -} - -void dcache_enable(unsigned long start, unsigned long size) -{ - cache_enable(start, size, CR_C); -} - -void dcache_disable(void) -{ - cache_disable(CR_C); -} - -int dcache_status(void) -{ - return (get_cr() & CR_C) != 0; -} diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 63e406c..2686db7 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -204,6 +204,28 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) dcache_op_mva(addr, len, OP_DCCIMVAC); } + +void dcache_mmu_disable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr &= ~(SCTLR_C | SCTLR_M); + write_sctlr(sctlr); +} + + +void dcache_mmu_enable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr |= SCTLR_C | SCTLR_M; + write_sctlr(sctlr); +} + void armv7_invalidate_caches(void) { uint32_t clidr; @@ -252,10 +274,3 @@ void armv7_invalidate_caches(void) /* Invalidate TLB */ tlb_invalidate_all(); } - -/* FIXME: wrapper around imported mmu_setup() for now */ -extern void mmu_setup(unsigned long start, unsigned long size); -void mmu_setup_by_mva(unsigned long start, unsigned long size) -{ - mmu_setup(start, size); -} diff --git a/src/arch/armv7/lib/cache_v7.c b/src/arch/armv7/lib/cache_v7.c deleted file mode 100644 index 1764351..0000000 --- a/src/arch/armv7/lib/cache_v7.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh(a)ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <armv7.h> -#include <common.h> -#include <system.h> -#include <utils.h> -#include <console/console.h> - -#define ARMV7_DCACHE_INVAL_ALL 1 -#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2 -#define ARMV7_DCACHE_INVAL_RANGE 3 -#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 - -/* - * Write the level and type you want to Cache Size Selection Register(CSSELR) - * to get size details from Current Cache Size ID Register(CCSIDR) - */ -static void set_csselr(u32 level, u32 type) -{ u32 csselr = level << 1 | type; - - /* Write to Cache Size Selection Register(CSSELR) */ - asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); -} - -static u32 get_ccsidr(void) -{ - u32 ccsidr; - - /* Read current CP15 Cache Size ID Register */ - asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr)); - return ccsidr; -} - -static u32 get_clidr(void) -{ - u32 clidr; - - /* Read current CP15 Cache Level ID Register */ - asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr)); - return clidr; -} - -static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, - u32 num_ways, u32 way_shift, - u32 log2_line_len) -{ - int way, set, setway; - - /* - * For optimal assembly code: - * a. count down - * b. have bigger loop inside - */ - for (way = num_ways - 1; way >= 0 ; way--) { - for (set = num_sets - 1; set >= 0; set--) { - setway = (level << 1) | (set << log2_line_len) | - (way << way_shift); - /* Invalidate data/unified cache line by set/way */ - asm volatile (" mcr p15, 0, %0, c7, c6, 2" - : : "r" (setway)); - } - } - /* DSB to make sure the operation is complete */ - CP15DSB; -} - -static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, - u32 num_ways, u32 way_shift, - u32 log2_line_len) -{ - int way, set, setway; - - /* - * For optimal assembly code: - * a. count down - * b. have bigger loop inside - */ - for (way = num_ways - 1; way >= 0 ; way--) { - for (set = num_sets - 1; set >= 0; set--) { - setway = (level << 1) | (set << log2_line_len) | - (way << way_shift); - /* - * Clean & Invalidate data/unified - * cache line by set/way - */ - asm volatile (" mcr p15, 0, %0, c7, c14, 2" - : : "r" (setway)); - } - } - /* DSB to make sure the operation is complete */ - CP15DSB; -} - -static void v7_maint_dcache_level_setway(u32 level, u32 operation) -{ - u32 ccsidr; - u32 num_sets, num_ways, log2_line_len, log2_num_ways; - u32 way_shift; - - set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED); - - ccsidr = get_ccsidr(); - - log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> - CCSIDR_LINE_SIZE_OFFSET) + 2; - /* Converting from words to bytes */ - log2_line_len += 2; - - num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >> - CCSIDR_ASSOCIATIVITY_OFFSET) + 1; - num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >> - CCSIDR_NUM_SETS_OFFSET) + 1; - /* - * According to ARMv7 ARM number of sets and number of ways need - * not be a power of 2 - */ - log2_num_ways = log_2_n_round_up(num_ways); - - way_shift = (32 - log2_num_ways); - if (operation == ARMV7_DCACHE_INVAL_ALL) { - v7_inval_dcache_level_setway(level, num_sets, num_ways, - way_shift, log2_line_len); - } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) { - v7_clean_inval_dcache_level_setway(level, num_sets, num_ways, - way_shift, log2_line_len); - } -} - -static void v7_maint_dcache_all(u32 operation) -{ - u32 level, cache_type, level_start_bit = 0; - - u32 clidr = get_clidr(); - - for (level = 0; level < 7; level++) { - cache_type = (clidr >> level_start_bit) & 0x7; - if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) || - (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) || - (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED)) - v7_maint_dcache_level_setway(level, operation); - level_start_bit += 3; - } -} - -static void v7_dcache_clean_inval_range(u32 start, - u32 stop, u32 line_len) -{ - u32 mva; - - /* Align start to cache line boundary */ - start &= ~(line_len - 1); - for (mva = start; mva < stop; mva = mva + line_len) { - /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */ - asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva)); - } -} - -static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) -{ - u32 mva; - - /* - * If start address is not aligned to cache-line do not - * invalidate the first cache-line - */ - if (start & (line_len - 1)) { - printk(BIOS_ERR, "%s - start address is not aligned - 0x%08x\n", - __func__, start); - /* move to next cache line */ - start = (start + line_len - 1) & ~(line_len - 1); - } - - /* - * If stop address is not aligned to cache-line do not - * invalidate the last cache-line - */ - if (stop & (line_len - 1)) { - printk(BIOS_ERR, "%s - stop address is not aligned - 0x%08x\n", - __func__, stop); - /* align to the beginning of this cache line */ - stop &= ~(line_len - 1); - } - - for (mva = start; mva < stop; mva = mva + line_len) { - /* DCIMVAC - Invalidate data cache by MVA to PoC */ - asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva)); - } -} - -static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) -{ - u32 line_len = dcache_get_line_size(); - - switch (range_op) { - case ARMV7_DCACHE_CLEAN_INVAL_RANGE: - v7_dcache_clean_inval_range(start, stop, line_len); - break; - case ARMV7_DCACHE_INVAL_RANGE: - v7_dcache_inval_range(start, stop, line_len); - break; - } - - /* DSB to make sure the operation is complete */ - CP15DSB; -} - -/* Invalidate TLB */ -void v7_inval_tlb(void) -{ - /* Invalidate entire unified TLB */ - asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); - /* Invalidate entire data TLB */ - asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); - /* Invalidate entire instruction TLB */ - asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); - /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; - /* Full system ISB - make sure the instruction stream sees it */ - CP15ISB; -} - -unsigned long dcache_get_line_size(void) -{ - u32 line_len, ccsidr; - - ccsidr = get_ccsidr(); - line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> - CCSIDR_LINE_SIZE_OFFSET) + 2; - /* Converting from words to bytes */ - line_len += 2; - /* converting from log2(linelen) to linelen */ - line_len = 1 << line_len; - - return line_len; -} - -void invalidate_dcache_all(void) -{ - v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); - - v7_outer_cache_inval_all(); -} - -/* - * Performs a clean & invalidation of the entire data cache - * at all levels - */ -void flush_dcache_all(void) -{ - v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL); - - v7_outer_cache_flush_all(); -} - -/* - * Invalidates range in all levels of D-cache/unified cache used: - * Affects the range [start, stop - 1] - */ -void invalidate_dcache_range(unsigned long start, unsigned long stop) -{ - - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); - - v7_outer_cache_inval_range(start, stop); -} - -/* - * Flush range(clean & invalidate) from all levels of D-cache/unified - * cache used: - * Affects the range [start, stop - 1] - */ -void flush_dcache_range(unsigned long start, unsigned long stop) -{ - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); - - v7_outer_cache_flush_range(start, stop); -} - -void arm_init_before_mmu(void) -{ - v7_outer_cache_enable(); - invalidate_dcache_all(); - v7_inval_tlb(); -} - -void mmu_page_table_flush(unsigned long start, unsigned long stop) -{ - flush_dcache_range(start, stop); - v7_inval_tlb(); -} - -/* - * Flush range from all levels of d-cache/unified-cache used: - * Affects the range [start, start + size - 1] - */ -void flush_cache(unsigned long start, unsigned long size) -{ - flush_dcache_range(start, start + size); -} - -/* Invalidate entire I-cache and branch predictor array */ -void invalidate_icache_all(void) -{ - /* - * Invalidate all instruction caches to PoU. - * Also flushes branch target cache. - */ - asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); - - /* Invalidate entire branch predictor array */ - asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); - - /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; - - /* ISB - make sure the instruction stream sees it */ - CP15ISB; -} diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c new file mode 100644 index 0000000..34a484f --- /dev/null +++ b/src/arch/armv7/lib/mmu.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <stdlib.h> +#include <types.h> + +#include <cbmem.h> +#include <console/console.h> + +#include <arch/cache.h> + +#define L1_TLB_ENTRIES 4096 /* 1 entry for each 1MB address space */ + +static uintptr_t ttb_addr; + +void mmu_config_range(unsigned long start_mb, unsigned long size_mb, + enum dcache_policy policy) +{ + unsigned int i; + uint32_t attr; + uint32_t *ttb_entry = (uint32_t *)ttb_addr; + const char *str = NULL; + + /* + * Section entry bits: + * 31:20 - section base address + * 18 - 0 to indicate normal section (versus supersection) + * 17 - nG, 0 to indicate page is global + * 16 - S, 0 for non-shareable (?) + * 15 - APX, 0 for full access + * 14:12 - TEX, 0b000 for outer and inner write-back + * 11:10 - AP, 0b11 for full access + * 9 - P, ? (FIXME: not described or possibly obsolete?) + * 8: 5 - Domain + * 4 - XN, 1 to set execute-never (and also avoid prefetches) + * 3 - C, 1 for cacheable + * 2 - B, 1 for bufferable + * 1: 0 - 0b10 to indicate section entry + */ + + switch(policy) { + case DCACHE_OFF: + /* XN set to avoid prefetches to uncached/unbuffered regions */ + attr = (0x3 << 10) | (1 << 4) | 0x2; + str = "off"; + break; + case DCACHE_WRITEBACK: + attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2; + str = "writeback"; + break; + case DCACHE_WRITETHROUGH: + attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2; + str = "writethrough"; + break; + default: + printk(BIOS_ERR, "unknown dcache policy: %02x\n", policy); + return; + } + + printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n", + start_mb << 20, ((start_mb + size_mb) << 20) - 1, str); + + for (i = start_mb; i < start_mb + size_mb; i++) + ttb_entry[i] = (i << 20) | attr; +} + +void mmu_init(void) +{ + unsigned int ttb_size; + uint32_t ttbcr; + + /* + * For coreboot's purposes, we will create a simple L1 page table + * in RAM with 1MB section translation entries over the 4GB address + * space. + * (ref: section 10.2 and example 15-4 in Cortex-A series + * programmer's guide) + * + * FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to + * 512 bytes. So add double the space in cbmem and fix-up the pointer. + */ + ttb_size = L1_TLB_ENTRIES * sizeof(unsigned long); + ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size * 2); + ttb_addr = ALIGN(ttb_addr + ttb_size, ttb_size); + printk(BIOS_DEBUG, "Translation table is @ 0x%08x\n", ttb_addr); + + /* + * Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0 + * table size is 16KB and has indices VA[31:20]. + * + * ref: Arch Ref. Manual for ARMv7-A, B3.5.4, + */ + ttbcr = read_ttbcr(); + ttbcr &= ~(0x3); + write_ttbcr(ttbcr); + + /* + * Translation table base 0 address is in bits 31:14-N, where N is given + * by bits 2:0 in TTBCR (which we set to 0). All lower bits in this + * register should be zero for coreboot. + */ + write_ttbr0(ttb_addr); + + /* disable domain-level checking of permissions */ + write_dacr(~0); +} diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index be5216f..1751a1b 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -23,19 +23,37 @@ #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/power.h> +#include <arch/cache.h> + +/* convenient shorthand (in MB) */ +#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) +#define DRAM_SIZE CONFIG_DRAM_SIZE_MB +#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ + void hardwaremain(int boot_complete); void main(void) { console_init(); printk(BIOS_INFO, "hello from ramstage; now with deluxe exception handling.\n"); - /* this is going to move, but we must have it now and we're not sure where */ - exception_init(); - /* place at top of physical memory */ + /* set up coreboot tables */ high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((CONFIG_DRAM_SIZE_MB << 20UL) * CONFIG_NR_DRAM_BANKS) - - CONFIG_COREBOOT_TABLES_SIZE; + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + cbmem_init(high_tables_base, high_tables_size); + + /* set up dcache and MMU */ + /* FIXME: this should happen via resource allocator */ + mmu_init(); + mmu_config_range(0, DRAM_START, DCACHE_OFF); + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + dcache_invalidate_all(); + dcache_mmu_enable(); + + /* this is going to move, but we must have it now and we're not sure where */ + exception_init(); const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index bfb4156..39069b2 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -113,9 +113,6 @@ void main(void) while(1); } - /* Set up MMU and caches */ - mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); - initialize_s5p_mshc(); graphics();

1 0

New patch to review for coreboot: 57918cd libpayload: Fix Config.in warning
by Stefan Reinauer 25 Mar '13

25 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2902 -gerrit commit 57918cdcd82dba69b6f251dc63ff7f20c29e4be8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 25 14:13:43 2013 -0700 libpayload: Fix Config.in warning PDcurses is already default. Hence drop the additional attempt that is not supported by Kconfig. Config.in:123:warning: defaults for choice values not supported Change-Id: I12cb5ea0bef2f146cf237c7a3cc9293a600d736b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/Config.in | 1 - 1 file changed, 1 deletion(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 377b7ba..9d083ea 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -120,7 +120,6 @@ config TINYCURSES config PDCURSES bool "PDCurses" - default y help libpayload's PDCurses port provides a full features curses implementation, including libpanel, libmenu and libform (which

1 0

Patch set updated for coreboot: a32ee09 armv7: add new dcache and MMU setup functions
by David Hendricks 25 Mar '13

25 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2877 -gerrit commit a32ee09d68bf6282e497edc2ecdf0d38140ffefc Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 21 21:58:50 2013 -0700 armv7: add new dcache and MMU setup functions ** do not submit ** This is a work-in-progress patch. This adds new MMU setup code which uses cbmem_add() to determine the translation table base address, which in turn helps our payload to avoid clobbering the page table. Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock_simple.c | 4 +- src/arch/armv7/include/arch/cache.h | 46 ++++- src/arch/armv7/include/system.h | 2 + src/arch/armv7/lib/Makefile.inc | 7 +- src/arch/armv7/lib/cache-cp15.c | 221 ----------------------- src/arch/armv7/lib/cache.c | 29 ++- src/arch/armv7/lib/cache_v7.c | 339 ----------------------------------- src/arch/armv7/lib/mmu.c | 135 ++++++++++++++ src/lib/Makefile.inc | 2 +- src/lib/cbmem.c | 13 ++ src/mainboard/google/snow/ramstage.c | 28 ++- src/mainboard/google/snow/romstage.c | 10 +- 12 files changed, 251 insertions(+), 585 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index ad25b41..c01335c 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -53,7 +53,9 @@ void main(void) armv7_invalidate_caches(); /* - * Re-enable caches and branch prediction. MMU will be set up later. + * Re-enable icache and branch prediction. MMU and dcache will be + * set up later. + * * Note: If booting from USB, we need to disable branch prediction * before copying from USB into RAM (FIXME: why?) */ diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index c003256..6d06b47 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -108,6 +108,32 @@ static inline void tlbiall(void) asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); } +/* write data access control register (DACR) */ +static inline void write_dacr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val)); +} + +/* write translation table base register 0 (TTBR0) */ +static inline void write_ttbr0(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory"); +} + +/* read translation table base control register (TTBCR) */ +static inline uint32_t read_ttbcr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val)); + return val; +} + +/* write translation table base control register (TTBCR) */ +static inline void write_ttbcr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory"); +} + /* * Low-level cache maintenance operations */ @@ -224,6 +250,12 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* dcache and MMU disable */ +void dcache_mmu_disable(void); + +/* dcache and MMU enable */ +void dcache_mmu_enable(void); + /* icache invalidate all (on current level given by CSSELR) */ void icache_invalidate_all(void); @@ -237,7 +269,17 @@ void tlb_invalidate_all(void); /* invalidate all caches on ARMv7 */ void armv7_invalidate_caches(void); -/* MMU setup by modified virtual address */ -void mmu_setup_by_mva(unsigned long start, unsigned long size); +enum dcache_policy { + DCACHE_OFF, + DCACHE_WRITEBACK, + DCACHE_WRITETHROUGH, +}; + +/* mmu initialization (set page table address, set permissions, etc) */ +void mmu_init(void); + +/* mmu range configuration (set dcache policy) */ +void mmu_config_range(unsigned long start_mb, unsigned long size_mb, + enum dcache_policy policy); #endif /* ARMV7_CACHE_H */ diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index eda0bc1..786af5b 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -64,6 +64,7 @@ static inline void set_cr(unsigned int val) } /* options available for data cache on each page */ +#if 0 enum dcache_option { DCACHE_OFF, DCACHE_WRITETHROUGH, @@ -99,6 +100,7 @@ void mmu_setup(unsigned long start, unsigned long size); void v7_inval_tlb(void); void arm_init_before_mmu(void); +#endif /* * FIXME: sdelay originally came from arch/arm/cpu/armv7/exynos5/setup.h in diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index c248b9e..56a1bb7 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -3,12 +3,8 @@ bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c bootblock-y += cache.c -bootblock-y += cache_v7.c -bootblock-y += cache-cp15.c romstage-y += cache.c -romstage-y += cache_v7.c -romstage-y += cache-cp15.c romstage-y += div0.c romstage-y += syslib.c romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c @@ -19,8 +15,7 @@ ramstage-y += div0.c #ramstage-y += memset.S ramstage-y += syslib.c ramstage-y += cache.c -ramstage-y += cache_v7.c -ramstage-y += cache-cp15.c +ramstage-y += mmu.c #FIXME(dhendrix): should this be a config option? romstage-y += eabi_compat.c diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c deleted file mode 100644 index 32f3c79..0000000 --- a/src/arch/armv7/lib/cache-cp15.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <stdlib.h> -#include <system.h> - -static unsigned int tlb_addr; - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++) - nop(); - asm volatile("" : : : "memory"); -} - -static void set_section_dcache(int section, enum dcache_option option) -{ - u32 value = section << MMU_SECTION_SHIFT | (3 << 10); - u32 *page_table; - unsigned int tlb_size = 4096 * 4; - - /* - * FIXME(dhendrix): This calculation is from arch/arm/lib/board.c - * in u-boot. We may need to subtract more due to logging. - * FIXME(rminnich) - * The cast avoids an incorrect overflow diagnostic. - * We really need to start adding ULL to constants that are - * intrinsically unsigned. - */ - tlb_addr = ((u32)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20UL)); - tlb_addr -= tlb_size; - /* round down to next 64KB limit */ - tlb_addr &= ~(0x10000 - 1); - page_table = (u32 *)tlb_addr; - - switch (option) { - case DCACHE_WRITETHROUGH: - value |= 0x1a; - break; - - case DCACHE_WRITEBACK: - value |= 0x1e; - break; - - case DCACHE_OFF: - value |= 0x12; - break; - } - - page_table[section] = value; -} - -#if 0 -void __mmu_page_table_flush(unsigned long start, unsigned long stop) -{ - debug("%s: Warning: not implemented\n", __func__); -} -#endif - -void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option option) -{ - u32 *page_table = &tlb_addr; - u32 upto, end; - - end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; - start = start >> MMU_SECTION_SHIFT; - debug("mmu_set_region_dcache start=%x, size=%x, option=%d\n", - start, size, option); - for (upto = start; upto < end; upto++) - set_section_dcache(upto, option); - mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); -} - -/** - * dram_bank_mmu_set - set up the data cache policy for a given dram bank - * - * @start: virtual address start of bank - * @size: size of bank (in bytes) - */ -static inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) -{ - int i; - - debug("%s: bank: %d\n", __func__, bank); - for (i = start >> 20; i < (start + size) >> 20; i++) { -#if defined(CONFIG_ARM_DCACHE_POLICY_WRITEBACK) - set_section_dcache(i, DCACHE_WRITEBACK); -#elif defined(CONFIG_ARM_DCACHE_POLICY_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#else -#error "Must define dcache policy." -#endif - } -} - -/* to activate the MMU we need to set up virtual memory: use 1M areas */ -inline void mmu_setup(unsigned long start, unsigned long size_mb) -{ - int i; - u32 reg; - -// arm_init_before_mmu(); - /* Set up an identity-mapping for all 4GB, rw for everyone */ - for (i = 0; i < 4096; i++) - set_section_dcache(i, DCACHE_OFF); - - dram_bank_mmu_setup(start, size_mb << 20); - - /* Copy the page table address to cp15 */ - asm volatile("mcr p15, 0, %0, c2, c0, 0" - : : "r" (tlb_addr) : "memory"); - /* Set the access control to all-supervisor */ - asm volatile("mcr p15, 0, %0, c3, c0, 0" - : : "r" (~0)); - /* and enable the mmu */ - reg = get_cr(); /* get control reg. */ - cp_delay(); - set_cr(reg | CR_M); -} - -static int mmu_enabled(void) -{ - return get_cr() & CR_M; -} - -/* cache_bit must be either CR_I or CR_C */ -static void cache_enable(unsigned long start, unsigned long size, uint32_t cache_bit) -{ - uint32_t reg; - - /* The data cache is not active unless the mmu is enabled too */ - if ((cache_bit == CR_C) && !mmu_enabled()) - mmu_setup(start, size); - reg = get_cr(); /* get control reg. */ - cp_delay(); - set_cr(reg | cache_bit); -} - -/* - * Big hack warning! - * - * Devs like to compile with -O0 to get a nice debugging illusion. But this - * function does not survive that since -O0 causes the compiler to read the - * PC back from the stack after the dcache flush. Might it be possible to fix - * this by flushing the write buffer? - */ -static void cache_disable(uint32_t cache_bit) __attribute__ ((optimize(2))); - -/* cache_bit must be either CR_I or CR_C */ -static void cache_disable(uint32_t cache_bit) -{ - uint32_t reg; - - if (cache_bit == CR_C) { - /* if cache isn;t enabled no need to disable */ - reg = get_cr(); - if ((reg & CR_C) != CR_C) - return; - /* if disabling data cache, disable mmu too */ - cache_bit |= CR_M; - } - reg = get_cr(); - cp_delay(); - if (cache_bit == (CR_C | CR_M)) - flush_dcache_all(); - set_cr(reg & ~cache_bit); -} - -void icache_enable(unsigned long start, unsigned long size) -{ - cache_enable(start, size, CR_I); -} - -void icache_disable(void) -{ - cache_disable(CR_I); -} - -int icache_status(void) -{ - return (get_cr() & CR_I) != 0; -} - -void dcache_enable(unsigned long start, unsigned long size) -{ - cache_enable(start, size, CR_C); -} - -void dcache_disable(void) -{ - cache_disable(CR_C); -} - -int dcache_status(void) -{ - return (get_cr() & CR_C) != 0; -} diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 63e406c..2686db7 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -204,6 +204,28 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) dcache_op_mva(addr, len, OP_DCCIMVAC); } + +void dcache_mmu_disable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr &= ~(SCTLR_C | SCTLR_M); + write_sctlr(sctlr); +} + + +void dcache_mmu_enable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr |= SCTLR_C | SCTLR_M; + write_sctlr(sctlr); +} + void armv7_invalidate_caches(void) { uint32_t clidr; @@ -252,10 +274,3 @@ void armv7_invalidate_caches(void) /* Invalidate TLB */ tlb_invalidate_all(); } - -/* FIXME: wrapper around imported mmu_setup() for now */ -extern void mmu_setup(unsigned long start, unsigned long size); -void mmu_setup_by_mva(unsigned long start, unsigned long size) -{ - mmu_setup(start, size); -} diff --git a/src/arch/armv7/lib/cache_v7.c b/src/arch/armv7/lib/cache_v7.c deleted file mode 100644 index 1764351..0000000 --- a/src/arch/armv7/lib/cache_v7.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh(a)ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <armv7.h> -#include <common.h> -#include <system.h> -#include <utils.h> -#include <console/console.h> - -#define ARMV7_DCACHE_INVAL_ALL 1 -#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2 -#define ARMV7_DCACHE_INVAL_RANGE 3 -#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 - -/* - * Write the level and type you want to Cache Size Selection Register(CSSELR) - * to get size details from Current Cache Size ID Register(CCSIDR) - */ -static void set_csselr(u32 level, u32 type) -{ u32 csselr = level << 1 | type; - - /* Write to Cache Size Selection Register(CSSELR) */ - asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); -} - -static u32 get_ccsidr(void) -{ - u32 ccsidr; - - /* Read current CP15 Cache Size ID Register */ - asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr)); - return ccsidr; -} - -static u32 get_clidr(void) -{ - u32 clidr; - - /* Read current CP15 Cache Level ID Register */ - asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr)); - return clidr; -} - -static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, - u32 num_ways, u32 way_shift, - u32 log2_line_len) -{ - int way, set, setway; - - /* - * For optimal assembly code: - * a. count down - * b. have bigger loop inside - */ - for (way = num_ways - 1; way >= 0 ; way--) { - for (set = num_sets - 1; set >= 0; set--) { - setway = (level << 1) | (set << log2_line_len) | - (way << way_shift); - /* Invalidate data/unified cache line by set/way */ - asm volatile (" mcr p15, 0, %0, c7, c6, 2" - : : "r" (setway)); - } - } - /* DSB to make sure the operation is complete */ - CP15DSB; -} - -static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, - u32 num_ways, u32 way_shift, - u32 log2_line_len) -{ - int way, set, setway; - - /* - * For optimal assembly code: - * a. count down - * b. have bigger loop inside - */ - for (way = num_ways - 1; way >= 0 ; way--) { - for (set = num_sets - 1; set >= 0; set--) { - setway = (level << 1) | (set << log2_line_len) | - (way << way_shift); - /* - * Clean & Invalidate data/unified - * cache line by set/way - */ - asm volatile (" mcr p15, 0, %0, c7, c14, 2" - : : "r" (setway)); - } - } - /* DSB to make sure the operation is complete */ - CP15DSB; -} - -static void v7_maint_dcache_level_setway(u32 level, u32 operation) -{ - u32 ccsidr; - u32 num_sets, num_ways, log2_line_len, log2_num_ways; - u32 way_shift; - - set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED); - - ccsidr = get_ccsidr(); - - log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> - CCSIDR_LINE_SIZE_OFFSET) + 2; - /* Converting from words to bytes */ - log2_line_len += 2; - - num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >> - CCSIDR_ASSOCIATIVITY_OFFSET) + 1; - num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >> - CCSIDR_NUM_SETS_OFFSET) + 1; - /* - * According to ARMv7 ARM number of sets and number of ways need - * not be a power of 2 - */ - log2_num_ways = log_2_n_round_up(num_ways); - - way_shift = (32 - log2_num_ways); - if (operation == ARMV7_DCACHE_INVAL_ALL) { - v7_inval_dcache_level_setway(level, num_sets, num_ways, - way_shift, log2_line_len); - } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) { - v7_clean_inval_dcache_level_setway(level, num_sets, num_ways, - way_shift, log2_line_len); - } -} - -static void v7_maint_dcache_all(u32 operation) -{ - u32 level, cache_type, level_start_bit = 0; - - u32 clidr = get_clidr(); - - for (level = 0; level < 7; level++) { - cache_type = (clidr >> level_start_bit) & 0x7; - if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) || - (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) || - (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED)) - v7_maint_dcache_level_setway(level, operation); - level_start_bit += 3; - } -} - -static void v7_dcache_clean_inval_range(u32 start, - u32 stop, u32 line_len) -{ - u32 mva; - - /* Align start to cache line boundary */ - start &= ~(line_len - 1); - for (mva = start; mva < stop; mva = mva + line_len) { - /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */ - asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva)); - } -} - -static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) -{ - u32 mva; - - /* - * If start address is not aligned to cache-line do not - * invalidate the first cache-line - */ - if (start & (line_len - 1)) { - printk(BIOS_ERR, "%s - start address is not aligned - 0x%08x\n", - __func__, start); - /* move to next cache line */ - start = (start + line_len - 1) & ~(line_len - 1); - } - - /* - * If stop address is not aligned to cache-line do not - * invalidate the last cache-line - */ - if (stop & (line_len - 1)) { - printk(BIOS_ERR, "%s - stop address is not aligned - 0x%08x\n", - __func__, stop); - /* align to the beginning of this cache line */ - stop &= ~(line_len - 1); - } - - for (mva = start; mva < stop; mva = mva + line_len) { - /* DCIMVAC - Invalidate data cache by MVA to PoC */ - asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva)); - } -} - -static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) -{ - u32 line_len = dcache_get_line_size(); - - switch (range_op) { - case ARMV7_DCACHE_CLEAN_INVAL_RANGE: - v7_dcache_clean_inval_range(start, stop, line_len); - break; - case ARMV7_DCACHE_INVAL_RANGE: - v7_dcache_inval_range(start, stop, line_len); - break; - } - - /* DSB to make sure the operation is complete */ - CP15DSB; -} - -/* Invalidate TLB */ -void v7_inval_tlb(void) -{ - /* Invalidate entire unified TLB */ - asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); - /* Invalidate entire data TLB */ - asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); - /* Invalidate entire instruction TLB */ - asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); - /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; - /* Full system ISB - make sure the instruction stream sees it */ - CP15ISB; -} - -unsigned long dcache_get_line_size(void) -{ - u32 line_len, ccsidr; - - ccsidr = get_ccsidr(); - line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> - CCSIDR_LINE_SIZE_OFFSET) + 2; - /* Converting from words to bytes */ - line_len += 2; - /* converting from log2(linelen) to linelen */ - line_len = 1 << line_len; - - return line_len; -} - -void invalidate_dcache_all(void) -{ - v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); - - v7_outer_cache_inval_all(); -} - -/* - * Performs a clean & invalidation of the entire data cache - * at all levels - */ -void flush_dcache_all(void) -{ - v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL); - - v7_outer_cache_flush_all(); -} - -/* - * Invalidates range in all levels of D-cache/unified cache used: - * Affects the range [start, stop - 1] - */ -void invalidate_dcache_range(unsigned long start, unsigned long stop) -{ - - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); - - v7_outer_cache_inval_range(start, stop); -} - -/* - * Flush range(clean & invalidate) from all levels of D-cache/unified - * cache used: - * Affects the range [start, stop - 1] - */ -void flush_dcache_range(unsigned long start, unsigned long stop) -{ - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); - - v7_outer_cache_flush_range(start, stop); -} - -void arm_init_before_mmu(void) -{ - v7_outer_cache_enable(); - invalidate_dcache_all(); - v7_inval_tlb(); -} - -void mmu_page_table_flush(unsigned long start, unsigned long stop) -{ - flush_dcache_range(start, stop); - v7_inval_tlb(); -} - -/* - * Flush range from all levels of d-cache/unified-cache used: - * Affects the range [start, start + size - 1] - */ -void flush_cache(unsigned long start, unsigned long size) -{ - flush_dcache_range(start, start + size); -} - -/* Invalidate entire I-cache and branch predictor array */ -void invalidate_icache_all(void) -{ - /* - * Invalidate all instruction caches to PoU. - * Also flushes branch target cache. - */ - asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); - - /* Invalidate entire branch predictor array */ - asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); - - /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; - - /* ISB - make sure the instruction stream sees it */ - CP15ISB; -} diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c new file mode 100644 index 0000000..bf47268 --- /dev/null +++ b/src/arch/armv7/lib/mmu.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <stdlib.h> +#include <types.h> + +#include <cbmem.h> +#include <console/console.h> + +#include <arch/cache.h> + +#define L1_TLB_ENTRIES 4096 + +static uintptr_t ttb_addr; + +void mmu_config_range(unsigned long start_mb, unsigned long size_mb, + enum dcache_policy policy) +{ + unsigned int i; + uint32_t attr; + uint32_t *ttb_entry = (uint32_t *)ttb_addr; + const char *str = NULL; + + /* + * Section entry bits: + * 31:20 - section base address + * 18 - 0 to indicate normal section (versus supersection) + * 17 - nG, 0 to indicate page is global + * 16 - S, 0 for non-shareable (?) + * 15 - APX, 0 for full access + * 14:12 - TEX, 0b000 for outer and inner write-back + * 11:10 - AP, 0b11 for full access + * 9 - P, ? (FIXME: not described or possibly obsolete?) + * 8: 5 - Domain + * 4 - XN, 1 to set execute-never (and also avoid prefetches) + * 3 - C, 1 for cacheable + * 2 - B, 1 for bufferable + * 1: 0 - 0b10 to indicate section entry + */ + + switch(policy) { + case DCACHE_OFF: + /* XN set to avoid prefetches to uncached/unbuffered regions */ + attr = (0x3 << 10) | (1 << 4) | 0x2; + str = "off"; + break; + case DCACHE_WRITEBACK: + attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2; + str = "writeback"; + break; + case DCACHE_WRITETHROUGH: + attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2; + str = "writethrough"; + break; + default: + printk(BIOS_ERR, "unknown dcache policy: %02x\n", policy); + return; + } + + printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n", + start_mb << 20, ((start_mb + size_mb) << 20) - 1, str); + + for (i = start_mb; i < start_mb + size_mb; i++) + ttb_entry[i] = (i << 20) | attr; + + /* FIXME: remove this */ + printk(BIOS_DEBUG, "start_mb: %lx, size_mb: %lx, i: %x\n", start_mb, size_mb, i); +} + +void mmu_init(void) +{ + unsigned int ttb_size; + uint32_t ttbcr; + + /* + * For coreboot's purposes, we will create a simple L1 page table + * in RAM with 1MB section translation entries over the 4GB address + * space. + * (ref: section 10.2 and example 15-4 in Cortex-A series + * programmer's guide) + * + * FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to + * 512 bytes. So add double the space in cbmem and fix-up the pointer. + */ + ttb_size = L1_TLB_ENTRIES * sizeof(unsigned long); + ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size * 2); + ttb_addr = ALIGN(ttb_addr + ttb_size, ttb_size); + printk(BIOS_DEBUG, "Translation table is @ 0x%08x\n", ttb_addr); + + /* + * Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0 + * table size is 16KB and has indices VA[31:20]. + * + * ref: Arch Ref. Manual for ARMv7-A, B3.5.4, + */ + ttbcr = read_ttbcr(); + ttbcr &= ~(0x3); + write_ttbcr(ttbcr); + + /* + * Translation table base 0 address is in bits 31:14-N, where N is given + * by bits 2:0 in TTBCR (which we set to 0). All lower bits in this + * register should be zero for coreboot. + */ + write_ttbr0(ttb_addr); + + /* disable domain-level checking of permissions */ + write_dacr(~0); +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 02c42a8..041de70 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -47,8 +47,8 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c -romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-y += compute_ip_checksum.c romstage-y += memmove.c romstage-$(CONFIG_ARCH_X86) += gcc.c diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index ad98082..d484d47 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -114,6 +114,19 @@ int cbmem_reinit(u64 baseaddr) bss_cbmem_toc = cbmem_toc; #endif + printk(BIOS_DEBUG, "%s: checkpoint 2\n", __func__); + printk(BIOS_DEBUG, "%s: cbmem_toc: %p\n", __func__, cbmem_toc); +#if 0 + printk(BIOS_DEBUG, "%s: cbmem_toc[0].magic: 0x%02x%02x%02x%02x, CBMEM_MAGIC: 0x%08x\n", + __func__, + *((uint8_t *)&cbmem_toc[0] + 0), + *((uint8_t *)&cbmem_toc[0] + 1), + *((uint8_t *)&cbmem_toc[0] + 2), + *((uint8_t *)&cbmem_toc[0] + 3), + CBMEM_MAGIC); +#endif + printk(BIOS_DEBUG, "%s: cbmem_toc[0].magic: 0x%08x, CBMEM_MAGIC: 0x%08x\n", + __func__, (uint32_t)(cbmem_toc[0].magic), CBMEM_MAGIC); return (cbmem_toc[0].magic == CBMEM_MAGIC); } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index be5216f..3303062 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -23,19 +23,37 @@ #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/power.h> +#include <arch/cache.h> + +/* convenient shorthand (in MB) */ +#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) +#define DRAM_SIZE CONFIG_DRAM_SIZE_MB +#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ + void hardwaremain(int boot_complete); void main(void) { console_init(); printk(BIOS_INFO, "hello from ramstage; now with deluxe exception handling.\n"); - /* this is going to move, but we must have it now and we're not sure where */ - exception_init(); - /* place at top of physical memory */ + /* set up coreboot tables */ high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((CONFIG_DRAM_SIZE_MB << 20UL) * CONFIG_NR_DRAM_BANKS) - - CONFIG_COREBOOT_TABLES_SIZE; + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + cbmem_init(high_tables_base, high_tables_size); + + /* set up dcache and MMU */ + /* FIXME: this should happen in romstage (along with cbmem init) */ + mmu_init(); + mmu_config_range(0, DRAM_START, DCACHE_OFF); + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + dcache_invalidate_all(); + dcache_mmu_enable(); + + /* this is going to move, but we must have it now and we're not sure where */ + exception_init(); const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index bfb4156..1e8dd8a 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -74,6 +74,13 @@ static void graphics(void) exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } +/* for cbmem_initialize() */ +unsigned long get_top_of_ram(void); +unsigned long get_top_of_ram(void) +{ + return CONFIG_SYS_SDRAM_BASE + CONFIG_DRAM_SIZE_MB - 1UL; +} + void main(void) { struct mem_timings *mem; @@ -113,9 +120,6 @@ void main(void) while(1); } - /* Set up MMU and caches */ - mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); - initialize_s5p_mshc(); graphics();

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Patch set updated for coreboot: 57b3269 AMD hudson & SB800 - Fix issues with mawk
by Martin Roth 25 Mar '13

25 Mar '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2628 -gerrit commit 57b3269107d8232e8fb1e3c8bb2ed7d2a9193cad Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Mar 11 13:17:27 2013 -0600 AMD hudson & SB800 - Fix issues with mawk When calculating the offsets of the various binary blobs within the coreboot.rom file, we noticed that using mawk as the awk tool instead of using gawk led to build issues. This was finally traced to the maximum value of the unsigned long variables within mawk - 0x7fff_ffff. Because we were doing calculations on values up in the 0xffxxxxxx range, these numbers would either be turned into floating point values and printed using scientific notation, or truncated at 0x7fff_ffff. To fix this, we print the values out as floating point, with no decimal digits. This works in gawk, mawk, and original-awk and as the testing below show, seems to be the best way to do this. printf %u 0xFFFFFFFF | awk '{printf("%.0f %u %d", $1 , $1 , $1 )}' mawk: 4294967295 2147483647 2147483647 original-awk: 4294967295 2147483648 4294967295 gawk: 4294967295 4294967295 4294967295 The issue of %d not matching gawk and original-awk has been reported to ubuntu. In the future, I'd recommend that whenever awk is used, a format is specified. It doesn't seem that we can count on the representation being the same between the different versions. Change-Id: I7b6b821c8ab13ad11f72e674ac726a98e8678710 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 15 +++++++++------ src/southbridge/amd/cimx/sb800/Makefile.inc | 6 ++++-- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 18a0ffb..da029a0 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -25,7 +25,8 @@ HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) #assume the cbfs header is less than 128 bytes. ROMSIG_SIZE=16 ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -HUDSON_XHCI_POSITION=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 | awk '{print $$1 + $$2 + $$3}') +HUDSON_XHCI_POSITION=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ + | awk '{printf("%.0f", $$1 + $$2 + $$3)}') XHCI_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_XHCI_FWM_FILE))) else HUDSON_XHCI_POSITION=0 @@ -34,7 +35,8 @@ endif ifeq ($(CONFIG_HUDSON_GEC_FWM), y) HUDSON_GEC_POSITION=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ - $(XHCI_FWM_SIZE) 128 | awk '{print $$1 + $$2 + $$3 + $$4 + $$5}') + $(XHCI_FWM_SIZE) 128 \ + | awk '{printf("%.0f", $$1 + $$2 + $$3 + $$4 + $$5)}') GEC_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_GEC_FWM_FILE))) else HUDSON_GEC_POSITION=0 @@ -42,10 +44,11 @@ GEC_FWM_SIZE=0 endif ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -HUDSON_IMC_POSITION_UNALIGN=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ - $(XHCI_FWM_SIZE) 128 \ - $(GEC_FWM_SIZE) 128 65535 | awk '{print $$1 + $$2 + $$3 + $$4 + $$5 + $$6 + $$7 + $$8}') -HUDSON_IMC_POSITION=$(shell echo $(HUDSON_IMC_POSITION_UNALIGN) | awk '{print $$1 - $$1 % 65536}') +HUDSON_IMC_POSITION_UNALIGN=$(shell echo $(HUDSON_FWM_POSITION) \ + $(ROMSIG_SIZE) 128 $(XHCI_FWM_SIZE) 128 $(GEC_FWM_SIZE) 128 65535 \ + | awk '{printf("%.0f", $$1 + $$2 + $$3 + $$4 + $$5 + $$6 + $$7 + $$8)}') +HUDSON_IMC_POSITION=$(shell echo $(HUDSON_IMC_POSITION_UNALIGN) \ + | awk '{printf("%.0f", $$1 - $$1 % 65536)}') else HUDSON_IMC_POSITION=0 endif diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 4041b22..524c2d3 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -70,8 +70,10 @@ SB800_FWM_POSITION=$(shell printf %u $(CONFIG_SB800_FWM_POSITION)) #assume the cbfs header is less than 128 bytes. ROMSIG_SIZE=16 -SB800_IMC_POSITION_UNALIGN=$(shell echo $(SB800_FWM_POSITION) $(ROMSIG_SIZE) 128 65535 | awk '{print $$1 + $$2 + $$3 + $$4}') -SB800_IMC_POSITION=$(shell echo $(SB800_IMC_POSITION_UNALIGN) | awk '{print $$1 - $$1 % 65536}') +SB800_IMC_POSITION_UNALIGN=$(shell echo $(SB800_FWM_POSITION) $(ROMSIG_SIZE) \ + 128 65535 | awk '{printf("%.0f", $$1 + $$2 + $$3 + $$4)}') +SB800_IMC_POSITION=$(shell echo $(SB800_IMC_POSITION_UNALIGN) \ + | awk '{printf("%.0f", $$1 - $$1 % 65536)}') $(obj)/coreboot_SB800_romsig.bin: \ $(call strip_quotes, $(CONFIG_SB800_IMC_FWM_FILE)) \

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coreboot-gerrit March 2013