coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 3651e58 AMD hudson & SB800 - Fix issues with mawk
by Martin Roth 25 Mar '13

25 Mar '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2628 -gerrit commit 3651e58b74dd0480dbd0b0ed21898f59642d71fd Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Mar 11 13:17:27 2013 -0600 AMD hudson & SB800 - Fix issues with mawk When calculating the offsets of the various binary blobs within the coreboot.rom file, we noticed that using mawk as the awk tool instead of using gawk led to build issues. This was finally traced to the maximum value of the unsigned long variables within mawk - 0x7fff_ffff. Because we were doing calculations on values up in the 0xffxxxxxx range, these numbers would either be turned into floating point values and printed using scientific notation, or truncated at 0x7fff_ffff. To fix this, we print the values out as floating point, with no decimal digits. This works in gawk, mawk, and original-awk and as the testing below show, seems to be the best way to do this. printf %u 0xFFFFFFFF | awk '{printf("%.0f %u %d", $1 , $1 , $1 )}' mawk: 4294967295 2147483647 2147483647 original-awk: 4294967295 2147483648 4294967295 gawk: 4294967295 4294967295 4294967295 The issue of %d not matching gawk and original-awk has been reported to ubuntu. In the future, I'd recommend that whenever awk is used, a format is specifiedi. It doesn't seem that we can count on the representation being the same between the different versions. Change-Id: I7b6b821c8ab13ad11f72e674ac726a98e8678710 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 15 +++++++++------ src/southbridge/amd/cimx/sb800/Makefile.inc | 6 ++++-- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 18a0ffb..da029a0 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -25,7 +25,8 @@ HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) #assume the cbfs header is less than 128 bytes. ROMSIG_SIZE=16 ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -HUDSON_XHCI_POSITION=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 | awk '{print $$1 + $$2 + $$3}') +HUDSON_XHCI_POSITION=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ + | awk '{printf("%.0f", $$1 + $$2 + $$3)}') XHCI_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_XHCI_FWM_FILE))) else HUDSON_XHCI_POSITION=0 @@ -34,7 +35,8 @@ endif ifeq ($(CONFIG_HUDSON_GEC_FWM), y) HUDSON_GEC_POSITION=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ - $(XHCI_FWM_SIZE) 128 | awk '{print $$1 + $$2 + $$3 + $$4 + $$5}') + $(XHCI_FWM_SIZE) 128 \ + | awk '{printf("%.0f", $$1 + $$2 + $$3 + $$4 + $$5)}') GEC_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_GEC_FWM_FILE))) else HUDSON_GEC_POSITION=0 @@ -42,10 +44,11 @@ GEC_FWM_SIZE=0 endif ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -HUDSON_IMC_POSITION_UNALIGN=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ - $(XHCI_FWM_SIZE) 128 \ - $(GEC_FWM_SIZE) 128 65535 | awk '{print $$1 + $$2 + $$3 + $$4 + $$5 + $$6 + $$7 + $$8}') -HUDSON_IMC_POSITION=$(shell echo $(HUDSON_IMC_POSITION_UNALIGN) | awk '{print $$1 - $$1 % 65536}') +HUDSON_IMC_POSITION_UNALIGN=$(shell echo $(HUDSON_FWM_POSITION) \ + $(ROMSIG_SIZE) 128 $(XHCI_FWM_SIZE) 128 $(GEC_FWM_SIZE) 128 65535 \ + | awk '{printf("%.0f", $$1 + $$2 + $$3 + $$4 + $$5 + $$6 + $$7 + $$8)}') +HUDSON_IMC_POSITION=$(shell echo $(HUDSON_IMC_POSITION_UNALIGN) \ + | awk '{printf("%.0f", $$1 - $$1 % 65536)}') else HUDSON_IMC_POSITION=0 endif diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 4041b22..524c2d3 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -70,8 +70,10 @@ SB800_FWM_POSITION=$(shell printf %u $(CONFIG_SB800_FWM_POSITION)) #assume the cbfs header is less than 128 bytes. ROMSIG_SIZE=16 -SB800_IMC_POSITION_UNALIGN=$(shell echo $(SB800_FWM_POSITION) $(ROMSIG_SIZE) 128 65535 | awk '{print $$1 + $$2 + $$3 + $$4}') -SB800_IMC_POSITION=$(shell echo $(SB800_IMC_POSITION_UNALIGN) | awk '{print $$1 - $$1 % 65536}') +SB800_IMC_POSITION_UNALIGN=$(shell echo $(SB800_FWM_POSITION) $(ROMSIG_SIZE) \ + 128 65535 | awk '{printf("%.0f", $$1 + $$2 + $$3 + $$4)}') +SB800_IMC_POSITION=$(shell echo $(SB800_IMC_POSITION_UNALIGN) \ + | awk '{printf("%.0f", $$1 - $$1 % 65536)}') $(obj)/coreboot_SB800_romsig.bin: \ $(call strip_quotes, $(CONFIG_SB800_IMC_FWM_FILE)) \

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Patch set updated for coreboot: 28164b9 samsung/exynos5: add resource functions for the display port
by Ronald G. Minnich 25 Mar '13

25 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2615 -gerrit commit 28164b94cc803bbef11c1343d9278a4d76f3f45b Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 18 09:49:54 2013 -0700 samsung/exynos5: add resource functions for the display port NOT WORKING. Simplified devicetree.cb however. Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. We realized that the display code should be part of the cpu -- that's how the hardware works! Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/displayport/Kconfig | 2 - .../exynos5-common/displayport/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/displayport/chip.h | 40 -------- .../exynos5-common/displayport/displayport.c | 107 --------------------- src/cpu/samsung/exynos5-common/exynos-fb.c | 4 +- src/cpu/samsung/exynos5250/chip.h | 40 ++++++++ src/cpu/samsung/exynos5250/cpu.c | 84 +++++++++++++++- src/mainboard/google/snow/devicetree.cb | 17 +--- src/vendorcode/google/chromeos/build-snow | 4 +- 9 files changed, 130 insertions(+), 170 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig deleted file mode 100644 index 26d1422..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config EXYNOS_DISPLAYPORT - bool diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc deleted file mode 100644 index 7c52eaf..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c - diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h deleted file mode 100644 index 53b7836..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/chip.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H -#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H - -struct cpu_samsung_exynos5_common_displayport_config { - /* special magic numbers! */ - int clkval_f; - int upper_margin; - int lower_margin; - int vsync; - int left_margin; - int right_margin; - int hsync; - - int xres; - int yres; - int bpp; - - u32 lcdbase; -}; - -#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c deleted file mode 100644 index 1c08bc7..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/displayport.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <delay.h> -#include <arch/io.h> -#include <device/device.h> - -/* we distinguish a display port device from a raw graphics device because there are - * dramatic differences in startup depending on graphics usage. To make startup fast - * and easier to understand and debug we explicitly name this common case. The alternate - * approach, involving lots of machine and callbacks, is hard to debug and verify. - */ -static void exynos_displayport_init(void) -{ - struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; - /* put these on the stack. If, at some point, we want to move this code to a - * pre-ram stage, it will be much easier. - */ - vidinfo_t vi; - struct exynos5_fimd_panel panel; - void *lcdbase; - - memset(vi, 0, sizeof(vi)); - memset(panel, 0, sizeof(panel)); - - panel.is_dp = 1; /* Display I/F is eDP */ - /* while it is true that we did a memset to zero, - * we leave some 'set to zero' entries here to make - * it clear what's going on. Graphics is confusing. - */ - panel.is_mipi = 0; - panel.fixvclk = 0; - panel.ivclk = 0; - panel.clkval_f = conf->clkval_f; - panel.upper_margin = conf->upper_margin; - panel.lower_margin = conf->lower_margin; - panel.vsync = conf->vsync; - panel.left_margin = conf->left_margin; - panel.right_margin = conf->right_margin; - panel.hsync = conf->hsync; - - vi->vl_col = conf->xres; - vi->fl_row = conf->yres; - vi->vl_bpix = conf->bpp; - vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */ - - lcdbase = conf->lcdbase; - printk(BIOS_DEBUG, "Initializing exynos VGA\n"); - ret = lcd_ctrl_init(&vi, &panel, lcdbase); -#if 0 - ret = board_dp_lcd_vdd(blob, &wait_ms); - ret = board_dp_bridge_setup(blob, &wait_ms); - while (tries < 5) { - ret = board_dp_bridge_init(blob, &wait_ms); - ret = board_dp_hotplug(blob, &wait_ms); - if (ret) { - ret = board_dp_bridge_reset(blob, &wait_ms); - continue; - } - ret = dp_controller_init(blob, &wait_ms); - ret = board_dp_backlight_vdd(blob, &wait_ms); - ret = board_dp_backlight_pwm(blob, &wait_ms); - ret = board_dp_backlight_en(blob, &wait_ms); - } -#endif -} - -static void exynos_displayport_noop(device_t dummy) -{ -} - -static struct device_operations exynos_displayport_operations = { - .read_resources = exynos_displayport_noop, - .set_resources = exynos_displayport_noop, - .enable_resources = exynos_displayport_noop, - .init = exynos_displayport_init, - .scan_bus = exynos_displayport_noop, -}; - -static void exynos_displayport_enable(struct device *dev) -{ - if (dev->link_list != NULL) - dev->ops = &exynos_displayport_operations; -} - -struct chip_operations drivers_i2c_exynos_displayport_ops = { - CHIP_NAME("exynos displayport") - .enable_dev = exynos_displayport_enable; -}; diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 30d0767..2671305 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -100,7 +100,7 @@ static void fimd_bypass(void) { struct exynos5_sysreg *sysreg = samsung_get_base_sysreg(); - /*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/ + setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } @@ -586,7 +586,9 @@ int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, //vi->yres = panel_info->vl_row; fimd_bypass(); + printk(BIOS_SPEW, "fimd_bypass\n"); fb_init(panel_info, lcdbase, panel_data); + printk(BIOS_SPEW, "fb_init(%p, %p, %p\n",panel_info, lcdbase, panel_data); /* Enable flushing after LCD writes if requested */ // forget it. lcd_set_flush_dcache(1); diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h new file mode 100644 index 0000000..798cd26 --- /dev/null +++ b/src/cpu/samsung/exynos5250/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5250_H +#define CPU_SAMSUNG_EXYNOS5250_H + +struct cpu_samsung_exynos5250_config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5250_H */ diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index bcf4d22..f090654 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,5 +1,14 @@ +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <delay.h> #include <console/console.h> +#include <arch/io.h> #include <device/device.h> +#include <cbmem.h> +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> +#include "chip.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) @@ -28,8 +37,76 @@ static struct device_operations domain_ops = { .scan_bus = domain_scan_bus, }; +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(device_t dev) +{ + int ret; + struct cpu_samsung_exynos5250_config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + u32 lcdbase; + + printk(BIOS_SPEW, "%s: dev %p, conf %p\n", __func__, dev, conf); + memset(&vi, 0, sizeof(vi)); + memset(&panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi.vl_col = conf->xres; + vi.vl_row = conf->yres; + vi.vl_bpix = conf->bpp; + printk(BIOS_SPEW, "lcd base is %08ulx\n", conf->lcdbase); + /* The size is a magic number from hardware. */ + mmio_resource(dev, 0, conf->lcdbase/KiB, 64); + vi.cmap = (void *)conf->lcdbase; + lcdbase = conf->lcdbase + 64*KiB; + + mmio_resource(dev, 1, lcdbase/KiB, (conf->xres*conf->yres*4 + (KiB-1))/KiB); + printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); +#if 0 + ret = board_dp_lcd_vdd(blob, &wait_ms); + ret = board_dp_bridge_setup(blob, &wait_ms); + while (tries < 5) { + ret = board_dp_bridge_init(blob, &wait_ms); + ret = board_dp_hotplug(blob, &wait_ms); + if (ret) { + ret = board_dp_bridge_reset(blob, &wait_ms); + continue; + } + ret = dp_controller_init(blob, &wait_ms); + ret = board_dp_backlight_vdd(blob, &wait_ms); + ret = board_dp_backlight_pwm(blob, &wait_ms); + ret = board_dp_backlight_en(blob, &wait_ms); + } +#endif +} + static void cpu_init(device_t dev) { + printk(BIOS_SPEW, "%s\n", __func__); + exynos_displayport_init(dev); } static void cpu_noop(device_t dev) @@ -44,17 +121,20 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_exynos5250_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { + printk(BIOS_SPEW, "%s: DOMAIN\n", __func__); dev->ops = &domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + printk(BIOS_SPEW, "%s: CPU_CLUSTER\n", __func__); dev->ops = &cpu_ops; } + printk(BIOS_SPEW, "%s: done\n", __func__); } struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") - .enable_dev = enable_dev, + .enable_dev = enable_exynos5250_dev, }; diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 5ad786e..e8da851 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -17,18 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# FIXME: this is just a stub for now chip cpu/samsung/exynos5250 - -device cpu_cluster 0 on -end - -device domain 0 on - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # ? - device i2c 9 on end # ? - end - chip cpu/samsung/exynos5-common/displayport + device cpu_cluster 0 on end register "xres" = "1366" register "yres" = "768" register "bpp" = "16" @@ -40,7 +30,6 @@ device domain 0 on register "left_margin" = "80" register "right_margin" = "48" register "hsync" = "32" - register "lcdbase" = "0x10000000" - end -end + register "lcdbase" = "0x50000000" + end diff --git a/src/vendorcode/google/chromeos/build-snow b/src/vendorcode/google/chromeos/build-snow index a749ba5..9cdba75 100755 --- a/src/vendorcode/google/chromeos/build-snow +++ b/src/vendorcode/google/chromeos/build-snow @@ -70,8 +70,8 @@ main() { create_diff_192k "$OUTPUT" "$TMP_DIFF" echo "OK: Generated image (with BL1) in $OUTPUT" if is_servod_ready; then - echo "servod detected - flashing into device." - fast_flash_image "$OUTPUT" "$TMP_DIFF" + echo "servod detected - NOT flashing into device." + echo fast_flash_image "$OUTPUT" "$TMP_DIFF" echo "OK: Generated and flashed 128k of image into device via servo." else echo "(servod is not running, flashing into device is skipped)"

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Patch merged into coreboot/master: 59c020a libpayload: fix use-after-free in usb_exit()
by gerrit＠coreboot.org 25 Mar '13

25 Mar '13

the following patch was just integrated into master: commit 59c020ab15fcc090e0605df1e17f41ffa861b153 Author: Mathias Krause <minipli(a)googlemail.com> Date: Sun Mar 24 19:40:02 2013 +0100 libpayload: fix use-after-free in usb_exit() The controller's shutdown function free()s the controller structure so we shouldn't access it any more after calling shutdown. As all controllers detach themself, i.e. unchain themself from usb_hcs, just keep iterating over usb_hcs until it's NULL. Change-Id: Ie85caba0f685494c3fe04c550a5a14bc4158a94e Signed-off-by: Mathias Krause <minipli(a)googlemail.com> Reviewed-on: http://review.coreboot.org/2900 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Mar 25 12:47:17 2013, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Mon Mar 25 15:34:13 2013, giving +2 See http://review.coreboot.org/2900 for details. -gerrit

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Patch merged into coreboot/master: 7a9da71 libpayload: EHCI - detach controller in ehci_shutdown()
by gerrit＠coreboot.org 25 Mar '13

25 Mar '13

the following patch was just integrated into master: commit 7a9da71c5f276cdfd986ad81b2b344fc641bd0a7 Author: Mathias Krause <minipli(a)googlemail.com> Date: Sun Mar 24 19:40:01 2013 +0100 libpayload: EHCI - detach controller in ehci_shutdown() It shouldn't be used any more as we're about to free() the memory behind the controller -- therefore detach it. Change-Id: I875322a9940570c51d412a7f3bfb6af4ea3b3764 Signed-off-by: Mathias Krause <minipli(a)googlemail.com> Reviewed-on: http://review.coreboot.org/2899 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.huber(a)secunet.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Mar 25 12:34:31 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Mar 25 13:18:40 2013, giving +2 See http://review.coreboot.org/2899 for details. -gerrit

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Patch set updated for coreboot: 71116c7 AMD: Drop six copies of wrmsr_amd and rdmsr_amd
by Kyösti Mälkki 25 Mar '13

25 Mar '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2898 -gerrit commit 71116c7ce208339e92d32e0496f8cbf41bc054f8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 25 12:48:49 2013 +0200 AMD: Drop six copies of wrmsr_amd and rdmsr_amd Based on comments in cpu/x86/msr.h for wrmsr/rdmsr, and for symmetry, I have added __attribute__((always_inline)) for these. Change-Id: Ia0a34c15241f9fbc8c78763386028ddcbe6690b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family10/model_10_init.c | 20 -------------------- src/cpu/amd/agesa/family12/model_12_init.c | 20 -------------------- src/cpu/amd/agesa/family14/model_14_init.c | 20 -------------------- src/cpu/amd/agesa/family15/model_15_init.c | 20 -------------------- src/cpu/amd/agesa/family15tn/model_15_init.c | 20 -------------------- src/cpu/amd/model_10xxx/model_10xxx_init.c | 20 -------------------- src/cpu/amd/model_10xxx/processor_name.c | 3 +-- src/cpu/amd/model_fxx/model_fxx_init.c | 20 -------------------- src/cpu/amd/model_fxx/processor_name.c | 12 +----------- src/cpu/amd/mtrr/amd_mtrr.c | 2 +- src/cpu/x86/mtrr/earlymtrr.c | 2 +- src/include/cpu/amd/amdfam12.h | 3 --- src/include/cpu/amd/amdfam14.h | 3 --- src/include/cpu/amd/amdfam15.h | 3 --- src/include/cpu/amd/model_10xxx_msr.h | 3 --- src/include/cpu/amd/mtrr.h | 20 ++++++++++++++++++++ 16 files changed, 24 insertions(+), 167 deletions(-) diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 1f098eb..899a3c4 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -35,26 +35,6 @@ #define MCI_STATUS 0x401 -static msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -static void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_10_init(device_t dev) { printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n"); diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 3450b99..0dae912 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -36,26 +36,6 @@ #define MCI_STATUS 0x401 -msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_12_init(device_t dev) { printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n"); diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 277f974..7ae2b24 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -39,26 +39,6 @@ #define MCI_STATUS 0x401 -msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_14_init(device_t dev) { u32 i; diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index ba1d9a4..ea7e663 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -32,26 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> -msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 938e9c9..aebc27b 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -37,26 +37,6 @@ #include <cpu/amd/agesa/s3_resume.h> #endif -msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index 01ae319..c6cf64a 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -38,26 +38,6 @@ #define MCI_STATUS 0x401 -msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_10xxx_init(device_t dev) { u8 i; diff --git a/src/cpu/amd/model_10xxx/processor_name.c b/src/cpu/amd/model_10xxx/processor_name.c index 62040d9..b16e9ba 100644 --- a/src/cpu/amd/model_10xxx/processor_name.c +++ b/src/cpu/amd/model_10xxx/processor_name.c @@ -29,11 +29,10 @@ #include <console/console.h> #include <string.h> #include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> #include <cpu/cpu.h> #include <cpu/amd/model_10xxx_rev.h> -extern void wrmsr_amd(u32 index, msr_t msr); - /* The maximum length of CPU names is 48 bytes, including the final NULL byte. * If you change these names your BIOS will _NOT_ pass the AMD validation and * your mainboard will not be posted on the AMD Recommended Motherboard Website diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 4ad28a7..d053894 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -80,26 +80,6 @@ int is_cpu_f0_in_bsp(int nodeid) #define MCI_STATUS 0x401 -static inline msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -static inline void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - #define MTRR_COUNT 8 #define ZERO_CHUNK_KB 0x800UL /* 2M */ #define TOLM_KB 0x400000UL diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c index 6f45b0f..766cf92 100644 --- a/src/cpu/amd/model_fxx/processor_name.c +++ b/src/cpu/amd/model_fxx/processor_name.c @@ -35,6 +35,7 @@ #include <console/console.h> #include <string.h> #include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> #include <cpu/amd/model_fxx_rev.h> /* The maximum length of CPU names is 48 bytes, including the final NULL byte. @@ -100,17 +101,6 @@ static const char *processor_names[]={ }; #endif -/* wrmsr_amd() is from yhlu's changes to model_fxx_init.c */ - -static inline void wrmsr_amd(unsigned index, msr_t msr) -{ - __asm__ __volatile__ ( - "wrmsr" - : /* No outputs */ - : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a) - ); -} - int init_processor_name(void) { #if !CONFIG_K8_REV_F_SUPPORT diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index b804d49..2f3e6e3 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -2,9 +2,9 @@ #include <device/device.h> #include <arch/cpu.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> /* These will likely move to some device node or cbmem. */ static uint64_t amd_topmem = 0; diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 593f066..55dbd2f 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -2,8 +2,8 @@ #define EARLYMTRR_C #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) diff --git a/src/include/cpu/amd/amdfam12.h b/src/include/cpu/amd/amdfam12.h index c8d8fcf..9ad84bd 100644 --- a/src/include/cpu/amd/amdfam12.h +++ b/src/include/cpu/amd/amdfam12.h @@ -33,9 +33,6 @@ #define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 -msr_t rdmsr_amd(u32 index); -void wrmsr_amd(u32 index, msr_t msr); - //#if defined(__GNUC__) //// it can be used to get unitid and coreid it running only //struct node_core_id get_node_core_id(u32 nb_cfg_54); diff --git a/src/include/cpu/amd/amdfam14.h b/src/include/cpu/amd/amdfam14.h index 16581e3..c39019b 100644 --- a/src/include/cpu/amd/amdfam14.h +++ b/src/include/cpu/amd/amdfam14.h @@ -33,9 +33,6 @@ #define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 -msr_t rdmsr_amd(u32 index); -void wrmsr_amd(u32 index, msr_t msr); - #if defined(__PRE_RAM__) void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 01da631..0c2cf7b 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -35,9 +35,6 @@ #define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 -msr_t rdmsr_amd(u32 index); -void wrmsr_amd(u32 index, msr_t msr); - #if defined(__PRE_RAM__) void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); diff --git a/src/include/cpu/amd/model_10xxx_msr.h b/src/include/cpu/amd/model_10xxx_msr.h index 7d63079..6678a4f 100644 --- a/src/include/cpu/amd/model_10xxx_msr.h +++ b/src/include/cpu/amd/model_10xxx_msr.h @@ -39,7 +39,4 @@ #define LOGICAL_CPUS_NUM_MSR 0xC001100d #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 -msr_t rdmsr_amd(u32 index); -void wrmsr_amd(u32 index, msr_t msr); - #endif /* CPU_AMD_MODEL_10XXX_MSR_H */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index aa904e6..a9e672b 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -40,6 +40,26 @@ #if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) void amd_setup_mtrrs(void); +static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned index) +{ + msr_t result; + __asm__ __volatile__ ( + "rdmsr" + : "=a" (result.lo), "=d" (result.hi) + : "c"(index), "D"(0x9c5a203a) + ); + return result; +} + +static inline __attribute__((always_inline)) void wrmsr_amd(unsigned index, msr_t msr) +{ + __asm__ __volatile__ ( + "wrmsr" + : /* No outputs */ + : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a) + ); +} + /* To distribute topmem MSRs to APs. */ void setup_bsp_ramtop(void); uint64_t bsp_topmem(void);

1 0

New patch to review for coreboot: 75040b9 libpayload: fix use-after-free in usb_exit()
by Mathias Krause 25 Mar '13

25 Mar '13

Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2900 -gerrit commit 75040b90c9a403905312d3f90636b606e6e5ecaf Author: Mathias Krause <minipli(a)googlemail.com> Date: Sun Mar 24 19:40:02 2013 +0100 libpayload: fix use-after-free in usb_exit() The controller's shutdown function free()s the controller structure so we shouldn't access it any more after calling shutdown. As all controllers detach themself, i.e. unchain themself from usb_hcs, just keep iterating over usb_hcs until it's NULL. Change-Id: Ie85caba0f685494c3fe04c550a5a14bc4158a94e Signed-off-by: Mathias Krause <minipli(a)googlemail.com> --- payloads/libpayload/drivers/usb/usb.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 0448d38..23561c4 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -74,12 +74,8 @@ detach_controller (hci_t *controller) int usb_exit (void) { - if (usb_hcs == 0) - return 0; - hci_t *controller = usb_hcs; - while (controller != NULL) { - controller->shutdown(controller); - controller = controller->next; + while (usb_hcs != NULL) { + usb_hcs->shutdown(usb_hcs); } return 0; }

1 0

New patch to review for coreboot: 7e4028b libpayload: EHCI - detach controller in ehci_shutdown()
by Mathias Krause 25 Mar '13

25 Mar '13

Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2899 -gerrit commit 7e4028b07c143ac0411ac4b5a0b51159076eeda5 Author: Mathias Krause <minipli(a)googlemail.com> Date: Sun Mar 24 19:40:01 2013 +0100 libpayload: EHCI - detach controller in ehci_shutdown() It shouldn't be used any more as we're about to free() the memory behind the controller -- therefore detach it. Change-Id: I875322a9940570c51d412a7f3bfb6af4ea3b3764 Signed-off-by: Mathias Krause <minipli(a)googlemail.com> --- payloads/libpayload/drivers/usb/ehci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 972962c..3e5de1d 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -170,6 +170,7 @@ static int ehci_set_periodic_schedule(ehci_t *ehcic, int enable) static void ehci_shutdown (hci_t *controller) { + detach_controller(controller); /* Make sure periodic schedule is disabled */ ehci_set_periodic_schedule(EHCI_INST(controller), 0); /* Free periodic frame list */

1 0

New patch to review for coreboot: 1e7f383 AMD: Drop six copies of wrmsr_amd and rdmsr_amd
by Kyösti Mälkki 25 Mar '13

25 Mar '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2898 -gerrit commit 1e7f38380ab176d7f17e0c0d6c3bdb716baf4501 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 25 12:48:49 2013 +0200 AMD: Drop six copies of wrmsr_amd and rdmsr_amd Based on comments in cpu/x86/msr.h for wrmsr/rdmsr, and for symmetry, I have added __attribute__((always_inline)) for these. Change-Id: Ia0a34c15241f9fbc8c78763386028ddcbe6690b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family10/model_10_init.c | 20 -------------------- src/cpu/amd/agesa/family12/model_12_init.c | 20 -------------------- src/cpu/amd/agesa/family14/model_14_init.c | 20 -------------------- src/cpu/amd/agesa/family15/model_15_init.c | 20 -------------------- src/cpu/amd/agesa/family15tn/model_15_init.c | 20 -------------------- src/cpu/amd/model_10xxx/model_10xxx_init.c | 20 -------------------- src/cpu/amd/model_fxx/model_fxx_init.c | 20 -------------------- src/cpu/amd/mtrr/amd_mtrr.c | 2 +- src/cpu/x86/mtrr/earlymtrr.c | 2 +- src/include/cpu/amd/amdfam12.h | 3 --- src/include/cpu/amd/amdfam14.h | 3 --- src/include/cpu/amd/amdfam15.h | 3 --- src/include/cpu/amd/model_10xxx_msr.h | 3 --- src/include/cpu/amd/mtrr.h | 20 ++++++++++++++++++++ 14 files changed, 22 insertions(+), 154 deletions(-) diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 1f098eb..899a3c4 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -35,26 +35,6 @@ #define MCI_STATUS 0x401 -static msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -static void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_10_init(device_t dev) { printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n"); diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 3450b99..0dae912 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -36,26 +36,6 @@ #define MCI_STATUS 0x401 -msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_12_init(device_t dev) { printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n"); diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 277f974..7ae2b24 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -39,26 +39,6 @@ #define MCI_STATUS 0x401 -msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_14_init(device_t dev) { u32 i; diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index ba1d9a4..ea7e663 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -32,26 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> -msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 938e9c9..aebc27b 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -37,26 +37,6 @@ #include <cpu/amd/agesa/s3_resume.h> #endif -msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index 01ae319..c6cf64a 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -38,26 +38,6 @@ #define MCI_STATUS 0x401 -msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - static void model_10xxx_init(device_t dev) { u8 i; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 4ad28a7..d053894 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -80,26 +80,6 @@ int is_cpu_f0_in_bsp(int nodeid) #define MCI_STATUS 0x401 -static inline msr_t rdmsr_amd(u32 index) -{ - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; -} - -static inline void wrmsr_amd(u32 index, msr_t msr) -{ - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); -} - #define MTRR_COUNT 8 #define ZERO_CHUNK_KB 0x800UL /* 2M */ #define TOLM_KB 0x400000UL diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index b804d49..2f3e6e3 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -2,9 +2,9 @@ #include <device/device.h> #include <arch/cpu.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> /* These will likely move to some device node or cbmem. */ static uint64_t amd_topmem = 0; diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 593f066..55dbd2f 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -2,8 +2,8 @@ #define EARLYMTRR_C #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) diff --git a/src/include/cpu/amd/amdfam12.h b/src/include/cpu/amd/amdfam12.h index c8d8fcf..9ad84bd 100644 --- a/src/include/cpu/amd/amdfam12.h +++ b/src/include/cpu/amd/amdfam12.h @@ -33,9 +33,6 @@ #define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 -msr_t rdmsr_amd(u32 index); -void wrmsr_amd(u32 index, msr_t msr); - //#if defined(__GNUC__) //// it can be used to get unitid and coreid it running only //struct node_core_id get_node_core_id(u32 nb_cfg_54); diff --git a/src/include/cpu/amd/amdfam14.h b/src/include/cpu/amd/amdfam14.h index 16581e3..c39019b 100644 --- a/src/include/cpu/amd/amdfam14.h +++ b/src/include/cpu/amd/amdfam14.h @@ -33,9 +33,6 @@ #define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 -msr_t rdmsr_amd(u32 index); -void wrmsr_amd(u32 index, msr_t msr); - #if defined(__PRE_RAM__) void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 01da631..0c2cf7b 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -35,9 +35,6 @@ #define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 -msr_t rdmsr_amd(u32 index); -void wrmsr_amd(u32 index, msr_t msr); - #if defined(__PRE_RAM__) void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); diff --git a/src/include/cpu/amd/model_10xxx_msr.h b/src/include/cpu/amd/model_10xxx_msr.h index 7d63079..6678a4f 100644 --- a/src/include/cpu/amd/model_10xxx_msr.h +++ b/src/include/cpu/amd/model_10xxx_msr.h @@ -39,7 +39,4 @@ #define LOGICAL_CPUS_NUM_MSR 0xC001100d #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 -msr_t rdmsr_amd(u32 index); -void wrmsr_amd(u32 index, msr_t msr); - #endif /* CPU_AMD_MODEL_10XXX_MSR_H */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index aa904e6..a9e672b 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -40,6 +40,26 @@ #if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) void amd_setup_mtrrs(void); +static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned index) +{ + msr_t result; + __asm__ __volatile__ ( + "rdmsr" + : "=a" (result.lo), "=d" (result.hi) + : "c"(index), "D"(0x9c5a203a) + ); + return result; +} + +static inline __attribute__((always_inline)) void wrmsr_amd(unsigned index, msr_t msr) +{ + __asm__ __volatile__ ( + "wrmsr" + : /* No outputs */ + : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a) + ); +} + /* To distribute topmem MSRs to APs. */ void setup_bsp_ramtop(void); uint64_t bsp_topmem(void);

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Patch merged into coreboot/master: c15551a dynamic cbmem: fix memconsole and timestamps
by gerrit＠coreboot.org 23 Mar '13

23 Mar '13

the following patch was just integrated into master: commit c15551ab0878c16f61335a701dd34c7d0e89120e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Mar 23 00:00:54 2013 -0500 dynamic cbmem: fix memconsole and timestamps There are assumptions that COLLECT_TIMESTAMPS and CONSOLE_CBMEM rely on EARLY_CBMEM_INIT. This isn't true in the face of DYNAMIC_CBMEM as it provides the same properties as EARLY_CBMEM_INIT. Therefore, allow one to select COLLECT_TIMESTAMPS and CONSOLE_CBMEM when DYNAMIC_CBMEM is selected. Lastly, don't hard code the cbmem implementation when COLLECT_TIMESTAMPS is selected. Change-Id: I053ebb385ad54a90a202da9d70b9d87ecc963656 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Mar 23 09:03:50 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sat Mar 23 19:44:21 2013, giving +2 See http://review.coreboot.org/2895 for details. -gerrit

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Patch merged into coreboot/master: c965076 resources: introduce reserved_ram_resource()
by gerrit＠coreboot.org 23 Mar '13

23 Mar '13

the following patch was just integrated into master: commit c965076c3ecec6ccf8eb0eb1d57d6a0a312dab04 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:03:09 2013 -0500 resources: introduce reserved_ram_resource() mmio_resource() was previously being used for reserving RAM from the OS by using IORESOURCE_IGNORE_MTRR atrribute. Instead, be more explicit for those uses with reserved_ram_resource(). bad_ram_resource() now calls reserved_ram_resource(). Those resources are marked as cacheable but reserved. The sandybridge and haswell code were relying on the implementation fo the MTRR algorithm's interaction for reserved regions. Instead be explicit about what ranges are MMIO reserved and what are RAM reserved. Change-Id: I1e47026970fb37c0305e4d49a12c98b0cdd1abe5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2886 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Mar 23 07:02:24 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sat Mar 23 19:40:35 2013, giving +2 See http://review.coreboot.org/2886 for details. -gerrit

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coreboot-gerrit March 2013