coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 2bb1900 sandybridge: mark graphics memory write-combining
by Aaron Durbin 23 Mar '13

23 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2894 -gerrit commit 2bb1900de285c84f029f9ce3831689bea5b9a0f7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:25:37 2013 -0500 sandybridge: mark graphics memory write-combining The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Change-Id: I7d37fd78906262aabef92c2b4f4cab0e3f7e4f6d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/sandybridge/gma.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index b9a07a2..0d4eb11 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -664,12 +664,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void gma_read_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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New patch to review for coreboot: 14dc66b haswell: mark graphics memory write-combining.
by Aaron Durbin 23 Mar '13

23 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2893 -gerrit commit 14dc66b92c7b8bc3d959ada57ba5fa5b937603da Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:23:05 2013 -0500 haswell: mark graphics memory write-combining. The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Change-Id: I797fcd9f0dfb074f9e45476773acbfe614eb4b0a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/gma.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index d085066..f7b0ab9 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -217,12 +217,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void gma_read_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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New patch to review for coreboot: 563698e mtrr: honor IORESOURCE_WRCOMB
by Aaron Durbin 23 Mar '13

23 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2892 -gerrit commit 563698e6a32661407df6d085780cfdaa4a0eff2c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:20:01 2013 -0500 mtrr: honor IORESOURCE_WRCOMB All resources that set the IORESOURCE_WRCOMB attribute which are also marked as IORESOURCE_PREFETCH will have a MTRR set up that is of the write-combining cacheable type. The only resources on x86 that can be set to write-combining are prefetchable ones. Change-Id: Iba7452cff3677e07d7e263b79982a49c93be9c54 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 6df659b..1f124a2 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -152,10 +152,12 @@ static struct memory_ranges *get_physical_address_space(void) if (addr_space == NULL) { struct memory_range *r; uint32_t below4gbase; - const unsigned long mask = IORESOURCE_CACHEABLE; + unsigned long mask; + unsigned long match; addr_space = &addr_space_storage; + mask = IORESOURCE_CACHEABLE; /* Collect cacheable and uncacheable address ranges. The * uncacheable regions take precedence over the cacheable * regions. */ @@ -168,6 +170,14 @@ static struct memory_ranges *get_physical_address_space(void) insert_memory_range(addr_space, RANGE_TO_PHYS_ADDR(below4gbase), 4096, MTRR_TYPE_UNCACHEABLE); + /* Handle any write combining resources. Only prefetchable + * resources with the IORESOURCE_WRCOMB flag are appropriate + * for this MTRR type. */ + match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; + mask |= match; + memory_ranges_add_resources(addr_space, mask, match, + MTRR_TYPE_WRCOMB); + /* Fill all holes in address space with an uncachable entry. */ memory_ranges_fill_holes(addr_space, MTRR_TYPE_UNCACHEABLE);

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New patch to review for coreboot: dd904de resources: introduce IORESOURCE_WRCOMB
by Aaron Durbin 23 Mar '13

23 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2891 -gerrit commit dd904de76f860c3f7797d8626ebf1dcf85bf693a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:16:58 2013 -0500 resources: introduce IORESOURCE_WRCOMB Certain MMIO resources can be set to a write-combining cacheable mode to increase performance. Typical resources that use this would be graphics memory. Change-Id: Icd96c720f86f7e2f19a6461bb23cb323124eb68e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/device/resource.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 6b66605..4bd9698 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,7 +21,7 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ - +#define IORESOURCE_WRCOMB 0x00100000 /* Write combining resource. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */

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New patch to review for coreboot: f3d0164 resources: remove IORESOURCE_[UMA_FB|IGNORE_MTRR]
by Aaron Durbin 23 Mar '13

23 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2890 -gerrit commit f3d0164cf5d4b8e630630fb4a2aa4867987c522f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:09:46 2013 -0500 resources: remove IORESOURCE_[UMA_FB|IGNORE_MTRR] The IORESOURCE_UMA_FB and IORESOURCE_IGNORE_MTRR attributes on a resource provided hints to the MTRR algorithm. The IORESOURCE_UMA_FB directed the MTRR algorithm to setup a uncacheable space for the resource. The IORESOURCE_IGNORE_MTRR directed the MTRR algorithm to ignore this resource as it was used reserving RAM space. Now that the optimizing MTRR algorithm is in place there isn't a need for these flags. All IORESOURCE_IGNORE_MTRR users are handled by the MTRR code merging resources of the same cacheable type. The users of the IORESOURCE_UMA_FB will find that the default MTRR type calculation mean there isn't a need for this flag any more. Change-Id: I4f62192edd9a700cb80fa7569caf49538f9b83b7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/device/device.h | 6 +++--- src/include/device/resource.h | 2 -- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/include/device/device.h b/src/include/device/device.h index b8dfbf5..44a9742 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -207,16 +207,16 @@ void fixed_mem_resource(device_t dev, unsigned long index, fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE) #define reserved_ram_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE | IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE | IORESOURCE_RESERVE) #define bad_ram_resource(dev, idx, basek, sizek) \ reserved_ram_resource((dev), (idx), (basek), (sizek)) #define uma_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE) #define mmio_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE) void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index ea1bab5..6b66605 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,8 +21,6 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ -#define IORESOURCE_UMA_FB 0x00100000 /* UMA framebuffer */ -#define IORESOURCE_IGNORE_MTRR 0x00200000 /* The resource does not affect MTRR setup. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */

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New patch to review for coreboot: b92c865 x86: add new mtrr implementation
by Aaron Durbin 23 Mar '13

23 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2889 -gerrit commit b92c8659006a0cc343fb5a260e41187da905ce5f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 21:28:08 2013 -0500 x86: add new mtrr implementation The old MTRR code had issues using too many variable MTRRs depending on the physical address space layout dictated by the device resources. This new implementation calculates the default MTRR type by comparing the number of variable MTRRs used for each type. This avoids the need for IORESOURE_UMA_FB because in many of those situations setting the default type to WB frees up the variable MTTRs to set that space to UC. Additionally, it removes the need for IORESOURCE_IGNORE_MTRR becuase the new mtrr uses the memrange library which does merging of resources. Lastly, the sandybridge gma has its speedup optimization removed for the graphics memory by writing a pre-determined MTRR index. That will be fixed in an upcoming patch once write-combining support is added to the resources. Slight differences from previous MTRR code: - The number of reserved OS MTRRs is not a hard limit. It's now advisory as PAT can be used by the OS to setup the regions to the caching policy desired. - The memory types are calculated once by the first CPU to run the code. After that all other CPUs use that value. A pathological case that was previously fixed by changing vendor code to adjust the IO hole location looked like the following: MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 As noted by the output below it's impossible to accomodate those ranges even with 10 variable MTRRS. However, because the code can select WB as the default MTRR type it can be done in 6 MTRRs: MTRR: default type WB/UC MTRR counts: 6/14. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 Change-Id: Idfcc78d9afef9d44c769a676716aae3ff2bd79de Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 776 ++++++++++++++++++-------------- src/include/cpu/x86/mtrr.h | 10 +- src/northbridge/intel/sandybridge/gma.c | 16 +- 3 files changed, 429 insertions(+), 373 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 7076a7e..6df659b 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -4,6 +4,7 @@ * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel * * Copyright 2000 Silicon Integrated System Corporation + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,14 +24,9 @@ * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming */ -/* - 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed - 2005.6 Eric add address bit in x86_setup_mtrrs - 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs, - for AMD, it will not use x86_setup_fixed_mtrrs -*/ - #include <stddef.h> +#include <stdlib.h> +#include <string.h> #include <console/console.h> #include <device/device.h> #include <cpu/x86/msr.h> @@ -39,6 +35,7 @@ #include <cpu/x86/lapic.h> #include <arch/cpu.h> #include <arch/acpi.h> +#include <memrange.h> #if CONFIG_X86_AMD_FIXED_MTRRS #include <cpu/amd/mtrr.h> #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) @@ -46,12 +43,6 @@ #define MTRR_FIXED_WRBACK_BITS 0 #endif -static unsigned int mtrr_msr[] = { - MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, - MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR, - MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, -}; - /* 2 MTRRS are reserved for the operating system */ #define BIOS_MTRRS 6 #define OS_MTRRS 2 @@ -70,82 +61,32 @@ static void detect_var_mtrrs(void) bios_mtrrs = total_mtrrs - OS_MTRRS; } -void enable_fixed_mtrr(void) +static void disable_fixed_mtrr(void) { msr_t msr; msr = rdmsr(MTRRdefType_MSR); - msr.lo |= 0xc00; + msr.lo &= ~MTRRdefTypeFixEn; wrmsr(MTRRdefType_MSR, msr); } -static void enable_var_mtrr(void) +void enable_fixed_mtrr(void) { msr_t msr; msr = rdmsr(MTRRdefType_MSR); - msr.lo |= MTRRdefTypeEn; + msr.lo |= MTRRdefTypeEn | MTRRdefTypeFixEn; wrmsr(MTRRdefType_MSR, msr); } -/* setting variable mtrr, comes from linux kernel source */ -void set_var_mtrr( - unsigned int reg, unsigned long basek, unsigned long sizek, - unsigned char type, unsigned address_bits) +static void enable_var_mtrr(unsigned char deftype) { - msr_t base, mask; - unsigned address_mask_high; - - if (reg >= total_mtrrs) - return; - - // it is recommended that we disable and enable cache when we - // do this. - if (sizek == 0) { - disable_cache(); - - msr_t zero; - zero.lo = zero.hi = 0; - /* The invalid bit is kept in the mask, so we simply clear the - relevant mask register to disable a range. */ - wrmsr (MTRRphysMask_MSR(reg), zero); - - enable_cache(); - return; - } - - - address_mask_high = ((1u << (address_bits - 32u)) - 1u); - - base.hi = basek >> 22; - base.lo = basek << 10; - - if (sizek < 4*1024*1024) { - mask.hi = address_mask_high; - mask.lo = ~((sizek << 10) -1); - } - else { - mask.hi = address_mask_high & (~((sizek >> 22) -1)); - mask.lo = 0; - } - - // it is recommended that we disable and enable cache when we - // do this. - disable_cache(); - - /* Bit 32-35 of MTRRphysMask should be set to 1 */ - base.lo |= type; - mask.lo |= MTRRphysMaskValid; - wrmsr (MTRRphysBase_MSR(reg), base); - wrmsr (MTRRphysMask_MSR(reg), mask); - - enable_cache(); + msr_t msr; - printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", - reg, basek >>10, sizek >> 10, - (type==MTRR_TYPE_UNCACHEABLE)?"UC": - ((type==MTRR_TYPE_WRBACK)?"WB":"Other") - ); + msr = rdmsr(MTRRdefType_MSR); + msr.lo &= ~0xff; + msr.lo |= MTRRdefTypeEn | deftype; + wrmsr(MTRRdefType_MSR, msr); } /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ @@ -172,343 +113,478 @@ static inline unsigned int fls(unsigned int x) return r; } -/* setting up variable and fixed mtrr - * - * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement: - * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum). - * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous - * requirement. So a 8K range must be 8K aligned not 4K aligned. - * - * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]). - * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]). - * A 124MB (128MB - 4MB SMA) example: - * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB). - * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions. - * - * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible, - * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula - * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used. - * The same 124MB example: - * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB) - * or a 156MB (128MB + 32MB - 4MB SMA) example: - * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB) - */ +#define MTRR_VERBOSE_LEVEL BIOS_NEVER + +/* MTRRs are at a 4KiB granularity. Therefore all address calculations can + * be done with 32-bit numbers. This allows for the MTRR code to handle + * up to 2^44 bytes (16 TiB) of address space. */ +#define RANGE_SHIFT 12 +#define ADDR_SHIFT_TO_RANGE_SHIFT(x) \ + (((x) > RANGE_SHIFT) ? ((x) - RANGE_SHIFT) : RANGE_SHIFT) +#define PHYS_TO_RANGE_ADDR(x) ((x) >> RANGE_SHIFT) +#define RANGE_TO_PHYS_ADDR(x) (((resource_t)(x)) << RANGE_SHIFT) +#define NUM_FIXED_MTRRS (NUM_FIXED_RANGES / RANGES_PER_FIXED_MTRR) + +/* The minimum alignment while handling variable MTRR ranges is 64MiB. */ +#define MTRR_MIN_ALIGN PHYS_TO_RANGE_ADDR(64 << 20) +/* Helpful constants. */ +#define RANGE_1MB PHYS_TO_RANGE_ADDR(1 << 20) +#define RANGE_4GB (1 << (ADDR_SHIFT_TO_RANGE_SHIFT(32))) + +static inline uint32_t memory_range_base_mtrr_addr(struct memory_range *r) +{ + return PHYS_TO_RANGE_ADDR(memory_range_base(r)); +} -static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) +static inline uint32_t memory_range_end_mtrr_addr(struct memory_range *r) { - unsigned int i; - unsigned int fixed_msr = NUM_FIXED_RANGES >> 3; - msr_t msr; - msr.lo = msr.hi = 0; /* Shut up gcc */ - for(i = first; i < last; i++) { - /* When I switch to a new msr read it in */ - if (fixed_msr != i >> 3) { - /* But first write out the old msr */ - if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { - disable_cache(); - wrmsr(mtrr_msr[fixed_msr], msr); - enable_cache(); - } - fixed_msr = i>>3; - msr = rdmsr(mtrr_msr[fixed_msr]); - } - if ((i & 7) < 4) { - msr.lo &= ~(0xff << ((i&3)*8)); - msr.lo |= type << ((i&3)*8); - } else { - msr.hi &= ~(0xff << ((i&3)*8)); - msr.hi |= type << ((i&3)*8); - } - } - /* Write out the final msr */ - if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { - disable_cache(); - wrmsr(mtrr_msr[fixed_msr], msr); - enable_cache(); - } + return PHYS_TO_RANGE_ADDR(memory_range_end(r)); } -static unsigned fixed_mtrr_index(unsigned long addrk) +static struct memory_ranges *get_physical_address_space(void) { - unsigned index; - index = (addrk - 0) >> 6; - if (index >= 8) { - index = ((addrk - 8*64) >> 4) + 8; + static struct memory_ranges *addr_space; + static struct memory_ranges addr_space_storage; + + /* In order to handle some chipsets not being able to pre-determine + * uncacheable ranges, such as graphics memory, at resource inseration + * time remove unacheable regions from the cacheable ones. */ + if (addr_space == NULL) { + struct memory_range *r; + uint32_t below4gbase; + const unsigned long mask = IORESOURCE_CACHEABLE; + + addr_space = &addr_space_storage; + + /* Collect cacheable and uncacheable address ranges. The + * uncacheable regions take precedence over the cacheable + * regions. */ + memory_ranges_init(addr_space, mask, mask, MTRR_TYPE_WRBACK); + memory_ranges_add_resources(addr_space, mask, 0, + MTRR_TYPE_UNCACHEABLE); + /* Ensure there is an uncacheable entry just below 4GiB to + * be expanded with the fill holes routine below. */ + below4gbase = RANGE_4GB - PHYS_TO_RANGE_ADDR(4096); + insert_memory_range(addr_space, RANGE_TO_PHYS_ADDR(below4gbase), + 4096, MTRR_TYPE_UNCACHEABLE); + + /* Fill all holes in address space with an uncachable entry. */ + memory_ranges_fill_holes(addr_space, MTRR_TYPE_UNCACHEABLE); + + printk(BIOS_DEBUG, "MTRR: Physical address space:\n"); + memory_ranges_each_entry(r, addr_space) + printk(BIOS_DEBUG, + "0x%016llx - 0x%016llx size 0x%08llx type %ld\n", + memory_range_base(r), memory_range_end(r), + memory_range_size(r), memory_range_tag(r)); } - if (index >= 24) { - index = ((addrk - (8*64 + 16*16)) >> 2) + 24; - } - if (index > NUM_FIXED_RANGES) { - index = NUM_FIXED_RANGES; - } - return index; + + return addr_space; } -static unsigned int range_to_mtrr(unsigned int reg, - unsigned long range_startk, unsigned long range_sizek, - unsigned long next_range_startk, unsigned char type, - unsigned int address_bits, unsigned int above4gb) +/* Fixed MTRR descriptor. This structure defines the step size and begin + * and end (exclusive) address covered by a set of fixe MTRR MSRs. + * It also describes the offset in byte intervals to store the calculated MTRR + * type in an array. */ +struct fixed_mtrr_desc { + uint32_t begin; + uint32_t end; + uint32_t step; + int range_index; + int msr_index_base; +}; + +/* Shared MTRR calculations. Can be reused by APs. */ +static uint8_t fixed_mtrr_types[NUM_FIXED_RANGES]; + +/* Fixed MTRR descriptors. */ +static const struct fixed_mtrr_desc fixed_mtrr_desc[] = { + { PHYS_TO_RANGE_ADDR(0x000000), PHYS_TO_RANGE_ADDR(0x080000), + PHYS_TO_RANGE_ADDR(64 * 1024), 0, MTRRfix64K_00000_MSR }, + { PHYS_TO_RANGE_ADDR(0x080000), PHYS_TO_RANGE_ADDR(0x0C0000), + PHYS_TO_RANGE_ADDR(16 * 1024), 8, MTRRfix16K_80000_MSR }, + { PHYS_TO_RANGE_ADDR(0x0C0000), PHYS_TO_RANGE_ADDR(0x100000), + PHYS_TO_RANGE_ADDR(4 * 1024), 24, MTRRfix4K_C0000_MSR }, +}; + +static void calc_fixed_mtrrs(void) { - unsigned long hole_startk = 0, hole_sizek = 0; - - if (!range_sizek) { - /* If there's no MTRR hole, this function will bail out - * here when called for the hole. - */ - printk(BIOS_SPEW, "Zero-sized MTRR range @%ldKB\n", range_startk); - return reg; - } + static int fixed_mtrr_types_initialized; + struct memory_ranges *phys_addr_space; + struct memory_range *r; + const struct fixed_mtrr_desc *desc; + const struct fixed_mtrr_desc *last_desc; + uint32_t begin; + uint32_t end; + int type_index; + + if (fixed_mtrr_types_initialized) + return; - if (reg >= bios_mtrrs) { - printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n", - range_startk >>10, range_sizek >> 10, - (type==MTRR_TYPE_UNCACHEABLE)?"UC": - ((type==MTRR_TYPE_WRBACK)?"WB":"Other") ); - return reg; - } + phys_addr_space = get_physical_address_space(); -#define MIN_ALIGN 0x10000 /* 64MB */ - - if (above4gb == 2 && type == MTRR_TYPE_WRBACK && - range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) { - /* - * If this range is not divisible then instead - * make a larger range and carve out an uncached hole. - */ - hole_startk = range_startk + range_sizek; - hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN); - range_sizek += hole_sizek; - } + /* Set all fixed ranges to uncacheable first. */ + memset(&fixed_mtrr_types[0], MTRR_TYPE_UNCACHEABLE, NUM_FIXED_RANGES); - while(range_sizek) { - unsigned long max_align, align; - unsigned long sizek; - /* Compute the maximum size I can make a range */ - max_align = fls(range_startk); - align = fms(range_sizek); - if (align > max_align) { - align = max_align; - } - sizek = 1 << align; - - /* if range is above 4GB, MTRR is needed - * only if above4gb flag is set - */ - if (range_startk < 0x100000000ull / 1024 || above4gb) - set_var_mtrr(reg++, range_startk, sizek, type, address_bits); - range_startk += sizek; - range_sizek -= sizek; - if (reg >= bios_mtrrs) { - printk(BIOS_ERR, "Running out of variable MTRRs!\n"); + desc = &fixed_mtrr_desc[0]; + last_desc = &fixed_mtrr_desc[ARRAY_SIZE(fixed_mtrr_desc) - 1]; + type_index = desc->range_index; + + memory_ranges_each_entry(r, phys_addr_space) { + begin = memory_range_base_mtrr_addr(r); + end = memory_range_end_mtrr_addr(r); + + if (begin >= last_desc->end) break; + + if (end > last_desc->end) + end = last_desc->end; + + /* Get to the correct fixed mtrr descriptor. */ + while (begin >= desc->end) + desc++; + + type_index = desc->range_index; + type_index += (begin - desc->begin) / desc->step; + + while (begin != end) { + unsigned char type; + + type = memory_range_tag(r); + printk(MTRR_VERBOSE_LEVEL, + "MTRR addr 0x%x-0x%x set to %d type @ %d\n", + begin, begin + desc->step, type, type_index); + if (type == MTRR_TYPE_WRBACK) + type |= MTRR_FIXED_WRBACK_BITS; + fixed_mtrr_types[type_index] = type; + type_index++; + begin += desc->step; + if (begin == desc->end) + desc++; } } + fixed_mtrr_types_initialized = 1; +} - if (hole_sizek) { - printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n", - hole_startk >> 10, (hole_startk + hole_sizek) >> 10); - reg = range_to_mtrr(reg, hole_startk, hole_sizek, - next_range_startk, MTRR_TYPE_UNCACHEABLE, - address_bits, above4gb); +static void commit_fixed_mtrrs(void) +{ + int i; + int j; + int msr_num; + int type_index; + /* 8 ranges per msr. */ + msr_t fixed_msrs[NUM_FIXED_MTRRS]; + unsigned long msr_index[NUM_FIXED_MTRRS]; + + memset(&fixed_msrs, 0, sizeof(fixed_msrs)); + + disable_cache(); + + msr_num = 0; + type_index = 0; + for (i = 0; i < ARRAY_SIZE(fixed_mtrr_desc); i++) { + const struct fixed_mtrr_desc *desc; + int num_ranges; + + desc = &fixed_mtrr_desc[i]; + num_ranges = (desc->end - desc->begin) / desc->step; + for (j = 0; j < num_ranges; j += RANGES_PER_FIXED_MTRR) { + msr_index[msr_num] = desc->msr_index_base + + (j / RANGES_PER_FIXED_MTRR); + fixed_msrs[msr_num].lo |= + fixed_mtrr_types[type_index++] << 0; + fixed_msrs[msr_num].lo |= + fixed_mtrr_types[type_index++] << 8; + fixed_msrs[msr_num].lo |= + fixed_mtrr_types[type_index++] << 16; + fixed_msrs[msr_num].lo |= + fixed_mtrr_types[type_index++] << 24; + fixed_msrs[msr_num].hi |= + fixed_mtrr_types[type_index++] << 0; + fixed_msrs[msr_num].hi |= + fixed_mtrr_types[type_index++] << 8; + fixed_msrs[msr_num].hi |= + fixed_mtrr_types[type_index++] << 16; + fixed_msrs[msr_num].hi |= + fixed_mtrr_types[type_index++] << 24; + msr_num++; + } + } + + for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) { + printk(BIOS_DEBUG, "MTRR: Fixed MSR 0x%lx 0x%08x%08x\n", + msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); + wrmsr(msr_index[i], fixed_msrs[i]); } - return reg; + enable_cache(); } -static unsigned long resk(uint64_t value) +void x86_setup_fixed_mtrrs_no_enable(void) { - unsigned long resultk; - if (value < (1ULL << 42)) { - resultk = value >> 10; - } - else { - resultk = 0xffffffff; - } - return resultk; + calc_fixed_mtrrs(); + disable_fixed_mtrr(); + commit_fixed_mtrrs(); } -static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res) +void x86_setup_fixed_mtrrs(void) { - unsigned int start_mtrr; - unsigned int last_mtrr; - const unsigned char type = MTRR_TYPE_WRBACK | MTRR_FIXED_WRBACK_BITS; - start_mtrr = fixed_mtrr_index(resk(res->base)); - last_mtrr = fixed_mtrr_index(resk((res->base + res->size))); - if (start_mtrr >= NUM_FIXED_RANGES) { - return; - } - printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n", - start_mtrr, last_mtrr); - set_fixed_mtrrs(start_mtrr, last_mtrr, type); + x86_setup_fixed_mtrrs_no_enable(); + printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); + enable_fixed_mtrr(); } struct var_mtrr_state { - unsigned long range_startk, range_sizek; - unsigned int reg; - unsigned long hole_startk, hole_sizek; - unsigned int address_bits; - unsigned int above4gb; /* Set if MTRRs are needed for DRAM above 4GB */ + struct memory_ranges *addr_space; + int above4gb; + int address_bits; + int commit_mtrrs; + int mtrr_index; + int def_mtrr_type; }; -void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) +static void clear_var_mtrr(int index) { - struct var_mtrr_state *state = gp; - unsigned long basek, sizek; - if (state->reg >= bios_mtrrs) - return; + msr_t msr_val; - basek = resk(res->base); - sizek = resk(res->size); + msr_val = rdmsr(MTRRphysMask_MSR(index)); + msr_val.lo &= ~MTRRphysMaskValid; + wrmsr(MTRRphysMask_MSR(index), msr_val); +} - if (res->flags & IORESOURCE_UMA_FB) { - /* FIXME: could I use Write-Combining for Frame Buffer ? */ - state->reg = range_to_mtrr(state->reg, basek, sizek, 0, - MTRR_TYPE_UNCACHEABLE, state->address_bits, state->above4gb); +static void write_var_mtrr(struct var_mtrr_state *var_state, + uint32_t base, uint32_t size, int mtrr_type) +{ + msr_t msr_val; + unsigned long msr_index; + resource_t rbase; + resource_t rsize; + resource_t mask; + + /* Some variable MTRRs are attempted to be saved for the OS use. + * However, it's more important to try to map the full address space + * properly. */ + if (var_state->mtrr_index >= bios_mtrrs) + printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n"); + if (var_state->mtrr_index >= total_mtrrs) { + printk(BIOS_ERR, "ERROR: Not enough MTTRs available!\n"); return; } - if (res->flags & IORESOURCE_IGNORE_MTRR) { - return; - } + rbase = base; + rsize = size; - if (!(res->flags & IORESOURCE_CACHEABLE)) - return; + rbase = RANGE_TO_PHYS_ADDR(rbase); + rsize = RANGE_TO_PHYS_ADDR(rsize); + rsize = -rsize; - /* See if I can merge with the last range - * Either I am below 1M and the fixed mtrrs handle it, or - * the ranges touch. - */ - if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) { - unsigned long endk = basek + sizek; - state->range_sizek = endk - state->range_startk; - return; - } - /* Write the range mtrrs */ - if (state->range_sizek != 0) { - if (state->hole_sizek == 0 && state->above4gb != 2) { - /* We need to put that on to hole */ - unsigned long endk = basek + sizek; - state->hole_startk = state->range_startk + state->range_sizek; - state->hole_sizek = basek - state->hole_startk; - state->range_sizek = endk - state->range_startk; - return; - } - state->reg = range_to_mtrr(state->reg, state->range_startk, - state->range_sizek, basek, MTRR_TYPE_WRBACK, - state->address_bits, state->above4gb); - - state->reg = range_to_mtrr(state->reg, state->hole_startk, - state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, - state->address_bits, state->above4gb); - - state->range_startk = 0; - state->range_sizek = 0; - state->hole_startk = 0; - state->hole_sizek = 0; - } - /* Allocate an msr */ - printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); - state->range_startk = basek; - state->range_sizek = sizek; + mask = (1ULL << var_state->address_bits) - 1; + rsize = rsize & mask; + + printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", + var_state->mtrr_index, rbase, rsize, mtrr_type); + + msr_val.lo = rbase; + msr_val.lo |= mtrr_type; + + msr_val.hi = rbase >> 32; + msr_index = MTRRphysBase_MSR(var_state->mtrr_index); + wrmsr(msr_index, msr_val); + + msr_val.lo = rsize; + msr_val.lo |= MTRRphysMaskValid; + msr_val.hi = rsize >> 32; + msr_index = MTRRphysMask_MSR(var_state->mtrr_index); + wrmsr(msr_index, msr_val); } -void x86_setup_fixed_mtrrs_no_enable(void) +static void calc_var_mtrr_range(struct var_mtrr_state *var_state, + uint32_t base, uint32_t size, int mtrr_type) { - /* Try this the simple way of incrementally adding together - * mtrrs. If this doesn't work out we can get smart again - * and clear out the mtrrs. - */ - - printk(BIOS_DEBUG, "\n"); - /* Initialized the fixed_mtrrs to uncached */ - printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n", - 0, NUM_FIXED_RANGES); - set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); - - /* Now see which of the fixed mtrrs cover ram. - */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - set_fixed_mtrr_resource, NULL); - printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); + while (size != 0) { + uint32_t addr_lsb; + uint32_t size_msb; + uint32_t mtrr_size; + + addr_lsb = fls(base); + size_msb = fms(size); + + /* All MTRR entries need to have their base aligned to the mask + * size. The maximum size is calculated by a function of the + * min base bit set and maximum size bit set. */ + if (addr_lsb > size_msb) + mtrr_size = 1 << size_msb; + else + mtrr_size = 1 << addr_lsb; + + if (var_state->commit_mtrrs) + write_var_mtrr(var_state, base, mtrr_size, mtrr_type); + + size -= mtrr_size; + base += mtrr_size; + var_state->mtrr_index++; + } } -void x86_setup_fixed_mtrrs(void) +static void setup_var_mtrrs_by_state(struct var_mtrr_state *var_state) { - x86_setup_fixed_mtrrs_no_enable(); + struct memory_range *r; + + /* + * For each range that meets the non-default type process it in the + * following manner: + * +------------------+ c2 = end + * | 0 or more byes | + * +------------------+ b2 = c1 = round_down(end) + * | | + * +------------------+ b1 = a2 = round_up(begin) + * | 0 or more byes | + * +------------------+ a1 = begin + * + * Thus, there are 3 sub-ranges to configure variable MTRRs for. + */ + memory_ranges_each_entry(r, var_state->addr_space) { + uint32_t a1, a2, b1, b2, c1, c2; + int mtrr_type = memory_range_tag(r); + + /* Skip default type. */ + if (var_state->def_mtrr_type == mtrr_type) + continue; + + a1 = memory_range_base_mtrr_addr(r); + c2 = memory_range_end_mtrr_addr(r); + + /* The end address is under 1MiB. The fixed MTRRs take + * precedence over the variable ones. Therefore this range + * can be ignored. */ + if (c2 < RANGE_1MB) + continue; + + /* Again, the fixed MTRRs take precedence so the beginning + * of the range can be set to 0 if it starts below 1MiB. */ + if (a1 < RANGE_1MB) + a1 = 0; + + /* If the range starts above 4GiB the processing is done. */ + if (!var_state->above4gb && a1 >= RANGE_4GB) + break; - printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); - enable_fixed_mtrr(); -} + /* Clip the upper address to 4GiB if addresses above 4GiB + * are not being processed. */ + if (!var_state->above4gb && c2 > RANGE_4GB) + c2 = RANGE_4GB; + /* Don't align up or down on the range if it is smaller + * than the minimum granularity. */ + if ((c2 - a1) < MTRR_MIN_ALIGN) { + calc_var_mtrr_range(var_state, a1, c2 - a1, mtrr_type); + continue; + } -void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) -/* this routine needs to know how many address bits a given processor - * supports. CPUs get grumpy when you set too many bits in - * their mtrr registers :( I would generically call cpuid here - * and find out how many physically supported but some cpus are - * buggy, and report more bits then they actually support. - * If above4gb flag is set, variable MTRR ranges must be used to - * set cacheability of DRAM above 4GB. If above4gb flag is clear, - * some other mechanism is controlling cacheability of DRAM above 4GB. - */ + b1 = a2 = round_up(a1, MTRR_MIN_ALIGN); + b2 = c1 = round_down(c2, MTRR_MIN_ALIGN); + + calc_var_mtrr_range(var_state, a1, a2 - a1, mtrr_type); + calc_var_mtrr_range(var_state, b1, b2 - b1, mtrr_type); + calc_var_mtrr_range(var_state, c1, c2 - c1, mtrr_type); + } +} + +static int calc_var_mtrrs(struct memory_ranges *addr_space, + int above4gb, int address_bits) { - /* Try this the simple way of incrementally adding together - * mtrrs. If this doesn't work out we can get smart again - * and clear out the mtrrs. - */ + int wb_deftype_count; + int uc_deftype_count; struct var_mtrr_state var_state; - /* Cache as many memory areas as possible */ - /* FIXME is there an algorithm for computing the optimal set of mtrrs? - * In some cases it is definitely possible to do better. - */ - var_state.range_startk = 0; - var_state.range_sizek = 0; - var_state.hole_startk = 0; - var_state.hole_sizek = 0; - var_state.reg = 0; - var_state.address_bits = address_bits; + /* The default MTRR cacheability type is determined by calculating + * the number of MTTRs required for each MTTR type as if it was the + * default. */ + var_state.addr_space = addr_space; var_state.above4gb = above4gb; + var_state.address_bits = address_bits; + var_state.commit_mtrrs = 0; - /* Detect number of variable MTRRs */ - if (above4gb == 2) - detect_var_mtrrs(); - - search_global_resources(IORESOURCE_MEM, IORESOURCE_MEM, - set_var_mtrr_resource, &var_state); + var_state.mtrr_index = 0; + var_state.def_mtrr_type = MTRR_TYPE_WRBACK; + setup_var_mtrrs_by_state(&var_state); + wb_deftype_count = var_state.mtrr_index; - /* Write the last range */ - var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, - var_state.range_sizek, 0, MTRR_TYPE_WRBACK, - var_state.address_bits, var_state.above4gb); + var_state.mtrr_index = 0; + var_state.def_mtrr_type = MTRR_TYPE_UNCACHEABLE; + setup_var_mtrrs_by_state(&var_state); + uc_deftype_count = var_state.mtrr_index; - var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk, - var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, - var_state.address_bits, var_state.above4gb); + printk(BIOS_DEBUG, "MTRR: default type WB/UC MTRR counts: %d/%d.\n", + wb_deftype_count, uc_deftype_count); - printk(BIOS_DEBUG, "DONE variable MTRRs\n"); - printk(BIOS_DEBUG, "Clear out the extra MTRR's\n"); - /* Clear out the extra MTRR's */ - while(var_state.reg < total_mtrrs) { - set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); + if (wb_deftype_count < uc_deftype_count) { + printk(BIOS_DEBUG, "MTRR: WB selected as default type.\n"); + return MTRR_TYPE_WRBACK; } + printk(BIOS_DEBUG, "MTRR: UC selected as default type.\n"); + return MTRR_TYPE_UNCACHEABLE; +} + +static void commit_var_mtrrs(struct memory_ranges *addr_space, int def_type, + int above4gb, int address_bits) +{ + struct var_mtrr_state var_state; + int i; -#if CONFIG_CACHE_ROM + var_state.addr_space = addr_space; + var_state.above4gb = above4gb; + var_state.address_bits = address_bits; + /* Write the MSRs. */ + var_state.commit_mtrrs = 1; + var_state.mtrr_index = 0; + var_state.def_mtrr_type = def_type; + setup_var_mtrrs_by_state(&var_state); + + /* Clear all remaining variable MTTRs. */ + for (i = var_state.mtrr_index; i < total_mtrrs; i++) + clear_var_mtrr(i); + + #if CONFIG_CACHE_ROM /* Enable Caching and speculative Reads for the - * complete ROM now that we actually have RAM. - */ - if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(total_mtrrs - 1, (4096 - 8)*1024, 8 * 1024, - MTRR_TYPE_WRPROT, address_bits); + * complete ROM now that we actually have RAM. */ + if (boot_cpu() && acpi_slp_type != 3 && + var_state.mtrr_index != total_mtrrs) { + uint32_t size; + uint32_t base; + + /* Use the last MTRR for caching the BIOS image. */ + var_state.mtrr_index = total_mtrrs - 1; + + size = PHYS_TO_RANGE_ADDR(CONFIG_ROM_SIZE); + base = RANGE_4GB - size; + printk(BIOS_DEBUG, "Caching ROM as WP at 0x%llx\n", + RANGE_TO_PHYS_ADDR(base)); + write_var_mtrr(&var_state, base, size, MTRR_TYPE_WRPROT); } -#endif + #endif /* CONFIG_CACHE_ROM */ +} - printk(BIOS_SPEW, "call enable_var_mtrr()\n"); - enable_var_mtrr(); - printk(BIOS_SPEW, "Leave %s\n", __func__); - post_code(0x6A); +void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) +{ + static int var_mtrr_default_type = -1; + struct memory_ranges *addr_space; + + addr_space = get_physical_address_space(); + + if (var_mtrr_default_type == -1) { + if (above4gb == 2) + detect_var_mtrrs(); + var_mtrr_default_type = + calc_var_mtrrs(addr_space, !!above4gb, address_bits); + } + + disable_cache(); + commit_var_mtrrs(addr_space, var_mtrr_default_type, !!above4gb, + address_bits); + enable_var_mtrr(var_mtrr_default_type); + enable_cache(); } void x86_setup_mtrrs(void) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index fe85ad0..a896159 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -26,6 +26,7 @@ #define MTRRphysMaskValid (1 << 11) #define NUM_FIXED_RANGES 88 +#define RANGES_PER_FIXED_MTRR 8 #define MTRRfix64K_00000_MSR 0x250 #define MTRRfix16K_80000_MSR 0x258 #define MTRRfix16K_A0000_MSR 0x259 @@ -39,19 +40,10 @@ #define MTRRfix4K_F8000_MSR 0x26f #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) -#include <device/device.h> -/* You should almost NEVER use this function. - * N.B. We worked on a lot of ways to make this continue as static, - * but just making it available ended up being the simplest solution. - */ -void set_var_mtrr( - unsigned int reg, unsigned long basek, unsigned long sizek, - unsigned char type, unsigned address_bits); void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); void x86_setup_mtrrs(void); int x86_mtrr_check(void); -void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res); void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 4a043eb..b9a07a2 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -622,25 +622,12 @@ static void gma_pm_init_post_vbios(struct device *dev) static void gma_func0_init(struct device *dev) { u32 reg32; - u32 graphics_base, graphics_size; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - /* Set up an MTRR for the graphics memory BAR to vastly improve - * speed of VGA initialization (and later access). To stay out of - * the way of the MTRR init code, we are using MTRR #8 to cover - * that range. - */ - graphics_base = dev->resource_list[1].base; - graphics_size = dev->resource_list[1].size; - printk(BIOS_DEBUG, "Setting up MTRR for graphics 0x%08x (%dK)\n", - graphics_base, graphics_size / 1024); - set_var_mtrr(8, graphics_base >> 10, graphics_size >> 10, - MTRR_TYPE_WRCOMB, 0x24); - /* Init graphics power management */ gma_pm_init_pre_vbios(dev); @@ -655,10 +642,11 @@ static void gma_func0_init(struct device *dev) #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); - u32 iobase, mmiobase, physbase; + u32 iobase, mmiobase, physbase, graphics_base; iobase = dev->resource_list[2].base; mmiobase = dev->resource_list[0].base; physbase = pci_read_config32(dev, 0x5c) & ~0xf; + graphics_base = dev->resource_list[1].base; int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); i915lightup(physbase, iobase, mmiobase, graphics_base);

1 0

New patch to review for coreboot: 2006b1e lib: add memrange infrastructure
by Aaron Durbin 23 Mar '13

23 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2888 -gerrit commit 2006b1e08b8cfab4645c0b415e13cc9d8b0935bc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 20:44:46 2013 -0500 lib: add memrange infrastructure The memrange infrastructure allows for keeping track of the machine's physical address space. Each memory_range entry in a memory_ranges structure can be tagged with an arbitrary value. It supports merging and deleting ranges as well as filling in holes in the address space with a particular tag. The memrange infrastructure will serve as a shared implementation for address tracking by the MTRR and coreboot mem table code. Change-Id: Id5bea9d2a419114fca55c59af0fdca063551110e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/memrange.h | 101 +++++++++++++++++ src/lib/Makefile.inc | 1 + src/lib/memrange.c | 293 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 395 insertions(+) diff --git a/src/include/memrange.h b/src/include/memrange.h new file mode 100644 index 0000000..f087c83 --- /dev/null +++ b/src/include/memrange.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef MEMRANGE_H_ +#define MEMRANGE_H_ + +#include <device/resource.h> +#include <list.h> + +/* Each memory_range covers the inclusive addresses of [begin, end]. Even + * though the fields are exposed in this header file the wrapper functions + * below should be used for obtaining base, end, and size for forward API + * compatibility. */ +struct memory_range { + resource_t begin; + resource_t end; + struct list_head siblings; + unsigned long tag; +}; + +/* A memory_ranges structure consists of a list of memory_range(s). */ +struct memory_ranges { + struct list_head list; +}; + +/* Return inclusive base address of memory range. */ +static inline resource_t memory_range_base(const struct memory_range *r) +{ + return r->begin; +} + +/* Return exclusive end address of memory range. */ +static inline resource_t memory_range_end(const struct memory_range *r) +{ + return r->end + 1; +} + +/* Return size of of memory range. */ +static inline resource_t memory_range_size(const struct memory_range *r) +{ + return r->end - r->begin + 1; +} + +static inline unsigned long memory_range_tag(const struct memory_range *r) +{ + return r->tag; +} + +/* Iterate over each entry in a memory_ranges structure. Ranges cannot + * be deleted while processing each entry as the list cannot be safely + * traversed after such an operation. + * r - memory_range pointer. + * ranges - memory_rnages pointer */ +#define memory_ranges_each_entry(r, ranges) \ + list_for_each_entry(r, &(ranges)->list, siblings) + +/* Initialize and fill a memory_ranges structure according to the + * mask and match type for all memory resources. Tag each entry with the + * specified type. */ +void memory_ranges_init(struct memory_ranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag); + +/* Remove and free all entries within the memory_ranges structure. */ +void memory_ranges_teardown(struct memory_ranges *ranges); + +/* Add memory resources that match with the corresponding mask and match. + * Each entry will be tagged with the provided tag. */ +void memory_ranges_add_resources(struct memory_ranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag); + +/* Fill all address ranges not covered by an entry associated with tag. */ +void memory_ranges_fill_holes(struct memory_ranges *ranges, unsigned long tag); + +/* Delete a resource from the given memory_ranges. */ +void delete_memory_range(struct memory_ranges *ranges, + resource_t base, resource_t size); + +/* Insert a resource to the given memory_ranges. All existing ranges + * covered by range specified by base and size will be removed before a + * new one is added. */ +void insert_memory_range(struct memory_ranges *ranges, + resource_t base, resource_t size, unsigned long tag); + +#endif /* MEMRANGE_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 6193e63..e8ed4f4 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -85,6 +85,7 @@ ramstage-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c +ramstage-y += memrange.c # The CBMEM implementations are chosen based on CONFIG_DYNAMIC_CBMEM. ifeq ($(CONFIG_DYNAMIC_CBMEM),y) diff --git a/src/lib/memrange.c b/src/lib/memrange.c new file mode 100644 index 0000000..027d860 --- /dev/null +++ b/src/lib/memrange.c @@ -0,0 +1,293 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdlib.h> +#include <console/console.h> +#include <memrange.h> + +/* Coreboot doesn't have a free() function. Therefore, keep a cache of + * free'd entries. */ +static LIST_HEAD(free_list); + +static inline void memory_range_unlink(struct memory_range *r) +{ + list_del_init(&r->siblings); +} + +static struct memory_range *alloc_range(void) +{ + if (!list_empty(&free_list)) { + struct memory_range *r; + + r = list_first_entry(&free_list, struct memory_range, siblings); + memory_range_unlink(r); + return r; + } + return malloc(sizeof(struct memory_range)); +} + +static void memory_range_free(struct memory_range *e) +{ + if (!list_empty(&e->siblings)) + printk(BIOS_ERR, "Freeing linked memory_range!\n"); + list_add(&free_list, &e->siblings); +} + +static inline struct memory_range * +range_list_add(struct list_head *head, resource_t begin, resource_t end, + unsigned long tag) +{ + struct memory_range *new_entry; + + new_entry = alloc_range(); + if (new_entry == NULL) { + printk(BIOS_ERR, "Could not allocate memory_range!\n"); + return NULL; + } + new_entry->begin = begin; + new_entry->end = end; + new_entry->tag = tag; + list_add(&new_entry->siblings, head); + + return new_entry; +} + +static void merge_neighbor_entries(struct memory_ranges *ranges) +{ + struct memory_range *cur; + struct memory_range *prev; + struct memory_range *tmp; + + prev = NULL; + /* Merge all neighbors and delete/free the leftover entry. */ + list_for_each_entry_safe(cur, tmp, &ranges->list, siblings) { + /* First entry. Just set prev. */ + if (prev == NULL) { + prev = cur; + continue; + } + + /* If the previous entry merges with the current update the + * previous entry to cover full range and delete current from + * the list. */ + if (prev->end + 1 >= cur->begin && prev->tag == cur->tag) { + prev->end = cur->end; + memory_range_unlink(cur); + memory_range_free(cur); + continue; + } + + prev = cur; + } +} + +static void remove_memory_range(struct memory_ranges *ranges, + resource_t begin, resource_t end, + unsigned long unused) +{ + struct memory_range *cur; + struct memory_range *tmp; + + list_for_each_entry_safe(cur, tmp, &ranges->list, siblings) { + resource_t tmp_end; + + /* No other ranges are affected. */ + if (end < cur->begin) + break; + + /* The removal range starts after this one. */ + if (begin > cur->end) + continue; + + /* The removal range overlaps with the current entry either + * partially or fully. However, we need to adjust the removal + * range for any holes. */ + if (begin <= cur->begin) { + begin = cur->begin; + + /* Full removal. */ + if (end >= cur->end) { + begin = cur->end + 1; + memory_range_unlink(cur); + memory_range_free(cur); + continue; + } + } + + /* Clip the end fragment to do proper splitting. */ + tmp_end = end; + if (end > cur->end) + tmp_end = cur->end; + + /* Hole punched in middle of entry. */ + if (begin > cur->begin && tmp_end < cur->end) { + range_list_add(&cur->siblings, end + 1, cur->end, + cur->tag); + cur->end = begin - 1; + continue; + } + + /* Removal at beginning. */ + if (begin == cur->begin) + cur->begin = tmp_end + 1; + + /* Removal at end. */ + if (tmp_end == cur->end) + cur->end = begin - 1; + } +} + +static void merge_add_memory_range(struct memory_ranges *ranges, + resource_t begin, resource_t end, + unsigned long tag) +{ + struct memory_range *cur; + struct list_head *head; + + head = &ranges->list; + + /* Remove all existing entries covered by the range. */ + remove_memory_range(ranges, begin, end, -1); + + /* Find the entry to place the new entry after. Since + * remove_memory_range() was called above there is a guranteed + * spot for this new entry. */ + list_for_each_entry(cur, &ranges->list, siblings) { + /* Found insertion spot before current entry. */ + if (end < cur->begin) + break; + + /* Keep track of previous entry to insert new entry after it. */ + head = &cur->siblings; + + /* The new entry starts after this one. */ + if (begin > cur->end) + continue; + + } + + /* Add new entry and merge with neighbors. */ + range_list_add(head, begin, end, tag); + merge_neighbor_entries(ranges); +} + +typedef void (*range_action_t)(struct memory_ranges *ranges, + resource_t begin, resource_t end, + unsigned long tag); + +static void do_action(struct memory_ranges *ranges, + resource_t base, resource_t size, unsigned long tag, + range_action_t action) +{ + resource_t end; + resource_t begin; + + /* The addresses are aligned to 4096 bytes: the begin address is + * aligned down while the end address is aligned up to be conservative + * about the full range covered. */ + begin = round_down(base, 4096); + end = begin + size + (base - begin); + end = round_up(end, 4096) - 1; + action(ranges, begin, end, tag); +} + +void delete_memory_range(struct memory_ranges *ranges, + resource_t base, resource_t size) +{ + do_action(ranges, base, size, -1, remove_memory_range); +} + +void insert_memory_range(struct memory_ranges *ranges, + resource_t base, resource_t size, unsigned long tag) +{ + do_action(ranges, base, size, tag, merge_add_memory_range); +} + +struct collect_context { + struct memory_ranges *ranges; + unsigned long tag; +}; + +static void collect_ranges(void *gp, struct device *dev, struct resource *res) +{ + struct collect_context *ctx = gp; + + insert_memory_range(ctx->ranges, res->base, res->size, ctx->tag); +} + +void memory_ranges_add_resources(struct memory_ranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag) +{ + struct collect_context context; + + /* Only deal with MEM resources. */ + mask |= IORESOURCE_MEM; + match |= IORESOURCE_MEM; + + context.ranges = ranges; + context.tag = tag; + search_global_resources(mask, match, collect_ranges, &context); +} + +void memory_ranges_init(struct memory_ranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag) +{ + INIT_LIST_HEAD(&ranges->list); + + memory_ranges_add_resources(ranges, mask, match, tag); +} + +void memory_ranges_teardown(struct memory_ranges *ranges) +{ + struct memory_range *cur; + struct memory_range *tmp; + + /* Merge all neighbors and delete/free the leftover entry. */ + list_for_each_entry_safe(cur, tmp, &ranges->list, siblings) { + memory_range_unlink(cur); + memory_range_free(cur); + } +} + +void memory_ranges_fill_holes(struct memory_ranges *ranges, unsigned long tag) +{ + struct memory_range *cur; + struct memory_range *prev; + struct memory_range *tmp; + + prev = NULL; + list_for_each_entry_safe(cur, tmp, &ranges->list, siblings) { + /* First entry. Just set prev. */ + if (prev == NULL) { + prev = cur; + continue; + } + + /* If the previous entry does not directly preceed the current + * entry then add a new entry just after the previous one. */ + if (prev->end + 1 != cur->begin) + range_list_add(&prev->siblings, prev->end + 1, + cur->begin - 1, tag); + + prev = cur; + } + /* Merge all entries that were newly added. */ + merge_neighbor_entries(ranges); +}

1 0

New patch to review for coreboot: 5ff7232 coreboot: add linux utilities
by Aaron Durbin 23 Mar '13

23 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2887 -gerrit commit 5ff7232c676cc7c8147c261b412ed6db6fec3eb1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 20:37:04 2013 -0500 coreboot: add linux utilities The linux kernel has some helpful data structures and functions defined. util.h is a copy of kernel.h with the kernel-specific bits removed. list.h is the kernel's linked list implementation. These headers are going to be used in subsequent patches. Change-Id: Ic8b991ba855ea53a1e6936edab3c0a962724fa43 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/list.h | 740 +++++++++++++++++++++++++++++++++++++++++++++++++++++ src/include/util.h | 258 +++++++++++++++++++ 2 files changed, 998 insertions(+) diff --git a/src/include/list.h b/src/include/list.h new file mode 100644 index 0000000..67c10e3 --- /dev/null +++ b/src/include/list.h @@ -0,0 +1,740 @@ +#ifndef _LINUX_LIST_H +#define _LINUX_LIST_H + +/* Linux kernel linked list support. */ +#include <stddef.h> +#include <util.h> + +struct list_head { + struct list_head *next, *prev; +}; + +struct hlist_head { + struct hlist_node *first; +}; + +struct hlist_node { + struct hlist_node *next, **pprev; +}; + +# define POISON_POINTER_DELTA 0 + +/* + * These are non-NULL pointers that will result in page faults + * under normal circumstances, used to verify that nobody uses + * non-initialized list entries. + */ +#define LIST_POISON1 ((void *) 0x00100100 + POISON_POINTER_DELTA) +#define LIST_POISON2 ((void *) 0x00200200 + POISON_POINTER_DELTA) + +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +static inline void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +#ifndef CONFIG_DEBUG_LIST +static inline void __list_add(struct list_head *new, + struct list_head *prev, + struct list_head *next) +{ + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; +} +#else +extern void __list_add(struct list_head *new, + struct list_head *prev, + struct list_head *next); +#endif + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +static inline void list_add(struct list_head *new, struct list_head *head) +{ + __list_add(new, head, head->next); +} + + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *new, struct list_head *head) +{ + __list_add(new, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_del(struct list_head * prev, struct list_head * next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, the entry is + * in an undefined state. + */ +#ifndef CONFIG_DEBUG_LIST +static inline void __list_del_entry(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); +} + +static inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = LIST_POISON1; + entry->prev = LIST_POISON2; +} +#else +extern void __list_del_entry(struct list_head *entry); +extern void list_del(struct list_head *entry); +#endif + +/** + * list_replace - replace old entry by new one + * @old : the element to be replaced + * @new : the new element to insert + * + * If @old was empty, it will be overwritten. + */ +static inline void list_replace(struct list_head *old, + struct list_head *new) +{ + new->next = old->next; + new->next->prev = new; + new->prev = old->prev; + new->prev->next = new; +} + +static inline void list_replace_init(struct list_head *old, + struct list_head *new) +{ + list_replace(old, new); + INIT_LIST_HEAD(old); +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static inline void list_del_init(struct list_head *entry) +{ + __list_del_entry(entry); + INIT_LIST_HEAD(entry); +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +static inline void list_move(struct list_head *list, struct list_head *head) +{ + __list_del_entry(list); + list_add(list, head); +} + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +static inline void list_move_tail(struct list_head *list, + struct list_head *head) +{ + __list_del_entry(list); + list_add_tail(list, head); +} + +/** + * list_is_last - tests whether @list is the last entry in list @head + * @list: the entry to test + * @head: the head of the list + */ +static inline int list_is_last(const struct list_head *list, + const struct list_head *head) +{ + return list->next == head; +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(const struct list_head *head) +{ + return head->next == head; +} + +/** + * list_empty_careful - tests whether a list is empty and not being modified + * @head: the list to test + * + * Description: + * tests whether a list is empty _and_ checks that no other CPU might be + * in the process of modifying either member (next or prev) + * + * NOTE: using list_empty_careful() without synchronization + * can only be safe if the only activity that can happen + * to the list entry is list_del_init(). Eg. it cannot be used + * if another CPU could re-list_add() it. + */ +static inline int list_empty_careful(const struct list_head *head) +{ + struct list_head *next = head->next; + return (next == head) && (next == head->prev); +} + +/** + * list_rotate_left - rotate the list to the left + * @head: the head of the list + */ +static inline void list_rotate_left(struct list_head *head) +{ + struct list_head *first; + + if (!list_empty(head)) { + first = head->next; + list_move_tail(first, head); + } +} + +/** + * list_is_singular - tests whether a list has just one entry. + * @head: the list to test. + */ +static inline int list_is_singular(const struct list_head *head) +{ + return !list_empty(head) && (head->next == head->prev); +} + +static inline void __list_cut_position(struct list_head *list, + struct list_head *head, struct list_head *entry) +{ + struct list_head *new_first = entry->next; + list->next = head->next; + list->next->prev = list; + list->prev = entry; + entry->next = list; + head->next = new_first; + new_first->prev = head; +} + +/** + * list_cut_position - cut a list into two + * @list: a new list to add all removed entries + * @head: a list with entries + * @entry: an entry within head, could be the head itself + * and if so we won't cut the list + * + * This helper moves the initial part of @head, up to and + * including @entry, from @head to @list. You should + * pass on @entry an element you know is on @head. @list + * should be an empty list or a list you do not care about + * losing its data. + * + */ +static inline void list_cut_position(struct list_head *list, + struct list_head *head, struct list_head *entry) +{ + if (list_empty(head)) + return; + if (list_is_singular(head) && + (head->next != entry && head != entry)) + return; + if (entry == head) + INIT_LIST_HEAD(list); + else + __list_cut_position(list, head, entry); +} + +static inline void __list_splice(const struct list_head *list, + struct list_head *prev, + struct list_head *next) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + + first->prev = prev; + prev->next = first; + + last->next = next; + next->prev = last; +} + +/** + * list_splice - join two lists, this is designed for stacks + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice(const struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head, head->next); +} + +/** + * list_splice_tail - join two lists, each list being a queue + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice_tail(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head->prev, head); +} + +/** + * list_splice_init - join two lists and reinitialise the emptied list. + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * The list at @list is reinitialised + */ +static inline void list_splice_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head, head->next); + INIT_LIST_HEAD(list); + } +} + +/** + * list_splice_tail_init - join two lists and reinitialise the emptied list + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * Each of the lists is a queue. + * The list at @list is reinitialised + */ +static inline void list_splice_tail_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head->prev, head); + INIT_LIST_HEAD(list); + } +} + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + container_of(ptr, type, member) + +/** + * list_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->next, type, member) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * __list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + * + * This variant doesn't differ from list_for_each() any more. + * We don't do prefetching in either case. + */ +#define __list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; \ + pos != (head); \ + pos = n, n = pos->prev) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_reverse - iterate backwards over list of given type. + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_reverse(pos, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() + * @pos: the type * to use as a start point + * @head: the head of the list + * @member: the name of the list_struct within the struct. + * + * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). + */ +#define list_prepare_entry(pos, head, member) \ + ((pos) ? : list_entry(head, typeof(*pos), member)) + +/** + * list_for_each_entry_continue - continue iteration over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Continue to iterate over list of given type, continuing after + * the current position. + */ +#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_continue_reverse - iterate backwards from the given point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Start to iterate over list of given type backwards, continuing after + * the current position. + */ +#define list_for_each_entry_continue_reverse(pos, head, member) \ + for (pos = list_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_for_each_entry_from - iterate over list of given type from the current point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing from current position. + */ +#define list_for_each_entry_from(pos, head, member) \ + for (; &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_continue - continue list iteration safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing after current point, + * safe against removal of list entry. + */ +#define list_for_each_entry_safe_continue(pos, n, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_from - iterate over list from current point safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type from current point, safe against + * removal of list entry. + */ +#define list_for_each_entry_safe_from(pos, n, head, member) \ + for (n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_reverse - iterate backwards over list safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate backwards over list of given type, safe against removal + * of list entry. + */ +#define list_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member), \ + n = list_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.prev, typeof(*n), member)) + +/** + * list_safe_reset_next - reset a stale list_for_each_entry_safe loop + * @pos: the loop cursor used in the list_for_each_entry_safe loop + * @n: temporary storage used in list_for_each_entry_safe + * @member: the name of the list_struct within the struct. + * + * list_safe_reset_next is not safe to use in general if the list may be + * modified concurrently (eg. the lock is dropped in the loop body). An + * exception to this is if the cursor element (pos) is pinned in the list, + * and list_safe_reset_next is called after re-taking the lock and before + * completing the current iteration of the loop body. + */ +#define list_safe_reset_next(pos, n, member) \ + n = list_entry(pos->member.next, typeof(*pos), member) + +/* + * Double linked lists with a single pointer list head. + * Mostly useful for hash tables where the two pointer list head is + * too wasteful. + * You lose the ability to access the tail in O(1). + */ + +#define HLIST_HEAD_INIT { .first = NULL } +#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } +#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) +static inline void INIT_HLIST_NODE(struct hlist_node *h) +{ + h->next = NULL; + h->pprev = NULL; +} + +static inline int hlist_unhashed(const struct hlist_node *h) +{ + return !h->pprev; +} + +static inline int hlist_empty(const struct hlist_head *h) +{ + return !h->first; +} + +static inline void __hlist_del(struct hlist_node *n) +{ + struct hlist_node *next = n->next; + struct hlist_node **pprev = n->pprev; + *pprev = next; + if (next) + next->pprev = pprev; +} + +static inline void hlist_del(struct hlist_node *n) +{ + __hlist_del(n); + n->next = LIST_POISON1; + n->pprev = LIST_POISON2; +} + +static inline void hlist_del_init(struct hlist_node *n) +{ + if (!hlist_unhashed(n)) { + __hlist_del(n); + INIT_HLIST_NODE(n); + } +} + +static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) +{ + struct hlist_node *first = h->first; + n->next = first; + if (first) + first->pprev = &n->next; + h->first = n; + n->pprev = &h->first; +} + +/* next must be != NULL */ +static inline void hlist_add_before(struct hlist_node *n, + struct hlist_node *next) +{ + n->pprev = next->pprev; + n->next = next; + next->pprev = &n->next; + *(n->pprev) = n; +} + +static inline void hlist_add_after(struct hlist_node *n, + struct hlist_node *next) +{ + next->next = n->next; + n->next = next; + next->pprev = &n->next; + + if(next->next) + next->next->pprev = &next->next; +} + +/* after that we'll appear to be on some hlist and hlist_del will work */ +static inline void hlist_add_fake(struct hlist_node *n) +{ + n->pprev = &n->next; +} + +/* + * Move a list from one list head to another. Fixup the pprev + * reference of the first entry if it exists. + */ +static inline void hlist_move_list(struct hlist_head *old, + struct hlist_head *new) +{ + new->first = old->first; + if (new->first) + new->first->pprev = &new->first; + old->first = NULL; +} + +#define hlist_entry(ptr, type, member) container_of(ptr,type,member) + +#define hlist_for_each(pos, head) \ + for (pos = (head)->first; pos ; pos = pos->next) + +#define hlist_for_each_safe(pos, n, head) \ + for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \ + pos = n) + +/** + * hlist_for_each_entry - iterate over list of given type + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry(tpos, pos, head, member) \ + for (pos = (head)->first; \ + pos && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = pos->next) + +/** + * hlist_for_each_entry_continue - iterate over a hlist continuing after current point + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry_continue(tpos, pos, member) \ + for (pos = (pos)->next; \ + pos && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = pos->next) + +/** + * hlist_for_each_entry_from - iterate over a hlist continuing from current point + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry_from(tpos, pos, member) \ + for (; pos && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = pos->next) + +/** + * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @n: another &struct hlist_node to use as temporary storage + * @head: the head for your list. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \ + for (pos = (head)->first; \ + pos && ({ n = pos->next; 1; }) && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = n) + +#endif diff --git a/src/include/util.h b/src/include/util.h new file mode 100644 index 0000000..e710ca8 --- /dev/null +++ b/src/include/util.h @@ -0,0 +1,258 @@ +#ifndef _LINUX_KERNEL_H +#define _LINUX_KERNEL_H + +#include <stdint.h> + +#define BITS_PER_LONG 32 +/* This code is taken from the linux kernel, kernel.h, with some function + * definitions and other non-applicable items culled out. */ + +#define USHRT_MAX ((u16)(~0U)) +#define SHRT_MAX ((s16)(USHRT_MAX>>1)) +#define SHRT_MIN ((s16)(-SHRT_MAX - 1)) +#define INT_MAX ((int)(~0U>>1)) +#define INT_MIN (-INT_MAX - 1) +#define UINT_MAX (~0U) +#define LONG_MAX ((long)(~0UL>>1)) +#define LONG_MIN (-LONG_MAX - 1) +#define ULONG_MAX (~0UL) +#define LLONG_MAX ((long long)(~0ULL>>1)) +#define LLONG_MIN (-LLONG_MAX - 1) +#define ULLONG_MAX (~0ULL) +#define SIZE_MAX (~(size_t)0) + +#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) + +/* + * This looks more complex than it should be. But we need to + * get the type for the ~ right in round_down (it needs to be + * as wide as the result!), and we want to evaluate the macro + * arguments just once each. + */ +#define __round_mask(x, y) ((__typeof__(x))((y)-1)) +#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) +#define round_down(x, y) ((x) & ~__round_mask(x, y)) + +#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f)) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) +#define DIV_ROUND_UP_ULL(ll,d) \ + ({ unsigned long long _tmp = (ll)+(d)-1; do_div(_tmp, d); _tmp; }) + +#if BITS_PER_LONG == 32 +# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP_ULL(ll, d) +#else +# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP(ll,d) +#endif + +/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */ +#define roundup(x, y) ( \ +{ \ + const typeof(y) __y = y; \ + (((x) + (__y - 1)) / __y) * __y; \ +} \ +) +#define rounddown(x, y) ( \ +{ \ + typeof(x) __x = (x); \ + __x - (__x % (y)); \ +} \ +) +#define DIV_ROUND_CLOSEST(x, divisor)( \ +{ \ + typeof(divisor) __divisor = divisor; \ + (((x) + ((__divisor) / 2)) / (__divisor)); \ +} \ +) + +/* + * Multiplies an integer by a fraction, while avoiding unnecessary + * overflow or loss of precision. + */ +#define mult_frac(x, numer, denom)( \ +{ \ + typeof(x) quot = (x) / (denom); \ + typeof(x) rem = (x) % (denom); \ + (quot * (numer)) + ((rem * (numer)) / (denom)); \ +} \ +) + + +/** + * upper_32_bits - return bits 32-63 of a number + * @n: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >= width of type" warning when that quantity is + * 32-bits. + */ +#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) + +/** + * lower_32_bits - return bits 0-31 of a number + * @n: the number we're accessing + */ +#define lower_32_bits(n) ((u32)(n)) + +#define might_sleep_if(cond) do { if (cond) might_sleep(); } while (0) + +/* + * abs() handles unsigned and signed longs, ints, shorts and chars. For all + * input types abs() returns a signed long. + * abs() should not be used for 64-bit types (s64, u64, long long) - use abs64() + * for those. + */ +#define abs(x) ({ \ + long ret; \ + if (sizeof(x) == sizeof(long)) { \ + long __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } else { \ + int __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } \ + ret; \ + }) + +#define abs64(x) ({ \ + s64 __x = (x); \ + (__x < 0) ? -__x : __x; \ + }) + +/* + * min()/max()/clamp() macros that also do + * strict type-checking.. See the + * "unnecessary" pointer comparison. + */ +#define min(x, y) ({ \ + typeof(x) _min1 = (x); \ + typeof(y) _min2 = (y); \ + (void) (&_min1 == &_min2); \ + _min1 < _min2 ? _min1 : _min2; }) + +#define max(x, y) ({ \ + typeof(x) _max1 = (x); \ + typeof(y) _max2 = (y); \ + (void) (&_max1 == &_max2); \ + _max1 > _max2 ? _max1 : _max2; }) + +#define min3(x, y, z) ({ \ + typeof(x) _min1 = (x); \ + typeof(y) _min2 = (y); \ + typeof(z) _min3 = (z); \ + (void) (&_min1 == &_min2); \ + (void) (&_min1 == &_min3); \ + _min1 < _min2 ? (_min1 < _min3 ? _min1 : _min3) : \ + (_min2 < _min3 ? _min2 : _min3); }) + +#define max3(x, y, z) ({ \ + typeof(x) _max1 = (x); \ + typeof(y) _max2 = (y); \ + typeof(z) _max3 = (z); \ + (void) (&_max1 == &_max2); \ + (void) (&_max1 == &_max3); \ + _max1 > _max2 ? (_max1 > _max3 ? _max1 : _max3) : \ + (_max2 > _max3 ? _max2 : _max3); }) + +/** + * min_not_zero - return the minimum that is _not_ zero, unless both are zero + * @x: value1 + * @y: value2 + */ +#define min_not_zero(x, y) ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + __x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); }) + +/** + * clamp - return a value clamped to a given range with strict typechecking + * @val: current value + * @min: minimum allowable value + * @max: maximum allowable value + * + * This macro does strict typechecking of min/max to make sure they are of the + * same type as val. See the unnecessary pointer comparisons. + */ +#define clamp(val, min, max) ({ \ + typeof(val) __val = (val); \ + typeof(min) __min = (min); \ + typeof(max) __max = (max); \ + (void) (&__val == &__min); \ + (void) (&__val == &__max); \ + __val = __val < __min ? __min: __val; \ + __val > __max ? __max: __val; }) + +/* + * ..and if you can't take the strict + * types, you can specify one yourself. + * + * Or not use min/max/clamp at all, of course. + */ +#define min_t(type, x, y) ({ \ + type __min1 = (x); \ + type __min2 = (y); \ + __min1 < __min2 ? __min1: __min2; }) + +#define max_t(type, x, y) ({ \ + type __max1 = (x); \ + type __max2 = (y); \ + __max1 > __max2 ? __max1: __max2; }) + +/** + * clamp_t - return a value clamped to a given range using a given type + * @type: the type of variable to use + * @val: current value + * @min: minimum allowable value + * @max: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of type + * 'type' to make all the comparisons. + */ +#define clamp_t(type, val, min, max) ({ \ + type __val = (val); \ + type __min = (min); \ + type __max = (max); \ + __val = __val < __min ? __min: __val; \ + __val > __max ? __max: __val; }) + +/** + * clamp_val - return a value clamped to a given range using val's type + * @val: current value + * @min: minimum allowable value + * @max: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of whatever + * type the input argument 'val' is. This is useful when val is an unsigned + * type and min and max are literals that will otherwise be assigned a signed + * integer type. + */ +#define clamp_val(val, min, max) ({ \ + typeof(val) __val = (val); \ + typeof(val) __min = (min); \ + typeof(val) __max = (max); \ + __val = __val < __min ? __min: __val; \ + __val > __max ? __max: __val; }) + + +/* + * swap - swap value of @a and @b + */ +#define swap(a, b) \ + do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +/* Trap pasters of __FUNCTION__ at compile-time */ +#define __FUNCTION__ (__func__) + + +#endif

1 0

New patch to review for coreboot: 3f476d8 resources: introduce reserved_ram_resource()
by Aaron Durbin 23 Mar '13

23 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2886 -gerrit commit 3f476d86eab0f1d458b77be1f9f92a6f92d8d6b8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:03:09 2013 -0500 resources: introduce reserved_ram_resource() mmio_resource() was previously being used for reserving RAM from the OS by using IORESOURCE_IGNORE_MTRR atrribute. Instead, be more explicit for those uses with reserved_ram_resource(). bad_ram_resource() now calls reserved_ram_resource(). Those resources are marked as cacheable but reserved. The sandybridge and haswell code were relying on the implementation fo the MTRR algorithm's interaction for reserved regions. Instead be explicit about what ranges are MMIO reserved and what are RAM reserved. Change-Id: I1e47026970fb37c0305e4d49a12c98b0cdd1abe5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/device/device.h | 5 ++++- src/northbridge/intel/haswell/northbridge.c | 21 ++++++++++----------- src/northbridge/intel/sandybridge/northbridge.c | 8 ++++++-- 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/src/include/device/device.h b/src/include/device/device.h index 5219310..b8dfbf5 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -206,8 +206,11 @@ void fixed_mem_resource(device_t dev, unsigned long index, #define ram_resource(dev, idx, basek, sizek) \ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE) +#define reserved_ram_resource(dev, idx, basek, sizek) \ + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE | IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) + #define bad_ram_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) + reserved_ram_resource((dev), (idx), (basek), (sizek)) #define uma_resource(dev, idx, basek, sizek) \ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index b57b28e..16196ad 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -53,15 +53,6 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -/* Reserve everything between A segment and 1MB: - * - * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) - * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI - */ -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; - void cbmem_post_handling(void) { update_mrc_cache(); @@ -414,9 +405,17 @@ static void mc_add_dram_resources(device_t dev) if (size_k > 0) ram_resource(dev, index++, base_k, size_k); - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); + /* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), + (0x100000 - 0xc0000) >> 10); #if CONFIG_CHROMEOS_RAMOOPS - mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, + reserved_ram_resource(dev, index++, + CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 13390bd..c39933f 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -127,10 +127,14 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); + mmio_resource(dev, index++, legacy_hole_base_k, + (0xc0000 >> 10) - legacy_hole_base_k); + reserved_ram_resource(dev, index++, 0xc0000 >> 10, + (0x100000 - 0xc0000) >> 10); #if CONFIG_CHROMEOS_RAMOOPS - mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, + reserved_ram_resource(dev, index++, + CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif

1 0

Patch set updated for coreboot: 0790bd8 armv7: add new dcache and MMU setup functions
by David Hendricks 23 Mar '13

23 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2877 -gerrit commit 0790bd842dd46ed5305d11e3341537d95620e765 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 21 21:58:50 2013 -0700 armv7: add new dcache and MMU setup functions ** do not submit ** This is a work-in-progress patch. This adds new MMU setup code which uses cbmem_add() to determine the translation table base address, which in turn helps our payload to avoid clobbering the page table. Right now it dies when cbmem_toc is accessed in cbmem_reinit(). Sounds like I'm not setting up permissions correctly or something. Hmmmmm... Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/Kconfig | 1 + src/arch/armv7/bootblock_simple.c | 6 +- src/arch/armv7/include/arch/cache.h | 32 ++++++++++ src/arch/armv7/lib/Makefile.inc | 1 + src/arch/armv7/lib/cache.c | 29 ++++++--- src/arch/armv7/lib/mmu.c | 119 +++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 3 +- src/mainboard/google/snow/romstage.c | 10 ++- 8 files changed, 190 insertions(+), 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 18b5bad..f15c32d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -225,6 +225,7 @@ config ARCH_X86 config ARCH_ARMV7 bool default n + select EARLY_CBMEM_INIT # Warning: The file is included whether or not the if is here. # but the if controls how the evaluation occurs. diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index ad25b41..0a5d6c3 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -53,12 +53,14 @@ void main(void) armv7_invalidate_caches(); /* - * Re-enable caches and branch prediction. MMU will be set up later. + * Re-enable icache and branch prediction. Dcache and MMU will be + * set up in romstage along with DRAM. + * * Note: If booting from USB, we need to disable branch prediction * before copying from USB into RAM (FIXME: why?) */ sctlr = read_sctlr(); - sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I; + sctlr |= SCTLR_Z | SCTLR_I; write_sctlr(sctlr); if (boot_cpu()) { diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index c003256..1d7518f 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -108,6 +108,32 @@ static inline void tlbiall(void) asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); } +/* write data access control register (DACR) */ +static inline void write_dacr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val)); +} + +/* write translation table base register 0 (TTBR0) */ +static inline void write_ttbr0(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory"); +} + +/* read translation table base control register (TTBCR) */ +static inline uint32_t read_ttbcr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val)); + return val; +} + +/* write translation table base control register (TTBCR) */ +static inline void write_ttbcr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory"); +} + /* * Low-level cache maintenance operations */ @@ -224,6 +250,12 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* dcache and MMU disable */ +void dcache_mmu_disable(void); + +/* dcache and MMU enable */ +void dcache_mmu_enable(void); + /* icache invalidate all (on current level given by CSSELR) */ void icache_invalidate_all(void); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index c248b9e..de41f7f 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += cache-cp15.c romstage-y += cache.c romstage-y += cache_v7.c romstage-y += cache-cp15.c +romstage-y += mmu.c romstage-y += div0.c romstage-y += syslib.c romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 63e406c..2686db7 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -204,6 +204,28 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) dcache_op_mva(addr, len, OP_DCCIMVAC); } + +void dcache_mmu_disable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr &= ~(SCTLR_C | SCTLR_M); + write_sctlr(sctlr); +} + + +void dcache_mmu_enable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr |= SCTLR_C | SCTLR_M; + write_sctlr(sctlr); +} + void armv7_invalidate_caches(void) { uint32_t clidr; @@ -252,10 +274,3 @@ void armv7_invalidate_caches(void) /* Invalidate TLB */ tlb_invalidate_all(); } - -/* FIXME: wrapper around imported mmu_setup() for now */ -extern void mmu_setup(unsigned long start, unsigned long size); -void mmu_setup_by_mva(unsigned long start, unsigned long size) -{ - mmu_setup(start, size); -} diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c new file mode 100644 index 0000000..eb66186 --- /dev/null +++ b/src/arch/armv7/lib/mmu.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <types.h> +#include <stdlib.h> + +#include <cbmem.h> +#include <console/console.h> + +#include <arch/cache.h> + +#define L1_TLB_ENTRIES 4096 + +void mmu_setup_by_mva(unsigned long dram_start_mb, unsigned long dram_size_mb) +{ + int i; + uintptr_t ttb_addr; + unsigned int ttb_size; + uint32_t *p; + uint32_t attr; + uint32_t ttbcr; + + /* + * For coreboot's purposes, we will create a simple L1 page table + * in RAM with 1MB section translation entries over the 4GB address + * space. + * (ref: section 10.2 and example 15-4 in Cortex-A series + * programmer's guide) + * + * FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to + * 512 bytes. So add double the space in cbmem and fix-up the pointer. + */ + ttb_size = L1_TLB_ENTRIES * sizeof(int); + ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size * 2); + ttb_addr = ALIGN(ttb_addr + ttb_size, ttb_size); + p = (uint32_t *)ttb_addr; + + /* + * Section entry bits: + * 31:20 - section base address + * 18 - 0 to indicate normal section (versus supersection) + * 17 - nG, 0 to indicate page is global + * 16 - S, 0 for non-shareable (?) + * 15 - APX, 0 for full access + * 14:12 - TEX, 0b000 for outer and inner write-back + * 11:10 - AP, 0b11 for full access + * 9 - P, ? (FIXME: not described or possibly obsolete?) + * 8: 5 - Domain + * 4 - XN, 1 to set execute-never (and also avoid prefetches) + * 3 - C, 1 for cacheable + * 2 - B, 1 for bufferable + * 1: 0 - 0b10 to indicate section entry + */ + printk(BIOS_DEBUG, "%s: Writing page table @ to 0x%p\n", __func__, p); + printk(BIOS_DEBUG, "%s: Non-cachable region: page table @ to 0x%p\n", __func__, p); + + /* + * Non-DRAM pages are non-cacheable. Since this may correspond to read- + * sensitive regions (ie MMIO), mark as XN to disable speculative + * prefetching. + */ + attr = (0x3 << 10) | (1 << 4) | 0x2; + for (i = 0; i < dram_start_mb; i++) + p[i] = (i << 20) | attr; + + for (i = dram_start_mb + dram_size_mb; i < L1_TLB_ENTRIES; i++) + p[i] = (i << 20) | attr; + + /* DRAM portion will be write-back for coreboot */ + attr = (0x3 << 10) | (1 << 4) | (1 << 3) | (1 << 2) | 0x2; + for (i = dram_start_mb; i < dram_size_mb; i++) + p[i] = (i << 20) | attr; + + /* + * Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0 + * table size is 16KB and has indices VA[31:20]. + * + * ref: Arch Ref. Manual for ARMv7-A, B3.5.4, + */ + ttbcr = read_ttbcr(); + ttbcr &= ~(0x3); + write_ttbcr(ttbcr); + + /* + * Translation table base 0 address is in bits 31:14-N, where N is given + * by bits 2:0 in TTBCR (which we set to 0). All lower bits in this + * register should be zero for coreboot. + */ + write_ttbr0(ttb_addr); + + /* disable domain-level checking of permissions */ + write_dacr(~0); +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 6193e63..041de70 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -47,7 +47,8 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c -romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c cbmem.c +romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-y += compute_ip_checksum.c romstage-y += memmove.c romstage-$(CONFIG_ARCH_X86) += gcc.c diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index bfb4156..ceffc65 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -74,6 +74,13 @@ static void graphics(void) exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } +/* for cbmem_initialize() */ +unsigned long get_top_of_ram(void); +unsigned long get_top_of_ram(void) +{ + return CONFIG_SYS_SDRAM_BASE + CONFIG_DRAM_SIZE_MB - 1UL; +} + void main(void) { struct mem_timings *mem; @@ -113,8 +120,9 @@ void main(void) while(1); } - /* Set up MMU and caches */ + /* Set up dcache and MMU */ mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + dcache_mmu_enable(); initialize_s5p_mshc();

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coreboot-gerrit March 2013