coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: a438ea8 Unify setting i82801e LPC
by gerrit＠coreboot.org 22 Mar '13

22 Mar '13

the following patch was just integrated into master: commit a438ea838e16ac4f3c2e7250ed2530671de4747d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting i82801e LPC Make it more similar to i82801d LPC init. Change-Id: I7b32747ee8012c220c8628994d749999c144b716 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/2545 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Feb 27 21:43:23 2013, giving +1 See http://review.coreboot.org/2545 for details. -gerrit

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Patch set updated for coreboot: d9c205c Intel i82801gx, bd82x6x: Enable PCI-to-PCI bridge
by Stefan Reinauer 22 Mar '13

22 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2706 -gerrit commit d9c205c5b9cd5755f897878f99ff9a4e0f08a084 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Mar 13 11:12:56 2013 +0200 Intel i82801gx, bd82x6x: Enable PCI-to-PCI bridge Once the PCI command register is written the bridge forwards future IO and memory regions, as programmed in the respective base and limit registers, to the secondary PCI bus. Since the LPC function claims the resources for IOAPIC, ROM and low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI configuration will not overlap those regions and does not hide the resources mentioned in the original comment. The bridge was disable in the following commit [1] commit a8e1168064b34b46494b58480411a11bc98340f6 Author: Stefan Reinauer <stepan(a)coresystems.de> Date: Wed Mar 11 14:54:18 2009 +0000 This patch contains some significant updates to the i82801gx component and will be required for a series of later patches. Roughly it contains: but unfortunately it was not noted which system this caused problems with. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b4… Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/bd82x6x/pci.c | 9 --------- src/southbridge/intel/i82801gx/pci.c | 9 --------- 2 files changed, 18 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 306e7d5..0f5f3f6 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -63,7 +63,6 @@ static void pci_init(struct device *dev) pci_write_config16(dev, SECSTS, reg16); } -#undef PCI_BRIDGE_UPDATE_COMMAND static void ich_pci_dev_enable_resources(struct device *dev) { const struct pci_operations *ops; @@ -83,16 +82,8 @@ static void ich_pci_dev_enable_resources(struct device *dev) command = pci_read_config16(dev, PCI_COMMAND); command |= dev->command; -#ifdef PCI_BRIDGE_UPDATE_COMMAND - /* If we write to PCI_COMMAND, on some systems - * this will cause the ROM and APICs not being visible - * anymore. - */ printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); pci_write_config16(dev, PCI_COMMAND, command); -#else - printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); -#endif } static void ich_pci_bus_enable_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 0f372e7..5a21b21 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -62,7 +62,6 @@ static void pci_init(struct device *dev) pci_write_config16(dev, SECSTS, reg16); } -#undef PCI_BRIDGE_UPDATE_COMMAND static void ich_pci_dev_enable_resources(struct device *dev) { const struct pci_operations *ops; @@ -80,16 +79,8 @@ static void ich_pci_dev_enable_resources(struct device *dev) command = pci_read_config16(dev, PCI_COMMAND); command |= dev->command; -#ifdef PCI_BRIDGE_UPDATE_COMMAND - /* If we write to PCI_COMMAND, on some systems - * this will cause the ROM and APICs not being visible - * anymore. - */ printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); pci_write_config16(dev, PCI_COMMAND, command); -#else - printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); -#endif } static void ich_pci_bus_enable_resources(struct device *dev)

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Patch set updated for coreboot: 2c7cd92 Drop add_mainboard_resources and HAVE_MAINBOARD_RESOURCES again
by Stefan Reinauer 22 Mar '13

22 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2707 -gerrit commit 2c7cd925836fce24b5fafc878ddd96209c96fb03 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Mar 13 11:44:39 2013 +0200 Drop add_mainboard_resources and HAVE_MAINBOARD_RESOURCES again These are not defined since commit »Drop HAVE_MAINBOARD_RESOURCES« (1c5071d1) [1] but were unfortunately introduced again in new ports. [1] http://review.coreboot.org/1414 Change-Id: I5eb61628141aefd08779615702d51ca155fa632a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/coreboot_tables.h | 4 ---- src/mainboard/google/butterfly/Kconfig | 1 - src/mainboard/google/link/Kconfig | 1 - src/mainboard/google/parrot/Kconfig | 1 - src/mainboard/supermicro/h8scm/mainboard.c | 7 ------- 5 files changed, 14 deletions(-) diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h index 4c2a013..d8955ba 100644 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ b/src/arch/armv7/include/arch/coreboot_tables.h @@ -21,8 +21,4 @@ struct lb_memory *get_lb_mem(void); extern struct cmos_option_table option_table; -/* defined by mainboard.c if the mainboard requires extra resources */ -int add_mainboard_resources(struct lb_memory *mem); -int add_northbridge_resources(struct lb_memory *mem); - #endif /* COREBOOT_TABLE_H */ diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 0813042..feafff0 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index c171390..db3bf32 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 96f1b4f..f1957e0 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/supermicro/h8scm/mainboard.c b/src/mainboard/supermicro/h8scm/mainboard.c index 819208c..23b1d72 100644 --- a/src/mainboard/supermicro/h8scm/mainboard.c +++ b/src/mainboard/supermicro/h8scm/mainboard.c @@ -72,13 +72,6 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } -#if CONFIG_HAVE_MAINBOARD_RESOURCES -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} -#endif - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, };

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Patch merged into coreboot/master: d1cc812 libpayload: Add comments on virtual pointers in lib_sysinfo
by gerrit＠coreboot.org 22 Mar '13

22 Mar '13

the following patch was just integrated into master: commit d1cc812799d3156888cd667d13f93bfa44c639c1 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Feb 8 12:39:28 2013 +0100 libpayload: Add comments on virtual pointers in lib_sysinfo After another incident related to virtual pointers in lib_sysinfo (and resulting confusion), I decided to put some comments on the matter into the code. Remember, we decided to always use virtual pointers in lib_sysinfo, but it's not always obvious from the code, that they are. See also: 425973c libpayload: Always use virtual pointers in struct sysinfo_t 593f577 libpayload: Fix use of virtual pointers in sysinfo Change-Id: I886c3b1d182cba07f1aab1667e702e2868ad4b68 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/2878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 22 09:59:27 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 22 16:20:07 2013, giving +2 See http://review.coreboot.org/2878 for details. -gerrit

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New patch to review for coreboot: 0c295ff libpayload: Add comments on virtual pointers in lib_sysinfo
by Nico Huber 22 Mar '13

22 Mar '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2878 -gerrit commit 0c295ff543873da0857dedf409b9d1a938a35795 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Feb 8 12:39:28 2013 +0100 libpayload: Add comments on virtual pointers in lib_sysinfo After another incident related to virtual pointers in lib_sysinfo (and resulting confusion), I decided to put some comments on the matter into the code. Remember, we decided to always use virtual pointers in lib_sysinfo, but it's not always obvious from the code, that they are. See also: 425973c libpayload: Always use virtual pointers in struct sysinfo_t 593f577 libpayload: Fix use of virtual pointers in sysinfo Change-Id: I886c3b1d182cba07f1aab1667e702e2868ad4b68 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/arch/armv7/coreboot.c | 2 ++ payloads/libpayload/arch/x86/coreboot.c | 2 ++ payloads/libpayload/include/sysinfo.h | 6 ++++++ 3 files changed, 10 insertions(+) diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/armv7/coreboot.c index 0003c29..9545f29 100644 --- a/payloads/libpayload/arch/armv7/coreboot.c +++ b/payloads/libpayload/arch/armv7/coreboot.c @@ -129,6 +129,7 @@ static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) #ifdef CONFIG_NVRAM static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { + /* ptr points to a coreboot table entry and is already virtual */ info->option_table = ptr; } @@ -144,6 +145,7 @@ static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) #ifdef CONFIG_COREBOOT_VIDEO_CONSOLE static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) { + /* ptr points to a coreboot table entry and is already virtual */ info->framebuffer = ptr; } #endif diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index e8bc380..f4f9b86 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -137,6 +137,7 @@ static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) #ifdef CONFIG_NVRAM static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { + /* ptr points to a coreboot table entry and is already virtual */ info->option_table = ptr; } @@ -152,6 +153,7 @@ static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) #ifdef CONFIG_COREBOOT_VIDEO_CONSOLE static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) { + /* ptr points to a coreboot table entry and is already virtual */ info->framebuffer = ptr; } #endif diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 4c7ce45..e05ef9f 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -39,6 +39,12 @@ struct cb_serial; +/* + * All pointers in here shall be virtual. + * + * If a relocation happens after the last call to lib_get_sysinfo(), + * it is up to the user to call lib_get_sysinfo() again. + */ struct sysinfo_t { unsigned int cpu_khz; struct cb_serial *serial;

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Patch set updated for coreboot: 2a04b2c armv7: add new dcache and MMU setup functions
by David Hendricks 22 Mar '13

22 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2877 -gerrit commit 2a04b2c5f49aee76ce29b544966cfc826af5d257 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 21 21:58:50 2013 -0700 armv7: add new dcache and MMU setup functions ** do not submit ** This is a work-in-progress patch. This adds new MMU setup code which uses cbmem_add() to determine the translation table base address, which in turn helps our payload to avoid clobbering the page table. Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/Kconfig | 1 + src/arch/armv7/bootblock_simple.c | 6 +- src/arch/armv7/include/arch/cache.h | 32 ++++++++++ src/arch/armv7/lib/Makefile.inc | 1 + src/arch/armv7/lib/cache.c | 29 ++++++--- src/arch/armv7/lib/mmu.c | 117 +++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 3 +- src/mainboard/google/snow/romstage.c | 10 ++- 8 files changed, 188 insertions(+), 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7a8985c..32db4bd 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -217,6 +217,7 @@ config ARCH_X86 config ARCH_ARMV7 bool default n + select EARLY_CBMEM_INIT # Warning: The file is included whether or not the if is here. # but the if controls how the evaluation occurs. diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index ad25b41..0a5d6c3 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -53,12 +53,14 @@ void main(void) armv7_invalidate_caches(); /* - * Re-enable caches and branch prediction. MMU will be set up later. + * Re-enable icache and branch prediction. Dcache and MMU will be + * set up in romstage along with DRAM. + * * Note: If booting from USB, we need to disable branch prediction * before copying from USB into RAM (FIXME: why?) */ sctlr = read_sctlr(); - sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I; + sctlr |= SCTLR_Z | SCTLR_I; write_sctlr(sctlr); if (boot_cpu()) { diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index c003256..1d7518f 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -108,6 +108,32 @@ static inline void tlbiall(void) asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); } +/* write data access control register (DACR) */ +static inline void write_dacr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val)); +} + +/* write translation table base register 0 (TTBR0) */ +static inline void write_ttbr0(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory"); +} + +/* read translation table base control register (TTBCR) */ +static inline uint32_t read_ttbcr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val)); + return val; +} + +/* write translation table base control register (TTBCR) */ +static inline void write_ttbcr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory"); +} + /* * Low-level cache maintenance operations */ @@ -224,6 +250,12 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* dcache and MMU disable */ +void dcache_mmu_disable(void); + +/* dcache and MMU enable */ +void dcache_mmu_enable(void); + /* icache invalidate all (on current level given by CSSELR) */ void icache_invalidate_all(void); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index c248b9e..de41f7f 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += cache-cp15.c romstage-y += cache.c romstage-y += cache_v7.c romstage-y += cache-cp15.c +romstage-y += mmu.c romstage-y += div0.c romstage-y += syslib.c romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 63e406c..2686db7 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -204,6 +204,28 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) dcache_op_mva(addr, len, OP_DCCIMVAC); } + +void dcache_mmu_disable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr &= ~(SCTLR_C | SCTLR_M); + write_sctlr(sctlr); +} + + +void dcache_mmu_enable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr |= SCTLR_C | SCTLR_M; + write_sctlr(sctlr); +} + void armv7_invalidate_caches(void) { uint32_t clidr; @@ -252,10 +274,3 @@ void armv7_invalidate_caches(void) /* Invalidate TLB */ tlb_invalidate_all(); } - -/* FIXME: wrapper around imported mmu_setup() for now */ -extern void mmu_setup(unsigned long start, unsigned long size); -void mmu_setup_by_mva(unsigned long start, unsigned long size) -{ - mmu_setup(start, size); -} diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c new file mode 100644 index 0000000..816ce41 --- /dev/null +++ b/src/arch/armv7/lib/mmu.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <types.h> +#include <stdlib.h> + +#include <cbmem.h> +#include <console/console.h> + +#include <arch/cache.h> + +/* FIXME: wrapper around imported mmu_setup() for now */ +#define L1_TLB_ENTRIES 4096 +//extern void mmu_setup(unsigned long start, unsigned long size); +void mmu_setup_by_mva(unsigned long dram_start_mb, unsigned long dram_size_mb) +{ + int i; + uintptr_t ttb_addr; + unsigned int ttb_size; + uint32_t *p; + unsigned int dram_page_start = dram_start_mb >> 20; + unsigned int num_dram_pages = dram_page_start + (dram_size_mb >> 20); + uint32_t attr; + uint32_t ttbcr; + + /* + * For coreboot's purposes, we will create a simple L1 page table + * in RAM with 1MB section translation entries over the 4GB address + * space. + * (ref: section 10.2 and example 15-4 in Cortex-A series + * programmer's guide) + * + * FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to + * 512 bytes. So add double the space in cbmem and fix-up the pointer. + */ + ttb_size = L1_TLB_ENTRIES * sizeof(int); + ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size * 2); + ttb_addr = ALIGN(ttb_addr + ttb_size, ttb_size); + p = (uint32_t *)ttb_addr; + + /* + * Section entry bits: + * 31:20 - section base address + * 18 - 0 to indicate normal section (versus supersection) + * 17 - nG, 0 to indicate page is global + * 16 - S, 0 for non-shareable (?) + * 15 - APX, 0 for full access + * 14:12 - TEX, 0b000 for outer and inner write-back + * 11:10 - AP, 0b11 for full access + * 9 - P, ? (FIXME: not described or possibly obsolete?) + * 8: 5 - Domain + * 4 - XN, 1 to set execute-never (and also avoid prefetches) + * 3 - C, 1 for cacheable + * 2 - B, 1 for bufferable + * 1: 0 - 0b10 to indicate section entry + */ + printk(BIOS_DEBUG, "%s: Writing page table @ to %p\n", __func__, p); + + /* Non-DRAM pages are non-cacheable */ + attr = (0x3 << 10) | (1 << 4) | 0x2; + for (i = 0; i < dram_page_start; i++) + p[i] = (i << 20) | attr; + + for (i = dram_page_start + num_dram_pages; i < L1_TLB_ENTRIES; i++) + p[i] = (i << 20) | attr; + + /* DRAM portion will be write-back for coreboot */ + attr = (0x3 << 10) | (1 << 4) | (1 << 3) | (1 << 2) | 0x2; + for (i = dram_page_start; i < num_dram_pages; i++) + p[i] = (i << 20) | attr; + + /* + * Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0 + * table size is 16KB and has indices VA[31:20]. + * + * ref: Arch Ref. Manual for ARMv7-A, B3.5.4, + */ + ttbcr = read_ttbcr(); + ttbcr &= ~(0x3); + write_ttbcr(ttbcr); + + /* + * Translation table base 0 address is in bits 31:14-N, where N is given + * by bits 2:0 in TTBCR (which we set to 0). All lower bits in this + * register should be zero for coreboot. + */ + write_ttbr0(ttb_addr); + + /* disable domain-level checking of permissions */ + write_dacr(~0); +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 97baaa2..2d79535 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -45,7 +45,8 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c -romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c cbmem.c +romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-y += compute_ip_checksum.c romstage-y += memmove.c romstage-$(CONFIG_ARCH_X86) += gcc.c diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index bfb4156..ceffc65 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -74,6 +74,13 @@ static void graphics(void) exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } +/* for cbmem_initialize() */ +unsigned long get_top_of_ram(void); +unsigned long get_top_of_ram(void) +{ + return CONFIG_SYS_SDRAM_BASE + CONFIG_DRAM_SIZE_MB - 1UL; +} + void main(void) { struct mem_timings *mem; @@ -113,8 +120,9 @@ void main(void) while(1); } - /* Set up MMU and caches */ + /* Set up dcache and MMU */ mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + dcache_mmu_enable(); initialize_s5p_mshc();

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New patch to review for coreboot: 0f4d4b8 armv7: add new dcache and MMU setup functions
by David Hendricks 22 Mar '13

22 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2877 -gerrit commit 0f4d4b8ff09c8ee1de5fb6a7a04d9077efbb6093 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 21 21:58:50 2013 -0700 armv7: add new dcache and MMU setup functions ** do not submit ** This is a work-in-progress patch. This adds new MMU setup code which uses cbmem_add() to determine the translation table base address. Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/Kconfig | 1 + src/arch/armv7/bootblock_simple.c | 6 +- src/arch/armv7/include/arch/cache.h | 32 ++++++++++ src/arch/armv7/lib/Makefile.inc | 1 + src/arch/armv7/lib/cache.c | 29 ++++++--- src/arch/armv7/lib/mmu.c | 117 +++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 3 +- src/mainboard/google/snow/romstage.c | 10 ++- 8 files changed, 188 insertions(+), 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7a8985c..32db4bd 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -217,6 +217,7 @@ config ARCH_X86 config ARCH_ARMV7 bool default n + select EARLY_CBMEM_INIT # Warning: The file is included whether or not the if is here. # but the if controls how the evaluation occurs. diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index ad25b41..0a5d6c3 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -53,12 +53,14 @@ void main(void) armv7_invalidate_caches(); /* - * Re-enable caches and branch prediction. MMU will be set up later. + * Re-enable icache and branch prediction. Dcache and MMU will be + * set up in romstage along with DRAM. + * * Note: If booting from USB, we need to disable branch prediction * before copying from USB into RAM (FIXME: why?) */ sctlr = read_sctlr(); - sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I; + sctlr |= SCTLR_Z | SCTLR_I; write_sctlr(sctlr); if (boot_cpu()) { diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index c003256..1d7518f 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -108,6 +108,32 @@ static inline void tlbiall(void) asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); } +/* write data access control register (DACR) */ +static inline void write_dacr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val)); +} + +/* write translation table base register 0 (TTBR0) */ +static inline void write_ttbr0(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory"); +} + +/* read translation table base control register (TTBCR) */ +static inline uint32_t read_ttbcr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val)); + return val; +} + +/* write translation table base control register (TTBCR) */ +static inline void write_ttbcr(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory"); +} + /* * Low-level cache maintenance operations */ @@ -224,6 +250,12 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* dcache and MMU disable */ +void dcache_mmu_disable(void); + +/* dcache and MMU enable */ +void dcache_mmu_enable(void); + /* icache invalidate all (on current level given by CSSELR) */ void icache_invalidate_all(void); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index c248b9e..de41f7f 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += cache-cp15.c romstage-y += cache.c romstage-y += cache_v7.c romstage-y += cache-cp15.c +romstage-y += mmu.c romstage-y += div0.c romstage-y += syslib.c romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 63e406c..2686db7 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -204,6 +204,28 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) dcache_op_mva(addr, len, OP_DCCIMVAC); } + +void dcache_mmu_disable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr &= ~(SCTLR_C | SCTLR_M); + write_sctlr(sctlr); +} + + +void dcache_mmu_enable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(); + dcache_clean_invalidate_all(); + sctlr |= SCTLR_C | SCTLR_M; + write_sctlr(sctlr); +} + void armv7_invalidate_caches(void) { uint32_t clidr; @@ -252,10 +274,3 @@ void armv7_invalidate_caches(void) /* Invalidate TLB */ tlb_invalidate_all(); } - -/* FIXME: wrapper around imported mmu_setup() for now */ -extern void mmu_setup(unsigned long start, unsigned long size); -void mmu_setup_by_mva(unsigned long start, unsigned long size) -{ - mmu_setup(start, size); -} diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c new file mode 100644 index 0000000..816ce41 --- /dev/null +++ b/src/arch/armv7/lib/mmu.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <types.h> +#include <stdlib.h> + +#include <cbmem.h> +#include <console/console.h> + +#include <arch/cache.h> + +/* FIXME: wrapper around imported mmu_setup() for now */ +#define L1_TLB_ENTRIES 4096 +//extern void mmu_setup(unsigned long start, unsigned long size); +void mmu_setup_by_mva(unsigned long dram_start_mb, unsigned long dram_size_mb) +{ + int i; + uintptr_t ttb_addr; + unsigned int ttb_size; + uint32_t *p; + unsigned int dram_page_start = dram_start_mb >> 20; + unsigned int num_dram_pages = dram_page_start + (dram_size_mb >> 20); + uint32_t attr; + uint32_t ttbcr; + + /* + * For coreboot's purposes, we will create a simple L1 page table + * in RAM with 1MB section translation entries over the 4GB address + * space. + * (ref: section 10.2 and example 15-4 in Cortex-A series + * programmer's guide) + * + * FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to + * 512 bytes. So add double the space in cbmem and fix-up the pointer. + */ + ttb_size = L1_TLB_ENTRIES * sizeof(int); + ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size * 2); + ttb_addr = ALIGN(ttb_addr + ttb_size, ttb_size); + p = (uint32_t *)ttb_addr; + + /* + * Section entry bits: + * 31:20 - section base address + * 18 - 0 to indicate normal section (versus supersection) + * 17 - nG, 0 to indicate page is global + * 16 - S, 0 for non-shareable (?) + * 15 - APX, 0 for full access + * 14:12 - TEX, 0b000 for outer and inner write-back + * 11:10 - AP, 0b11 for full access + * 9 - P, ? (FIXME: not described or possibly obsolete?) + * 8: 5 - Domain + * 4 - XN, 1 to set execute-never (and also avoid prefetches) + * 3 - C, 1 for cacheable + * 2 - B, 1 for bufferable + * 1: 0 - 0b10 to indicate section entry + */ + printk(BIOS_DEBUG, "%s: Writing page table @ to %p\n", __func__, p); + + /* Non-DRAM pages are non-cacheable */ + attr = (0x3 << 10) | (1 << 4) | 0x2; + for (i = 0; i < dram_page_start; i++) + p[i] = (i << 20) | attr; + + for (i = dram_page_start + num_dram_pages; i < L1_TLB_ENTRIES; i++) + p[i] = (i << 20) | attr; + + /* DRAM portion will be write-back for coreboot */ + attr = (0x3 << 10) | (1 << 4) | (1 << 3) | (1 << 2) | 0x2; + for (i = dram_page_start; i < num_dram_pages; i++) + p[i] = (i << 20) | attr; + + /* + * Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0 + * table size is 16KB and has indices VA[31:20]. + * + * ref: Arch Ref. Manual for ARMv7-A, B3.5.4, + */ + ttbcr = read_ttbcr(); + ttbcr &= ~(0x3); + write_ttbcr(ttbcr); + + /* + * Translation table base 0 address is in bits 31:14-N, where N is given + * by bits 2:0 in TTBCR (which we set to 0). All lower bits in this + * register should be zero for coreboot. + */ + write_ttbr0(ttb_addr); + + /* disable domain-level checking of permissions */ + write_dacr(~0); +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 97baaa2..2d79535 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -45,7 +45,8 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c -romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c cbmem.c +romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-y += compute_ip_checksum.c romstage-y += memmove.c romstage-$(CONFIG_ARCH_X86) += gcc.c diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index bfb4156..ceffc65 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -74,6 +74,13 @@ static void graphics(void) exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } +/* for cbmem_initialize() */ +unsigned long get_top_of_ram(void); +unsigned long get_top_of_ram(void) +{ + return CONFIG_SYS_SDRAM_BASE + CONFIG_DRAM_SIZE_MB - 1UL; +} + void main(void) { struct mem_timings *mem; @@ -113,8 +120,9 @@ void main(void) while(1); } - /* Set up MMU and caches */ + /* Set up dcache and MMU */ mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + dcache_mmu_enable(); initialize_s5p_mshc();

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Patch merged into coreboot/master: 57686f8 x86: unify amd and non-amd MTRR routines
by gerrit＠coreboot.org 22 Mar '13

22 Mar '13

the following patch was just integrated into master: commit 57686f848597f6b133c9d45a9b98a54638399b32 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 20 15:50:59 2013 -0500 x86: unify amd and non-amd MTRR routines The amd_mtrr.c file contains a copy of the fixed MTRR algorithm. However, the AMD code needs to handle the RdMem and WrMem attribute bits in the fixed MTRR MSRs. Instead of duplicating the code with the one slight change introduce a Kconfig option, X86_AMD_FIXED_MTRRS, which indicates that the RdMem and WrMem fields need to be handled for writeback fixed MTRR ranges. The order of how the AMD MTRR setup routine is maintained by providing a x86_setup_fixed_mtrrs_no_enable() function which does not enable the fixed MTRRs after setting them up. All Kconfig files which had a Makefile that included amd/mtrr in the subdirs-y now have a default X86_AMD_FIXED_MTRRS selection. There may be some overlap with the agesa and socket code, but I didn't know the best way to tease out the interdependency. Change-Id: I256d0210d1eb3004e2043b46374dcc0337432767 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2866 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Mar 22 04:04:23 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 22 03:38:09 2013, giving +2 See http://review.coreboot.org/2866 for details. -gerrit

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Patch merged into coreboot/master: c8eab2c Add support for ASUS F2A85-M board
by gerrit＠coreboot.org 22 Mar '13

22 Mar '13

the following patch was just integrated into master: commit c8eab2c0441851a141ef47d10022fb385d0eacad Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Wed Mar 20 21:43:50 2013 +0100 Add support for ASUS F2A85-M board The patch is based on Thatcher board. So far it boots Linux (3.2/3.7), internal network adapter works, AHCI works. External PCI/PCIe slots works too. Power management/ACPI seems to work. Internal VGA works with dumped ROM (VGA/DVI), but lacks GART. PCI pref devices are being relocated by Linux, reason unknown. This is a good start. USB and XHCI untested but visible. Change-Id: I1869aecb2634d548b00b3c9139517d6a0e0c9817 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Reviewed-on: http://review.coreboot.org/2038 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Mar 22 03:51:10 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 22 03:37:48 2013, giving +2 See http://review.coreboot.org/2038 for details. -gerrit

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Patch set updated for coreboot: 6c6f896 x86: unify amd and non-amd MTRR routines
by Stefan Reinauer 22 Mar '13

22 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2866 -gerrit commit 6c6f89696655f36bdb5ffa9d2c67600a4099f65b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 20 15:50:59 2013 -0500 x86: unify amd and non-amd MTRR routines The amd_mtrr.c file contains a copy of the fixed MTRR algorithm. However, the AMD code needs to handle the RdMem and WrMem attribute bits in the fixed MTRR MSRs. Instead of duplicating the code with the one slight change introduce a Kconfig option, X86_AMD_FIXED_MTRRS, which indicates that the RdMem and WrMem fields need to be handled for writeback fixed MTRR ranges. The order of how the AMD MTRR setup routine is maintained by providing a x86_setup_fixed_mtrrs_no_enable() function which does not enable the fixed MTRRs after setting them up. All Kconfig files which had a Makefile that included amd/mtrr in the subdirs-y now have a default X86_AMD_FIXED_MTRRS selection. There may be some overlap with the agesa and socket code, but I didn't know the best way to tease out the interdependency. Change-Id: I256d0210d1eb3004e2043b46374dcc0337432767 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/amd/agesa/family10/Kconfig | 1 + src/cpu/amd/agesa/family12/Kconfig | 1 + src/cpu/amd/agesa/family14/Kconfig | 1 + src/cpu/amd/agesa/family15/Kconfig | 1 + src/cpu/amd/agesa/family15tn/Kconfig | 1 + src/cpu/amd/mtrr/amd_mtrr.c | 111 +---------------------------------- src/cpu/amd/socket_754/Kconfig | 1 + src/cpu/amd/socket_939/Kconfig | 1 + src/cpu/amd/socket_940/Kconfig | 1 + src/cpu/amd/socket_AM2/Kconfig | 1 + src/cpu/amd/socket_AM2r2/Kconfig | 1 + src/cpu/amd/socket_AM3/Kconfig | 1 + src/cpu/amd/socket_ASB2/Kconfig | 1 + src/cpu/amd/socket_C32/Kconfig | 1 + src/cpu/amd/socket_F/Kconfig | 1 + src/cpu/amd/socket_F_1207/Kconfig | 1 + src/cpu/amd/socket_S1G1/Kconfig | 1 + src/cpu/x86/Kconfig | 7 +++ src/cpu/x86/mtrr/mtrr.c | 23 +++++--- src/include/cpu/x86/mtrr.h | 2 + 20 files changed, 43 insertions(+), 116 deletions(-) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index cb7b9a5..621ee58 100755 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -21,6 +21,7 @@ config CPU_AMD_AGESA_FAMILY10 bool select CPU_AMD_MODEL_10XXX select PCI_IO_CFG_EXT + select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 063e410..1adf5ec 100755 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -20,6 +20,7 @@ config CPU_AMD_AGESA_FAMILY12 bool select PCI_IO_CFG_EXT + select X86_AMD_FIXED_MTRRS config CPU_ADDR_BITS int diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 3c51bf0..dea839e 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -20,6 +20,7 @@ config CPU_AMD_AGESA_FAMILY14 bool select PCI_IO_CFG_EXT + select X86_AMD_FIXED_MTRRS config CPU_ADDR_BITS int diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 0afdab7..e20cce8 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -20,6 +20,7 @@ config CPU_AMD_AGESA_FAMILY15 bool select PCI_IO_CFG_EXT + select X86_AMD_FIXED_MTRRS config CPU_ADDR_BITS int diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index fba935a..d2f5a8c 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -20,6 +20,7 @@ config CPU_AMD_AGESA_FAMILY15_TN bool select PCI_IO_CFG_EXT + select X86_AMD_FIXED_MTRRS config CPU_ADDR_BITS int diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index bff6702..b804d49 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -6,102 +6,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -static unsigned long resk(uint64_t value) -{ - unsigned long resultk; - if (value < (1ULL << 42)) { - resultk = value >> 10; - } - else { - resultk = 0xffffffff; - } - return resultk; -} - -static unsigned fixed_mtrr_index(unsigned long addrk) -{ - unsigned index; - index = (addrk - 0) >> 6; - if (index >= 8) { - index = ((addrk - 8*64) >> 4) + 8; - } - if (index >= 24) { - index = ((addrk - (8*64 + 16*16)) >> 2) + 24; - } - if (index > NUM_FIXED_RANGES) { - index = NUM_FIXED_RANGES; - } - return index; -} - -static unsigned int mtrr_msr[] = { - MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, - MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR, - MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, -}; - -static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) -{ - unsigned int i; - unsigned int fixed_msr = NUM_FIXED_RANGES >> 3; - msr_t msr; - msr.lo = msr.hi = 0; /* Shut up gcc */ - for (i = first; i < last; i++) { - /* When I switch to a new msr read it in */ - if (fixed_msr != i >> 3) { - /* But first write out the old msr */ - if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { - disable_cache(); - wrmsr(mtrr_msr[fixed_msr], msr); - enable_cache(); - } - fixed_msr = i>>3; - msr = rdmsr(mtrr_msr[fixed_msr]); - } - if ((i & 7) < 4) { - msr.lo &= ~(0xff << ((i&3)*8)); - msr.lo |= type << ((i&3)*8); - } else { - msr.hi &= ~(0xff << ((i&3)*8)); - msr.hi |= type << ((i&3)*8); - } - } - /* Write out the final msr */ - if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { - disable_cache(); - wrmsr(mtrr_msr[fixed_msr], msr); - enable_cache(); - } -} - -struct mem_state { - unsigned long tomk, tom2k; -}; -static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res) -{ - struct mem_state *state = gp; - unsigned long topk; - unsigned int start_mtrr; - unsigned int last_mtrr; - - topk = resk(res->base + res->size); - if (state->tom2k < topk) { - state->tom2k = topk; - } - if ((topk < 4*1024*1024) && (state->tomk < topk)) { - state->tomk = topk; - } - start_mtrr = fixed_mtrr_index(resk(res->base)); - last_mtrr = fixed_mtrr_index(resk((res->base + res->size))); - if (start_mtrr >= NUM_FIXED_RANGES) { - return; - } - printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n", - start_mtrr, last_mtrr); - set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM); - -} - /* These will likely move to some device node or cbmem. */ static uint64_t amd_topmem = 0; static uint64_t amd_topmem2 = 0; @@ -162,7 +66,6 @@ static void setup_ap_ramtop(void) void amd_setup_mtrrs(void) { unsigned long address_bits; - struct mem_state state; unsigned long i; msr_t msr, sys_cfg; // Test if this CPU is a Fam 0Fh rev. F or later @@ -182,18 +85,8 @@ void amd_setup_mtrrs(void) wrmsr(SYSCFG_MSR, sys_cfg); enable_cache(); - printk(BIOS_DEBUG, "\n"); - /* Initialized the fixed_mtrrs to uncached */ - printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n", - 0, NUM_FIXED_RANGES); - set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); - - state.tomk = state.tom2k = 0; - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - set_fixed_mtrr_resource, &state); - - printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); + /* Setup fixed MTRRs, but do not enable them just yet. */ + x86_setup_fixed_mtrrs_no_enable(); disable_cache(); diff --git a/src/cpu/amd/socket_754/Kconfig b/src/cpu/amd/socket_754/Kconfig index 7a353a3..e77ac42 100644 --- a/src/cpu/amd/socket_754/Kconfig +++ b/src/cpu/amd/socket_754/Kconfig @@ -7,6 +7,7 @@ config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_AMD_MODEL_FXX select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS config CPU_ADDR_BITS int diff --git a/src/cpu/amd/socket_939/Kconfig b/src/cpu/amd/socket_939/Kconfig index 4546297..4c6cc2b 100644 --- a/src/cpu/amd/socket_939/Kconfig +++ b/src/cpu/amd/socket_939/Kconfig @@ -2,4 +2,5 @@ config CPU_AMD_SOCKET_939 bool select CPU_AMD_MODEL_FXX select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig index 2704876..051eadc 100644 --- a/src/cpu/amd/socket_940/Kconfig +++ b/src/cpu/amd/socket_940/Kconfig @@ -8,6 +8,7 @@ config SOCKET_SPECIFIC_OPTIONS select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS config CPU_ADDR_BITS int diff --git a/src/cpu/amd/socket_AM2/Kconfig b/src/cpu/amd/socket_AM2/Kconfig index 6849154..c8c79bb 100644 --- a/src/cpu/amd/socket_AM2/Kconfig +++ b/src/cpu/amd/socket_AM2/Kconfig @@ -5,6 +5,7 @@ config CPU_AMD_SOCKET_AM2 select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig index ae4d458..900bb2b 100644 --- a/src/cpu/amd/socket_AM2r2/Kconfig +++ b/src/cpu/amd/socket_AM2r2/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_SOCKET_AM2R2 select HT3_SUPPORT select PCI_IO_CFG_EXT select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig index ed656f1..a0e6593 100644 --- a/src/cpu/amd/socket_AM3/Kconfig +++ b/src/cpu/amd/socket_AM3/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_SOCKET_AM3 select HT3_SUPPORT select PCI_IO_CFG_EXT select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig index 7784a8d..dbd952c 100644 --- a/src/cpu/amd/socket_ASB2/Kconfig +++ b/src/cpu/amd/socket_ASB2/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_SOCKET_ASB2 select HT3_SUPPORT select PCI_IO_CFG_EXT select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig index db4b624..f8e441f 100644 --- a/src/cpu/amd/socket_C32/Kconfig +++ b/src/cpu/amd/socket_C32/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_SOCKET_C32_NON_AGESA select HT3_SUPPORT select PCI_IO_CFG_EXT select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_F/Kconfig b/src/cpu/amd/socket_F/Kconfig index 8514369..6d94f55 100644 --- a/src/cpu/amd/socket_F/Kconfig +++ b/src/cpu/amd/socket_F/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_SOCKET_F select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig index df98566..c80b5ed 100644 --- a/src/cpu/amd/socket_F_1207/Kconfig +++ b/src/cpu/amd/socket_F_1207/Kconfig @@ -3,6 +3,7 @@ config CPU_AMD_SOCKET_F_1207 select CPU_AMD_MODEL_10XXX select PCI_IO_CFG_EXT select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index b5090b9..2943b91 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -9,6 +9,7 @@ config SOCKET_SPECIFIC_OPTIONS select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX select CACHE_AS_RAM + select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE hex diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 62d78b5..8f05bf3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -84,3 +84,10 @@ config SMM_MODULE_HEAP_SIZE help This option determines the size of the heap within the SMM handler modules. + +config X86_AMD_FIXED_MTRRS + bool + default n + help + This option informs the MTRR code to use the RdMem and WrMem fields + in the fixed MTRR MSRs. diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 5051904..7076a7e 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -39,6 +39,12 @@ #include <cpu/x86/lapic.h> #include <arch/cpu.h> #include <arch/acpi.h> +#if CONFIG_X86_AMD_FIXED_MTRRS +#include <cpu/amd/mtrr.h> +#define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) +#else +#define MTRR_FIXED_WRBACK_BITS 0 +#endif static unsigned int mtrr_msr[] = { MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, @@ -325,6 +331,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc { unsigned int start_mtrr; unsigned int last_mtrr; + const unsigned char type = MTRR_TYPE_WRBACK | MTRR_FIXED_WRBACK_BITS; start_mtrr = fixed_mtrr_index(resk(res->base)); last_mtrr = fixed_mtrr_index(resk((res->base + res->size))); if (start_mtrr >= NUM_FIXED_RANGES) { @@ -332,7 +339,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc } printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n", start_mtrr, last_mtrr); - set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK); + set_fixed_mtrrs(start_mtrr, last_mtrr, type); } @@ -406,7 +413,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) state->range_sizek = sizek; } -void x86_setup_fixed_mtrrs(void) +void x86_setup_fixed_mtrrs_no_enable(void) { /* Try this the simple way of incrementally adding together * mtrrs. If this doesn't work out we can get smart again @@ -425,13 +432,17 @@ void x86_setup_fixed_mtrrs(void) IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_fixed_mtrr_resource, NULL); printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); +} - /* enable fixed MTRR */ - printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); - enable_fixed_mtrr(); +void x86_setup_fixed_mtrrs(void) +{ + x86_setup_fixed_mtrrs_no_enable(); + printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); + enable_fixed_mtrr(); } + void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) /* this routine needs to know how many address bits a given processor * supports. CPUs get grumpy when you set too many bits in @@ -500,7 +511,6 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) post_code(0x6A); } - void x86_setup_mtrrs(void) { int address_size; @@ -510,7 +520,6 @@ void x86_setup_mtrrs(void) x86_setup_var_mtrrs(address_size, 1); } - int x86_mtrr_check(void) { /* Only Pentium Pro and later have MTRR */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index dcb7075..fe85ad0 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -53,6 +53,8 @@ void x86_setup_mtrrs(void); int x86_mtrr_check(void); void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res); void x86_setup_fixed_mtrrs(void); +/* Set up fixed MTRRs but do not enable them. */ +void x86_setup_fixed_mtrrs_no_enable(void); #endif #if !defined(CONFIG_RAMTOP)

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coreboot-gerrit March 2013